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Merge tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: "Highlights: - ARM64 support for ACPI host bridges - new drivers for Axis ARTPEC-6 and Marvell Aardvark - new pci_alloc_irq_vectors() interface for MSI-X, MSI, legacy INTx - pci_resource_to_user() cleanup (more to come) Detailed summary: Enumeration: - Move ecam.h to linux/include/pci-ecam.h (Jayachandran C) - Add parent device field to ECAM struct pci_config_window (Jayachandran C) - Add generic MCFG table handling (Tomasz Nowicki) - Refactor pci_bus_assign_domain_nr() for CONFIG_PCI_DOMAINS_GENERIC (Tomasz Nowicki) - Factor DT-specific pci_bus_find_domain_nr() code out (Tomasz Nowicki) Resource management: - Add devm_request_pci_bus_resources() (Bjorn Helgaas) - Unify pci_resource_to_user() declarations (Bjorn Helgaas) - Implement pci_resource_to_user() with pcibios_resource_to_bus() (microblaze, powerpc, sparc) (Bjorn Helgaas) - Request host bridge window resources (designware, iproc, rcar, xgene, xilinx, xilinx-nwl) (Bjorn Helgaas) - Make PCI I/O space optional on ARM32 (Bjorn Helgaas) - Ignore write combining when mapping I/O port space (Bjorn Helgaas) - Claim bus resources on MIPS PCI_PROBE_ONLY set-ups (Bjorn Helgaas) - Remove unicore32 pci=firmware command line parameter handling (Bjorn Helgaas) - Support I/O resources when parsing host bridge resources (Jayachandran C) - Add helpers to request/release memory and I/O regions (Johannes Thumshirn) - Use pci_(request|release)_mem_regions (NVMe, lpfc, GenWQE, ethernet/intel, alx) (Johannes Thumshirn) - Extend pci=resource_alignment to specify device/vendor IDs (Koehrer Mathias (ETAS/ESW5)) - Add generic pci_bus_claim_resources() (Lorenzo Pieralisi) - Claim bus resources on ARM32 PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi) - Remove ARM32 and ARM64 arch-specific pcibios_enable_device() (Lorenzo Pieralisi) - Add pci_unmap_iospace() to unmap I/O resources (Sinan Kaya) - Remove powerpc __pci_mmap_set_pgprot() (Yinghai Lu) PCI device hotplug: - Allow additional bus numbers for hotplug bridges (Keith Busch) - Ignore interrupts during D3cold (Lukas Wunner) Power management: - Enforce type casting for pci_power_t (Andy Shevchenko) - Don't clear d3cold_allowed for PCIe ports (Mika Westerberg) - Put PCIe ports into D3 during suspend (Mika Westerberg) - Power on bridges before scanning new devices (Mika Westerberg) - Runtime resume bridge before rescan (Mika Westerberg) - Add runtime PM support for PCIe ports (Mika Westerberg) - Remove redundant check of pcie_set_clkpm (Shawn Lin) Virtualization: - Add function 1 DMA alias quirk for Marvell 88SE9182 (Aaron Sierra) - Add DMA alias quirk for Adaptec 3805 (Alex Williamson) - Mark Atheros AR9485 and QCA9882 to avoid bus reset (Chris Blake) - Add ACS quirk for Solarflare SFC9220 (Edward Cree) MSI: - Fix PCI_MSI dependencies (Arnd Bergmann) - Add pci_msix_desc_addr() helper (Christoph Hellwig) - Switch msix_program_entries() to use pci_msix_desc_addr() (Christoph Hellwig) - Make the "entries" argument to pci_enable_msix() optional (Christoph Hellwig) - Provide sensible IRQ vector alloc/free routines (Christoph Hellwig) - Spread interrupt vectors in pci_alloc_irq_vectors() (Christoph Hellwig) Error Handling: - Bind DPC to Root Ports as well as Downstream Ports (Keith Busch) - Remove DPC tristate module option (Keith Busch) - Convert Downstream Port Containment driver to use devm_* functions (Mika Westerberg) Generic host bridge driver: - Select IRQ_DOMAIN (Arnd Bergmann) - Claim bus resources on PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi) ACPI host bridge driver: - Add ARM64 acpi_pci_bus_find_domain_nr() (Tomasz Nowicki) - Add ARM64 ACPI support for legacy IRQs parsing and consolidation with DT code (Tomasz Nowicki) - Implement ARM64 AML accessors for PCI_Config region (Tomasz Nowicki) - Support ARM64 ACPI-based PCI host controller (Tomasz Nowicki) Altera host bridge driver: - Check link status before retrain link (Ley Foon Tan) - Poll for link up status after retraining the link (Ley Foon Tan) Axis ARTPEC-6 host bridge driver: - Add PCI_MSI_IRQ_DOMAIN dependency (Arnd Bergmann) - Add DT binding for Axis ARTPEC-6 PCIe controller (Niklas Cassel) - Add Axis ARTPEC-6 PCIe controller driver (Niklas Cassel) Intel VMD host bridge driver: - Use lock save/restore in interrupt enable path (Jon Derrick) - Select device dma ops to override (Keith Busch) - Initialize list item in IRQ disable (Keith Busch) - Use x86_vector_domain as parent domain (Keith Busch) - Separate MSI and MSI-X vector sharing (Keith Busch) Marvell Aardvark host bridge driver: - Add DT binding for the Aardvark PCIe controller (Thomas Petazzoni) - Add Aardvark PCI host controller driver (Thomas Petazzoni) - Add Aardvark PCIe support for Armada 3700 (Thomas Petazzoni) Microsoft Hyper-V host bridge driver: - Fix interrupt cleanup path (Cathy Avery) - Don't leak buffer in hv_pci_onchannelcallback() (Vitaly Kuznetsov) - Handle all pending messages in hv_pci_onchannelcallback() (Vitaly Kuznetsov) NVIDIA Tegra host bridge driver: - Program PADS_REFCLK_CFG* always, not just on legacy SoCs (Stephen Warren) - Program PADS_REFCLK_CFG* registers with per-SoC values (Stephen Warren) - Use lower-case hex consistently for register definitions (Thierry Reding) - Use generic pci_remap_iospace() rather than ARM32-specific one (Thierry Reding) - Stop setting pcibios_min_mem (Thierry Reding) Renesas R-Car host bridge driver: - Drop gen2 dummy I/O port region (Bjorn Helgaas) TI DRA7xx host bridge driver: - Fix return value in case of error (Christophe JAILLET) Xilinx AXI host bridge driver: - Fix return value in case of error (Christophe JAILLET) Miscellaneous: - Make bus_attr_resource_alignment static (Ben Dooks) - Include <asm/dma.h> for isa_dma_bridge_buggy (Ben Dooks) - MAINTAINERS: Add file patterns for PCI device tree bindings (Geert Uytterhoeven) - Make host bridge drivers explicitly non-modular (Paul Gortmaker)" * tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (125 commits) PCI: xgene: Make explicitly non-modular PCI: thunder-pem: Make explicitly non-modular PCI: thunder-ecam: Make explicitly non-modular PCI: tegra: Make explicitly non-modular PCI: rcar-gen2: Make explicitly non-modular PCI: rcar: Make explicitly non-modular PCI: mvebu: Make explicitly non-modular PCI: layerscape: Make explicitly non-modular PCI: keystone: Make explicitly non-modular PCI: hisi: Make explicitly non-modular PCI: generic: Make explicitly non-modular PCI: designware-plat: Make it explicitly non-modular PCI: artpec6: Make explicitly non-modular PCI: armada8k: Make explicitly non-modular PCI: artpec: Add PCI_MSI_IRQ_DOMAIN dependency PCI: Add ACS quirk for Solarflare SFC9220 arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700 PCI: aardvark: Add Aardvark PCI host controller driver dt-bindings: add DT binding for the Aardvark PCIe controller PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values ...
This commit is contained in:
Linus Torvalds
+79
-390
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Load Diff
@@ -0,0 +1,56 @@
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Aardvark PCIe controller
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This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
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The Device Tree node describing an Aardvark PCIe controller must
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contain the following properties:
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- compatible: Should be "marvell,armada-3700-pcie"
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- reg: range of registers for the PCIe controller
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- interrupts: the interrupt line of the PCIe controller
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- msi-controller: indicates that the PCIe controller can itself
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handle MSI interrupts
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- msi-parent: pointer to the MSI controller to be used
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- interrupt-map-mask and interrupt-map: standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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- bus-range: PCI bus numbers covered
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In addition, the Device Tree describing an Aardvark PCIe controller
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must include a sub-node that describes the legacy interrupt controller
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built into the PCIe controller. This sub-node must have the following
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properties:
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- interrupt-controller
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- #interrupt-cells: set to <1>
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Example:
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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device_type = "pci";
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status = "disabled";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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msi-controller;
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msi-parent = <&pcie0>;
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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@@ -0,0 +1,46 @@
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* Axis ARTPEC-6 PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
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- reg: base addresses and lengths of the PCIe controller (DBI),
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the phy controller, and configuration address space.
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- reg-names: Must include the following entries:
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- "dbi"
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- "phy"
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- "config"
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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- "msi": The interrupt that is asserted when an MSI is received
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- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
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used to enable and control the Synopsys IP.
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Example:
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pcie@f8050000 {
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compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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reg = <0xf8050000 0x2000
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0xf8040000 0x1000
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0xc0000000 0x1000>;
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reg-names = "dbi", "phy", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* downstream I/O */
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ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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axis,syscon-pcie = <&syscon>;
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};
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@@ -3021,6 +3021,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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resource_alignment=
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Format:
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[<order of align>@][<domain>:]<bus>:<slot>.<func>[; ...]
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[<order of align>@]pci:<vendor>:<device>\
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[:<subvendor>:<subdevice>][; ...]
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Specifies alignment and device to reassign
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aligned memory resources.
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If <order of align> is not specified,
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@@ -3039,6 +3041,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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hpmemsize=nn[KMG] The fixed amount of bus space which is
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reserved for hotplug bridge's memory window.
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Default size is 2 megabytes.
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hpbussize=nn The minimum amount of additional bus numbers
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reserved for buses below a hotplug bridge.
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Default is 1.
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realloc= Enable/disable reallocating PCI bridge resources
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if allocations done by BIOS are too small to
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accommodate resources required by all child
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@@ -3070,6 +3075,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe
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ports driver.
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pcie_port_pm= [PCIE] PCIe port power management handling:
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off Disable power management of all PCIe ports
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force Forcibly enable power management of all PCIe ports
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pcie_pme= [PCIE,PM] Native PCIe PME signaling options:
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nomsi Do not use MSI for native PCIe PME signaling (this makes
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all PCIe root ports use INTx for all services).
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+17
@@ -8883,6 +8883,7 @@ L: linux-pci@vger.kernel.org
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Q: http://patchwork.ozlabs.org/project/linux-pci/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
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S: Supported
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F: Documentation/devicetree/bindings/pci/
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F: Documentation/PCI/
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F: drivers/pci/
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F: include/linux/pci*
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@@ -8946,6 +8947,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/pci/host/*mvebu*
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PCI DRIVER FOR AARDVARK (Marvell Armada 3700)
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M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/pci/host/pci-aardvark.c
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PCI DRIVER FOR NVIDIA TEGRA
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M: Thierry Reding <thierry.reding@gmail.com>
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L: linux-tegra@vger.kernel.org
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@@ -9028,6 +9036,15 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
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F: drivers/pci/host/pci-xgene-msi.c
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PCIE DRIVER FOR AXIS ARTPEC
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M: Niklas Cassel <niklas.cassel@axis.com>
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M: Jesper Nilsson <jesper.nilsson@axis.com>
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L: linux-arm-kernel@axis.com
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/axis,artpec*
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F: drivers/pci/host/*artpec*
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PCIE DRIVER FOR HISILICON
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M: Zhou Wang <wangzhou1@hisilicon.com>
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M: Gabriele Paoloni <gabriele.paoloni@huawei.com>
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+1
-1
@@ -700,7 +700,7 @@ config ARCH_VIRT
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depends on ARCH_MULTI_V7
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select ARM_AMBA
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select ARM_GIC
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select ARM_GIC_V2M if PCI_MSI
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select ARM_GIC_V2M if PCI
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select ARM_GIC_V3
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select ARM_PSCI
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select HAVE_ARM_ARCH_TIMER
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@@ -22,6 +22,7 @@ struct hw_pci {
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struct msi_controller *msi_ctrl;
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struct pci_ops *ops;
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int nr_controllers;
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unsigned int io_optional:1;
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void **private_data;
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int (*setup)(int nr, struct pci_sys_data *);
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struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
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+20
-25
@@ -410,7 +410,8 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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return irq;
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}
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static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
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static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,
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int io_optional)
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{
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int ret;
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struct resource_entry *window;
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@@ -420,6 +421,14 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
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&iomem_resource, sys->mem_offset);
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}
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/*
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* If a platform says I/O port support is optional, we don't add
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* the default I/O space. The platform is responsible for adding
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* any I/O space it needs.
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*/
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if (io_optional)
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return 0;
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resource_list_for_each_entry(window, &sys->resources)
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if (resource_type(window->res) == IORESOURCE_IO)
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return 0;
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@@ -466,7 +475,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
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if (ret > 0) {
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struct pci_host_bridge *host_bridge;
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ret = pcibios_init_resources(nr, sys);
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ret = pcibios_init_resource(nr, sys, hw->io_optional);
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if (ret) {
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kfree(sys);
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break;
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@@ -515,25 +524,23 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
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list_for_each_entry(sys, &head, node) {
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struct pci_bus *bus = sys->bus;
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if (!pci_has_flag(PCI_PROBE_ONLY)) {
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/*
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* We insert PCI resources into the iomem_resource and
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* ioport_resource trees in either pci_bus_claim_resources()
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* or pci_bus_assign_resources().
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*/
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if (pci_has_flag(PCI_PROBE_ONLY)) {
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pci_bus_claim_resources(bus);
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} else {
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struct pci_bus *child;
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/*
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* Size the bridge windows.
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*/
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pci_bus_size_bridges(bus);
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/*
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* Assign resources.
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*/
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pci_bus_assign_resources(bus);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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}
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/*
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* Tell drivers about devices found.
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*/
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pci_bus_add_devices(bus);
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}
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}
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@@ -590,18 +597,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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return start;
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}
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/**
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* pcibios_enable_device - Enable I/O and memory.
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* @dev: PCI device to be enabled
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*/
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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if (pci_has_flag(PCI_PROBE_ONLY))
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return 0;
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return pci_enable_resources(dev, mask);
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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+4
-2
@@ -3,6 +3,7 @@ config ARM64
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select ACPI_CCA_REQUIRED if ACPI
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select ACPI_GENERIC_GSI if ACPI
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select ACPI_REDUCED_HARDWARE_ONLY if ACPI
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select ACPI_MCFG if ACPI
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select ARCH_HAS_DEVMEM_IS_ALLOWED
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select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
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select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
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@@ -22,9 +23,9 @@ config ARM64
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select ARM_ARCH_TIMER
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select ARM_GIC
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select AUDIT_ARCH_COMPAT_GENERIC
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select ARM_GIC_V2M if PCI_MSI
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select ARM_GIC_V2M if PCI
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS if PCI_MSI
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select ARM_GIC_V3_ITS if PCI
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select ARM_PSCI_FW
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select BUILDTIME_EXTABLE_SORT
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select CLONE_BACKWARDS
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@@ -102,6 +103,7 @@ config ARM64
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select OF_EARLY_FLATTREE
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select OF_NUMA if NUMA && OF
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select OF_RESERVED_MEM
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select PCI_ECAM if ACPI
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select PERF_USE_VMALLOC
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select POWER_RESET
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select POWER_SUPPLY
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||||
|
||||
@@ -76,3 +76,8 @@
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON17 (PCIe) / CON12 (mini-PCIe) */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -176,5 +176,30 @@
|
||||
<0x1d40000 0x40000>; /* GICR */
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@d0070000 {
|
||||
compatible = "marvell,armada-3700-pcie";
|
||||
device_type = "pci";
|
||||
status = "disabled";
|
||||
reg = <0 0xd0070000 0 0x20000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
|
||||
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
+138
-21
@@ -17,6 +17,9 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-acpi.h>
|
||||
#include <linux/pci-ecam.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
/*
|
||||
@@ -36,25 +39,17 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
|
||||
return res->start;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcibios_enable_device - Enable I/O and memory.
|
||||
* @dev: PCI device to be enabled
|
||||
* @mask: bitmask of BARs to enable
|
||||
*/
|
||||
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
||||
{
|
||||
if (pci_has_flag(PCI_PROBE_ONLY))
|
||||
return 0;
|
||||
|
||||
return pci_enable_resources(dev, mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Try to assign the IRQ number from DT when adding a new device
|
||||
* Try to assign the IRQ number when probing a new device
|
||||
*/
|
||||
int pcibios_add_device(struct pci_dev *dev)
|
||||
int pcibios_alloc_irq(struct pci_dev *dev)
|
||||
{
|
||||
dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
|
||||
if (acpi_disabled)
|
||||
dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
|
||||
#ifdef CONFIG_ACPI
|
||||
else
|
||||
return acpi_pci_irq_enable(dev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -65,13 +60,21 @@ int pcibios_add_device(struct pci_dev *dev)
|
||||
int raw_pci_read(unsigned int domain, unsigned int bus,
|
||||
unsigned int devfn, int reg, int len, u32 *val)
|
||||
{
|
||||
return -ENXIO;
|
||||
struct pci_bus *b = pci_find_bus(domain, bus);
|
||||
|
||||
if (!b)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
return b->ops->read(b, devfn, reg, len, val);
|
||||
}
|
||||
|
||||
int raw_pci_write(unsigned int domain, unsigned int bus,
|
||||
unsigned int devfn, int reg, int len, u32 val)
|
||||
{
|
||||
return -ENXIO;
|
||||
struct pci_bus *b = pci_find_bus(domain, bus);
|
||||
|
||||
if (!b)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
return b->ops->write(b, devfn, reg, len, val);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NUMA
|
||||
@@ -85,10 +88,124 @@ EXPORT_SYMBOL(pcibus_to_node);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
/* Root bridge scanning */
|
||||
|
||||
struct acpi_pci_generic_root_info {
|
||||
struct acpi_pci_root_info common;
|
||||
struct pci_config_window *cfg; /* config space mapping */
|
||||
};
|
||||
|
||||
int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_config_window *cfg = bus->sysdata;
|
||||
struct acpi_device *adev = to_acpi_device(cfg->parent);
|
||||
struct acpi_pci_root *root = acpi_driver_data(adev);
|
||||
|
||||
return root->segment;
|
||||
}
|
||||
|
||||
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
|
||||
{
|
||||
if (!acpi_disabled) {
|
||||
struct pci_config_window *cfg = bridge->bus->sysdata;
|
||||
struct acpi_device *adev = to_acpi_device(cfg->parent);
|
||||
ACPI_COMPANION_SET(&bridge->dev, adev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Lookup the bus range for the domain in MCFG, and set up config space
|
||||
* mapping.
|
||||
*/
|
||||
static struct pci_config_window *
|
||||
pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)
|
||||
{
|
||||
struct resource *bus_res = &root->secondary;
|
||||
u16 seg = root->segment;
|
||||
struct pci_config_window *cfg;
|
||||
struct resource cfgres;
|
||||
unsigned int bsz;
|
||||
|
||||
/* Use address from _CBA if present, otherwise lookup MCFG */
|
||||
if (!root->mcfg_addr)
|
||||
root->mcfg_addr = pci_mcfg_lookup(seg, bus_res);
|
||||
|
||||
if (!root->mcfg_addr) {
|
||||
dev_err(&root->device->dev, "%04x:%pR ECAM region not found\n",
|
||||
seg, bus_res);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
bsz = 1 << pci_generic_ecam_ops.bus_shift;
|
||||
cfgres.start = root->mcfg_addr + bus_res->start * bsz;
|
||||
cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;
|
||||
cfgres.flags = IORESOURCE_MEM;
|
||||
cfg = pci_ecam_create(&root->device->dev, &cfgres, bus_res,
|
||||
&pci_generic_ecam_ops);
|
||||
if (IS_ERR(cfg)) {
|
||||
dev_err(&root->device->dev, "%04x:%pR error %ld mapping ECAM\n",
|
||||
seg, bus_res, PTR_ERR(cfg));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return cfg;
|
||||
}
|
||||
|
||||
/* release_info: free resources allocated by init_info */
|
||||
static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci)
|
||||
{
|
||||
struct acpi_pci_generic_root_info *ri;
|
||||
|
||||
ri = container_of(ci, struct acpi_pci_generic_root_info, common);
|
||||
pci_ecam_free(ri->cfg);
|
||||
kfree(ri);
|
||||
}
|
||||
|
||||
static struct acpi_pci_root_ops acpi_pci_root_ops = {
|
||||
.release_info = pci_acpi_generic_release_info,
|
||||
};
|
||||
|
||||
/* Interface called from ACPI code to setup PCI host controller */
|
||||
struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
|
||||
{
|
||||
/* TODO: Should be revisited when implementing PCI on ACPI */
|
||||
return NULL;
|
||||
int node = acpi_get_node(root->device->handle);
|
||||
struct acpi_pci_generic_root_info *ri;
|
||||
struct pci_bus *bus, *child;
|
||||
|
||||
ri = kzalloc_node(sizeof(*ri), GFP_KERNEL, node);
|
||||
if (!ri)
|
||||
return NULL;
|
||||
|
||||
ri->cfg = pci_acpi_setup_ecam_mapping(root);
|
||||
if (!ri->cfg) {
|
||||
kfree(ri);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
acpi_pci_root_ops.pci_ops = &ri->cfg->ops->pci_ops;
|
||||
bus = acpi_pci_root_create(root, &acpi_pci_root_ops, &ri->common,
|
||||
ri->cfg);
|
||||
if (!bus)
|
||||
return NULL;
|
||||
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
|
||||
list_for_each_entry(child, &bus->children, node)
|
||||
pcie_bus_configure_settings(child);
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
void pcibios_add_bus(struct pci_bus *bus)
|
||||
{
|
||||
acpi_pci_add_bus(bus);
|
||||
}
|
||||
|
||||
void pcibios_remove_bus(struct pci_bus *bus)
|
||||
{
|
||||
acpi_pci_remove_bus(bus);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -82,9 +82,6 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
|
||||
pgprot_t prot);
|
||||
|
||||
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc,
|
||||
resource_size_t *start, resource_size_t *end);
|
||||
|
||||
extern void pcibios_setup_bus_devices(struct pci_bus *bus);
|
||||
extern void pcibios_setup_bus_self(struct pci_bus *bus);
|
||||
|
||||
@@ -218,33 +218,6 @@ static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
|
||||
* device mapping.
|
||||
*/
|
||||
static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
|
||||
pgprot_t protection,
|
||||
enum pci_mmap_state mmap_state,
|
||||
int write_combine)
|
||||
{
|
||||
pgprot_t prot = protection;
|
||||
|
||||
/* Write combine is always 0 on non-memory space mappings. On
|
||||
* memory space, if the user didn't pass 1, we check for a
|
||||
* "prefetchable" resource. This is a bit hackish, but we use
|
||||
* this to workaround the inability of /sysfs to provide a write
|
||||
* combine bit
|
||||
*/
|
||||
if (mmap_state != pci_mmap_mem)
|
||||
write_combine = 0;
|
||||
else if (write_combine == 0) {
|
||||
if (rp->flags & IORESOURCE_PREFETCH)
|
||||
write_combine = 1;
|
||||
}
|
||||
|
||||
return pgprot_noncached(prot);
|
||||
}
|
||||
|
||||
/*
|
||||
* This one is used by /dev/mem and fbdev who have no clue about the
|
||||
* PCI device, it tries to find the PCI device first and calls the
|
||||
@@ -317,9 +290,7 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
return -EINVAL;
|
||||
|
||||
vma->vm_pgoff = offset >> PAGE_SHIFT;
|
||||
vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
|
||||
vma->vm_page_prot,
|
||||
mmap_state, write_combine);
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
|
||||
ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
|
||||
vma->vm_end - vma->vm_start, vma->vm_page_prot);
|
||||
@@ -473,39 +444,25 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc,
|
||||
resource_size_t *start, resource_size_t *end)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(dev->bus);
|
||||
resource_size_t offset = 0;
|
||||
struct pci_bus_region region;
|
||||
|
||||
if (hose == NULL)
|
||||
if (rsrc->flags & IORESOURCE_IO) {
|
||||
pcibios_resource_to_bus(dev->bus, ®ion,
|
||||
(struct resource *) rsrc);
|
||||
*start = region.start;
|
||||
*end = region.end;
|
||||
return;
|
||||
}
|
||||
|
||||
if (rsrc->flags & IORESOURCE_IO)
|
||||
offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
||||
|
||||
/* We pass a fully fixed up address to userland for MMIO instead of
|
||||
* a BAR value because X is lame and expects to be able to use that
|
||||
* to pass to /dev/mem !
|
||||
/* We pass a CPU physical address to userland for MMIO instead of a
|
||||
* BAR value because X is lame and expects to be able to use that
|
||||
* to pass to /dev/mem!
|
||||
*
|
||||
* That means that we'll have potentially 64 bits values where some
|
||||
* userland apps only expect 32 (like X itself since it thinks only
|
||||
* Sparc has 64 bits MMIO) but if we don't do that, we break it on
|
||||
* 32 bits CHRPs :-(
|
||||
*
|
||||
* Hopefully, the sysfs insterface is immune to that gunk. Once X
|
||||
* has been fixed (and the fix spread enough), we can re-enable the
|
||||
* 2 lines below and pass down a BAR value to userland. In that case
|
||||
* we'll also have to re-enable the matching code in
|
||||
* __pci_mmap_make_offset().
|
||||
*
|
||||
* BenH.
|
||||
* That means we may have 64-bit values where some apps only expect
|
||||
* 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
|
||||
*/
|
||||
#if 0
|
||||
else if (rsrc->flags & IORESOURCE_MEM)
|
||||
offset = hose->pci_mem_offset;
|
||||
#endif
|
||||
|
||||
*start = rsrc->start - offset;
|
||||
*end = rsrc->end - offset;
|
||||
*start = rsrc->start;
|
||||
*end = rsrc->end;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -80,16 +80,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
|
||||
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
|
||||
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc, resource_size_t *start,
|
||||
resource_size_t *end)
|
||||
{
|
||||
phys_addr_t size = resource_size(rsrc);
|
||||
|
||||
*start = fixup_bigphys_addr(rsrc->start, size);
|
||||
*end = rsrc->start + size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dynamic DMA mapping stuff.
|
||||
* MIPS has everything mapped statically.
|
||||
|
||||
+18
-1
@@ -112,7 +112,14 @@ static void pcibios_scanbus(struct pci_controller *hose)
|
||||
need_domain_info = 1;
|
||||
}
|
||||
|
||||
if (!pci_has_flag(PCI_PROBE_ONLY)) {
|
||||
/*
|
||||
* We insert PCI resources into the iomem_resource and
|
||||
* ioport_resource trees in either pci_bus_claim_resources()
|
||||
* or pci_bus_assign_resources().
|
||||
*/
|
||||
if (pci_has_flag(PCI_PROBE_ONLY)) {
|
||||
pci_bus_claim_resources(bus);
|
||||
} else {
|
||||
pci_bus_size_bridges(bus);
|
||||
pci_bus_assign_resources(bus);
|
||||
}
|
||||
@@ -319,6 +326,16 @@ void pcibios_fixup_bus(struct pci_bus *bus)
|
||||
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
|
||||
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
|
||||
|
||||
void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc, resource_size_t *start,
|
||||
resource_size_t *end)
|
||||
{
|
||||
phys_addr_t size = resource_size(rsrc);
|
||||
|
||||
*start = fixup_bigphys_addr(rsrc->start, size);
|
||||
*end = rsrc->start + size;
|
||||
}
|
||||
|
||||
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
enum pci_mmap_state mmap_state, int write_combine)
|
||||
{
|
||||
|
||||
@@ -136,9 +136,6 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
|
||||
pgprot_t prot);
|
||||
|
||||
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc,
|
||||
resource_size_t *start, resource_size_t *end);
|
||||
|
||||
extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
|
||||
extern void pcibios_setup_bus_devices(struct pci_bus *bus);
|
||||
|
||||
@@ -411,36 +411,6 @@ static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
|
||||
* device mapping.
|
||||
*/
|
||||
static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
|
||||
pgprot_t protection,
|
||||
enum pci_mmap_state mmap_state,
|
||||
int write_combine)
|
||||
{
|
||||
|
||||
/* Write combine is always 0 on non-memory space mappings. On
|
||||
* memory space, if the user didn't pass 1, we check for a
|
||||
* "prefetchable" resource. This is a bit hackish, but we use
|
||||
* this to workaround the inability of /sysfs to provide a write
|
||||
* combine bit
|
||||
*/
|
||||
if (mmap_state != pci_mmap_mem)
|
||||
write_combine = 0;
|
||||
else if (write_combine == 0) {
|
||||
if (rp->flags & IORESOURCE_PREFETCH)
|
||||
write_combine = 1;
|
||||
}
|
||||
|
||||
/* XXX would be nice to have a way to ask for write-through */
|
||||
if (write_combine)
|
||||
return pgprot_noncached_wc(protection);
|
||||
else
|
||||
return pgprot_noncached(protection);
|
||||
}
|
||||
|
||||
/*
|
||||
* This one is used by /dev/mem and fbdev who have no clue about the
|
||||
* PCI device, it tries to find the PCI device first and calls the
|
||||
@@ -514,9 +484,10 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
return -EINVAL;
|
||||
|
||||
vma->vm_pgoff = offset >> PAGE_SHIFT;
|
||||
vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
|
||||
vma->vm_page_prot,
|
||||
mmap_state, write_combine);
|
||||
if (write_combine)
|
||||
vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
|
||||
else
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
|
||||
ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
|
||||
vma->vm_end - vma->vm_start, vma->vm_page_prot);
|
||||
@@ -666,39 +637,25 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc,
|
||||
resource_size_t *start, resource_size_t *end)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(dev->bus);
|
||||
resource_size_t offset = 0;
|
||||
struct pci_bus_region region;
|
||||
|
||||
if (hose == NULL)
|
||||
if (rsrc->flags & IORESOURCE_IO) {
|
||||
pcibios_resource_to_bus(dev->bus, ®ion,
|
||||
(struct resource *) rsrc);
|
||||
*start = region.start;
|
||||
*end = region.end;
|
||||
return;
|
||||
}
|
||||
|
||||
if (rsrc->flags & IORESOURCE_IO)
|
||||
offset = (unsigned long)hose->io_base_virt - _IO_BASE;
|
||||
|
||||
/* We pass a fully fixed up address to userland for MMIO instead of
|
||||
* a BAR value because X is lame and expects to be able to use that
|
||||
* to pass to /dev/mem !
|
||||
/* We pass a CPU physical address to userland for MMIO instead of a
|
||||
* BAR value because X is lame and expects to be able to use that
|
||||
* to pass to /dev/mem!
|
||||
*
|
||||
* That means that we'll have potentially 64 bits values where some
|
||||
* userland apps only expect 32 (like X itself since it thinks only
|
||||
* Sparc has 64 bits MMIO) but if we don't do that, we break it on
|
||||
* 32 bits CHRPs :-(
|
||||
*
|
||||
* Hopefully, the sysfs insterface is immune to that gunk. Once X
|
||||
* has been fixed (and the fix spread enough), we can re-enable the
|
||||
* 2 lines below and pass down a BAR value to userland. In that case
|
||||
* we'll also have to re-enable the matching code in
|
||||
* __pci_mmap_make_offset().
|
||||
*
|
||||
* BenH.
|
||||
* That means we may have 64-bit values where some apps only expect
|
||||
* 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
|
||||
*/
|
||||
#if 0
|
||||
else if (rsrc->flags & IORESOURCE_MEM)
|
||||
offset = hose->pci_mem_offset;
|
||||
#endif
|
||||
|
||||
*start = rsrc->start - offset;
|
||||
*end = rsrc->end - offset;
|
||||
*start = rsrc->start;
|
||||
*end = rsrc->end;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -55,9 +55,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
||||
}
|
||||
|
||||
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
|
||||
void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
||||
const struct resource *rsrc,
|
||||
resource_size_t *start, resource_size_t *end);
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __SPARC64_PCI_H */
|
||||
|
||||
+11
-9
@@ -986,16 +986,18 @@ void pci_resource_to_user(const struct pci_dev *pdev, int bar,
|
||||
const struct resource *rp, resource_size_t *start,
|
||||
resource_size_t *end)
|
||||
{
|
||||
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
|
||||
unsigned long offset;
|
||||
struct pci_bus_region region;
|
||||
|
||||
if (rp->flags & IORESOURCE_IO)
|
||||
offset = pbm->io_space.start;
|
||||
else
|
||||
offset = pbm->mem_space.start;
|
||||
|
||||
*start = rp->start - offset;
|
||||
*end = rp->end - offset;
|
||||
/*
|
||||
* "User" addresses are shown in /sys/devices/pci.../.../resource
|
||||
* and /proc/bus/pci/devices and used as mmap offsets for
|
||||
* /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
|
||||
*
|
||||
* On sparc, these are PCI bus addresses, i.e., raw BAR values.
|
||||
*/
|
||||
pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
|
||||
*start = region.start;
|
||||
*end = region.end;
|
||||
}
|
||||
|
||||
void pcibios_set_master(struct pci_dev *dev)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user