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Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits) MN10300: Save frame pointer in thread_info struct rather than global var MN10300: Change "Matsushita" to "Panasonic". MN10300: Create a defconfig for the ASB2364 board MN10300: Update the ASB2303 defconfig MN10300: ASB2364: Add support for SMSC911X and SMC911X MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA MN10300: Generic time support MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support MN10300: Map userspace atomic op regs as a vmalloc page MN10300: And Panasonic AM34 subarch and implement SMP MN10300: Delete idle_timestamp from irq_cpustat_t MN10300: Make various interrupt priority settings configurable MN10300: Optimise do_csum() MN10300: Implement atomic ops using atomic ops unit MN10300: Make the FPU operate in non-lazy mode under SMP MN10300: SMP TLB flushing MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control MN10300: Make the use of PIDR to mark TLB entries controllable MN10300: Rename __flush_tlb*() to local_flush_tlb*() MN10300: AM34 erratum requires MMUCTR read and write on exception entry ...
This commit is contained in:
Linus Torvalds
@@ -53,7 +53,7 @@ targets += arch/$(SRCARCH)/kernel/asm-offsets.s
|
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# Default sed regexp - multiline due to syntax constraints
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define sed-y
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"/^->/{s:->#\(.*\):/* \1 */:; \
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s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 (\2) /* \3 */:; \
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s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
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s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
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s:->::; p;}"
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endef
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+1
-1
@@ -4448,7 +4448,7 @@ L: platform-driver-x86@vger.kernel.org
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S: Maintained
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F: drivers/platform/x86/panasonic-laptop.c
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PANASONIC MN10300/AM33 PORT
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PANASONIC MN10300/AM33/AM34 PORT
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M: David Howells <dhowells@redhat.com>
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M: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
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L: linux-am33-list@redhat.com (moderated for non-subscribers)
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+219
-60
@@ -9,8 +9,19 @@ config MN10300
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def_bool y
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select HAVE_OPROFILE
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config AM33
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def_bool y
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config AM33_2
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def_bool n
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config AM33_3
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def_bool n
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config AM34_2
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def_bool n
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select MN10300_HAS_ATOMIC_OPS_UNIT
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select MN10300_HAS_CACHE_SNOOP
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config ERRATUM_NEED_TO_RELOAD_MMUCTR
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def_bool y if AM33_3 || AM34_2
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config MMU
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def_bool y
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@@ -37,7 +48,7 @@ config GENERIC_CALIBRATE_DELAY
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def_bool y
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config GENERIC_CMOS_UPDATE
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def_bool y
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def_bool n
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config GENERIC_FIND_NEXT_BIT
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def_bool y
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@@ -45,6 +56,27 @@ config GENERIC_FIND_NEXT_BIT
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config GENERIC_HWEIGHT
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def_bool y
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config GENERIC_TIME
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def_bool y
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config GENERIC_CLOCKEVENTS
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def_bool y
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config GENERIC_CLOCKEVENTS_BUILD
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def_bool y
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depends on GENERIC_CLOCKEVENTS
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config GENERIC_CLOCKEVENTS_BROADCAST
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bool
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config CEVT_MN10300
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def_bool y
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depends on GENERIC_CLOCKEVENTS
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config CSRC_MN10300
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def_bool y
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depends on GENERIC_TIME
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config GENERIC_BUG
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def_bool y
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@@ -61,18 +93,14 @@ config GENERIC_HARDIRQS
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config HOTPLUG_CPU
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def_bool n
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config HZ
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int
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default 1000
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mainmenu "Matsushita MN10300/AM33 Kernel Configuration"
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mainmenu "Panasonic MN10300/AM33 Kernel Configuration"
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source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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menu "Matsushita MN10300 system setup"
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menu "Panasonic MN10300 system setup"
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choice
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prompt "Unit type"
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@@ -87,6 +115,10 @@ config MN10300_UNIT_ASB2303
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config MN10300_UNIT_ASB2305
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bool "ASB2305"
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config MN10300_UNIT_ASB2364
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bool "ASB2364"
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select SMSC911X_ARCH_HOOKS if SMSC911X
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endchoice
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choice
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@@ -99,57 +131,51 @@ choice
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config MN10300_PROC_MN103E010
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bool "MN103E010"
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depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305
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select AM33_2
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select MN10300_PROC_HAS_TTYSM0
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select MN10300_PROC_HAS_TTYSM1
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select MN10300_PROC_HAS_TTYSM2
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config MN10300_PROC_MN2WS0050
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bool "MN2WS0050"
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depends on MN10300_UNIT_ASB2364
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select AM34_2
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select MN10300_PROC_HAS_TTYSM0
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select MN10300_PROC_HAS_TTYSM1
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select MN10300_PROC_HAS_TTYSM2
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endchoice
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choice
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prompt "Processor core support"
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default MN10300_CPU_AM33V2
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config MN10300_HAS_ATOMIC_OPS_UNIT
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def_bool n
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help
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This option specifies the processor core for which the kernel will be
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compiled. It affects the instruction set used.
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config MN10300_CPU_AM33V2
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bool "AM33v2"
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endchoice
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This should be enabled if the processor has an atomic ops unit
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capable of doing LL/SC equivalent operations.
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config FPU
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bool "FPU present"
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default y
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depends on MN10300_PROC_MN103E010
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depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
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choice
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prompt "CPU Caching mode"
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default MN10300_CACHE_WBACK
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config LAZY_SAVE_FPU
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bool "Save FPU state lazily"
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default y
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depends on FPU && !SMP
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help
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This option determines the caching mode for the kernel.
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Enable this to be lazy in the saving of the FPU state to the owning
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task's thread struct. This is useful if most tasks on the system
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don't use the FPU as only those tasks that use it will pass it
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between them, and the state needn't be saved for a task that isn't
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using it.
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Write-Back caching mode involves the all reads and writes causing
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the affected cacheline to be read into the cache first before being
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operated upon. Memory is not then updated by a write until the cache
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is filled and a cacheline needs to be displaced from the cache to
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make room. Only at that point is it written back.
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This can't be so easily used on SMP as the process that owns the FPU
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state on a CPU may be currently running on another CPU, so for the
|
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moment, it is disabled.
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Write-Through caching only fetches cachelines from memory on a
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read. Writes always get written directly to memory. If the affected
|
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cacheline is also in cache, it will be updated too.
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source "arch/mn10300/mm/Kconfig.cache"
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|
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The final option is to turn of caching entirely.
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config MN10300_CACHE_WBACK
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bool "Write-Back"
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config MN10300_CACHE_WTHRU
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bool "Write-Through"
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config MN10300_CACHE_DISABLED
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bool "Disabled"
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|
||||
endchoice
|
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config MN10300_TLB_USE_PIDR
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def_bool y
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menu "Memory layout options"
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@@ -170,24 +196,55 @@ config KERNEL_TEXT_ADDRESS
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config KERNEL_ZIMAGE_BASE_ADDRESS
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hex "Base address of compressed vmlinux image"
|
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default "0x90700000"
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default "0x50700000"
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config BOOT_STACK_OFFSET
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hex
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default "0xF00" if SMP
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default "0xFF0" if !SMP
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config BOOT_STACK_SIZE
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hex
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depends on SMP
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default "0x100"
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endmenu
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config PREEMPT
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bool "Preemptible Kernel"
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||||
help
|
||||
This option reduces the latency of the kernel when reacting to
|
||||
real-time or interactive events by allowing a low priority process to
|
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be preempted even if it is in kernel mode executing a system call.
|
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This allows applications to run more reliably even when the system is
|
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under load.
|
||||
config SMP
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bool "Symmetric multi-processing support"
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default y
|
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depends on MN10300_PROC_MN2WS0038 || MN10300_PROC_MN2WS0050
|
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---help---
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, like most personal computers, say N. If
|
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you have a system with more than one CPU, say Y.
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Say Y here if you are building a kernel for a desktop, embedded
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or real-time system. Say N if you are unsure.
|
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If you say N here, the kernel will run on single and multiprocessor
|
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machines, but will use only one CPU of a multiprocessor machine. If
|
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you say Y here, the kernel will run on many, but not all,
|
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singleprocessor machines. On a singleprocessor machine, the kernel
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will run faster if you say N here.
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See also <file:Documentation/i386/IO-APIC.txt>,
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<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
|
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<http://www.tldp.org/docs.html#howto>.
|
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|
||||
If you don't know what to do here, say N.
|
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config NR_CPUS
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int
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depends on SMP
|
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default "2"
|
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config USE_GENERIC_SMP_HELPERS
|
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bool
|
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depends on SMP
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default y
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source "kernel/Kconfig.preempt"
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config MN10300_CURRENT_IN_E2
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bool "Hold current task address in E2 register"
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depends on !SMP
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default y
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help
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This option removes the E2/R2 register from the set available to gcc
|
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@@ -209,12 +266,15 @@ config MN10300_USING_JTAG
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suppresses the use of certain hardware debugging features, such as
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single-stepping, which are taken over completely by the JTAG unit.
|
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source "kernel/Kconfig.hz"
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source "kernel/time/Kconfig"
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config MN10300_RTC
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bool "Using MN10300 RTC"
|
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depends on MN10300_PROC_MN103E010
|
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depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
|
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select GENERIC_CMOS_UPDATE
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default n
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help
|
||||
|
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This option enables support for the RTC, thus enabling time to be
|
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tracked, even when system is powered down. This is available on-chip
|
||||
on the MN103E010.
|
||||
@@ -306,14 +366,23 @@ config MN10300_TTYSM1
|
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|
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choice
|
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prompt "Select the timer to supply the clock for SIF1"
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default MN10300_TTYSM0_TIMER9
|
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default MN10300_TTYSM1_TIMER12 \
|
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if !(AM33_2 || AM33_3)
|
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default MN10300_TTYSM1_TIMER9 \
|
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if AM33_2 || AM33_3
|
||||
depends on MN10300_TTYSM1
|
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|
||||
config MN10300_TTYSM1_TIMER12
|
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bool "Use timer 12 (16-bit)"
|
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depends on !(AM33_2 || AM33_3)
|
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|
||||
config MN10300_TTYSM1_TIMER9
|
||||
bool "Use timer 9 (16-bit)"
|
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depends on AM33_2 || AM33_3
|
||||
|
||||
config MN10300_TTYSM1_TIMER3
|
||||
bool "Use timer 3 (8-bit)"
|
||||
depends on AM33_2 || AM33_3
|
||||
|
||||
endchoice
|
||||
|
||||
@@ -328,17 +397,107 @@ config MN10300_TTYSM2
|
||||
|
||||
choice
|
||||
prompt "Select the timer to supply the clock for SIF2"
|
||||
default MN10300_TTYSM0_TIMER10
|
||||
default MN10300_TTYSM2_TIMER3 \
|
||||
if !(AM33_2 || AM33_3)
|
||||
default MN10300_TTYSM2_TIMER10 \
|
||||
if AM33_2 || AM33_3
|
||||
depends on MN10300_TTYSM2
|
||||
|
||||
config MN10300_TTYSM2_TIMER9
|
||||
bool "Use timer 9 (16-bit)"
|
||||
depends on !(AM33_2 || AM33_3)
|
||||
|
||||
config MN10300_TTYSM2_TIMER1
|
||||
bool "Use timer 1 (8-bit)"
|
||||
depends on !(AM33_2 || AM33_3)
|
||||
|
||||
config MN10300_TTYSM2_TIMER3
|
||||
bool "Use timer 3 (8-bit)"
|
||||
depends on !(AM33_2 || AM33_3)
|
||||
|
||||
config MN10300_TTYSM2_TIMER10
|
||||
bool "Use timer 10 (16-bit)"
|
||||
depends on AM33_2 || AM33_3
|
||||
|
||||
endchoice
|
||||
|
||||
config MN10300_TTYSM2_CTS
|
||||
bool "Enable the use of the CTS line /dev/ttySM2"
|
||||
depends on MN10300_TTYSM2
|
||||
depends on MN10300_TTYSM2 && AM33_2
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Interrupt request priority options"
|
||||
|
||||
comment "[!] NOTE: A lower number/level indicates a higher priority (0 is highest, 6 is lowest)"
|
||||
|
||||
comment "____Non-maskable interrupt levels____"
|
||||
comment "The following must be set to a higher priority than local_irq_disable() and on-chip serial"
|
||||
|
||||
config GDBSTUB_IRQ_LEVEL
|
||||
int "GDBSTUB interrupt priority"
|
||||
depends on GDBSTUB
|
||||
range 0 1 if LINUX_CLI_LEVEL = 2
|
||||
range 0 2 if LINUX_CLI_LEVEL = 3
|
||||
range 0 3 if LINUX_CLI_LEVEL = 4
|
||||
range 0 4 if LINUX_CLI_LEVEL = 5
|
||||
range 0 5 if LINUX_CLI_LEVEL = 6
|
||||
default 0
|
||||
|
||||
comment "The following must be set to a higher priority than local_irq_disable()"
|
||||
|
||||
config MN10300_SERIAL_IRQ_LEVEL
|
||||
int "MN10300 on-chip serial interrupt priority"
|
||||
depends on MN10300_TTYSM
|
||||
range 1 1 if LINUX_CLI_LEVEL = 2
|
||||
range 1 2 if LINUX_CLI_LEVEL = 3
|
||||
range 1 3 if LINUX_CLI_LEVEL = 4
|
||||
range 1 4 if LINUX_CLI_LEVEL = 5
|
||||
range 1 5 if LINUX_CLI_LEVEL = 6
|
||||
default 1
|
||||
|
||||
comment "-"
|
||||
comment "____Maskable interrupt levels____"
|
||||
|
||||
config LINUX_CLI_LEVEL
|
||||
int "The highest interrupt priority excluded by local_irq_disable() (2-6)"
|
||||
range 2 6
|
||||
default 2
|
||||
help
|
||||
local_irq_disable() doesn't actually disable maskable interrupts -
|
||||
what it does is restrict the levels of interrupt which are permitted
|
||||
(a lower level indicates a higher priority) by lowering the value in
|
||||
EPSW.IM from 7. Any interrupt is permitted for which the level is
|
||||
lower than EPSW.IM.
|
||||
|
||||
Certain interrupts, such as GDBSTUB and virtual MN10300 on-chip
|
||||
serial DMA interrupts are allowed to interrupt normal disabled
|
||||
sections.
|
||||
|
||||
comment "The following must be set to a equal to or lower priority than LINUX_CLI_LEVEL"
|
||||
|
||||
config TIMER_IRQ_LEVEL
|
||||
int "Kernel timer interrupt priority"
|
||||
range LINUX_CLI_LEVEL 6
|
||||
default 4
|
||||
|
||||
config PCI_IRQ_LEVEL
|
||||
int "PCI interrupt priority"
|
||||
depends on PCI
|
||||
range LINUX_CLI_LEVEL 6
|
||||
default 5
|
||||
|
||||
config ETHERNET_IRQ_LEVEL
|
||||
int "Ethernet interrupt priority"
|
||||
depends on SMC91X || SMC911X || SMSC911X
|
||||
range LINUX_CLI_LEVEL 6
|
||||
default 6
|
||||
|
||||
config EXT_SERIAL_IRQ_LEVEL
|
||||
int "External serial port interrupt priority"
|
||||
depends on SERIAL_8250
|
||||
range LINUX_CLI_LEVEL 6
|
||||
default 6
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
@@ -36,6 +36,9 @@ endif
|
||||
ifeq ($(CONFIG_MN10300_PROC_MN103E010),y)
|
||||
PROCESSOR := mn103e010
|
||||
endif
|
||||
ifeq ($(CONFIG_MN10300_PROC_MN2WS0050),y)
|
||||
PROCESSOR := mn2ws0050
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MN10300_UNIT_ASB2303),y)
|
||||
UNIT := asb2303
|
||||
@@ -43,6 +46,9 @@ endif
|
||||
ifeq ($(CONFIG_MN10300_UNIT_ASB2305),y)
|
||||
UNIT := asb2305
|
||||
endif
|
||||
ifeq ($(CONFIG_MN10300_UNIT_ASB2364),y)
|
||||
UNIT := asb2364
|
||||
endif
|
||||
|
||||
|
||||
head-y := arch/mn10300/kernel/head.o arch/mn10300/kernel/init_task.o
|
||||
|
||||
@@ -14,10 +14,29 @@
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/cpu-regs.h>
|
||||
#include <asm/cache.h>
|
||||
#ifdef CONFIG_SMP
|
||||
#include <proc/smp-regs.h>
|
||||
#endif
|
||||
|
||||
.globl startup_32
|
||||
startup_32:
|
||||
# first save off parameters from bootloader
|
||||
#ifdef CONFIG_SMP
|
||||
#
|
||||
# Secondary CPUs jump directly to the kernel entry point
|
||||
#
|
||||
# Must save primary CPU's D0-D2 registers as they hold boot parameters
|
||||
#
|
||||
mov (CPUID), d3
|
||||
and CPUID_MASK,d3
|
||||
beq startup_primary
|
||||
mov CONFIG_KERNEL_TEXT_ADDRESS,a0
|
||||
jmp (a0)
|
||||
|
||||
startup_primary:
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
# first save parameters from bootloader
|
||||
mov param_save_area,a0
|
||||
mov d0,(a0)
|
||||
mov d1,(4,a0)
|
||||
@@ -37,8 +56,15 @@ startup_32:
|
||||
mov (a0),d0
|
||||
btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
|
||||
lne
|
||||
mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD,d0 # writethru dcache
|
||||
|
||||
#ifdef CONFIG_MN10300_CACHE_ENABLED
|
||||
#ifdef CONFIG_MN10300_CACHE_WBACK
|
||||
mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
|
||||
#else
|
||||
mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
|
||||
#endif /* WBACK */
|
||||
movhu d0,(a0) # enable
|
||||
#endif /* !ENABLED */
|
||||
|
||||
# clear the BSS area
|
||||
mov __bss_start,a0
|
||||
@@ -54,6 +80,9 @@ bssclear_end:
|
||||
|
||||
# decompress the kernel
|
||||
call decompress_kernel[],0
|
||||
#ifdef CONFIG_MN10300_CACHE_WBACK
|
||||
call mn10300_dcache_flush_inv[],0
|
||||
#endif
|
||||
|
||||
# disable caches again
|
||||
mov CHCTR,a0
|
||||
@@ -69,10 +98,46 @@ bssclear_end:
|
||||
mov (4,a0),d1
|
||||
mov (8,a0),d2
|
||||
|
||||
# jump to the kernel proper entry point
|
||||
mov a3,sp
|
||||
mov CONFIG_KERNEL_TEXT_ADDRESS,a0
|
||||
jmp (a0)
|
||||
|
||||
|
||||
###############################################################################
|
||||
#
|
||||
# Cache flush routines
|
||||
#
|
||||
###############################################################################
|
||||
#ifdef CONFIG_MN10300_CACHE_WBACK
|
||||
mn10300_dcache_flush_inv:
|
||||
movhu (CHCTR),d0
|
||||
btst CHCTR_DCEN,d0
|
||||
beq mn10300_dcache_flush_inv_end
|
||||
|
||||
mov L1_CACHE_NENTRIES,d1
|
||||
clr a1
|
||||
|
||||
mn10300_dcache_flush_inv_loop:
|
||||
mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
|
||||
mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
|
||||
mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
|
||||
mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
|
||||
|
||||
add L1_CACHE_BYTES,a1
|
||||
add -1,d1
|
||||
bne mn10300_dcache_flush_inv_loop
|
||||
|
||||
mn10300_dcache_flush_inv_end:
|
||||
ret [],0
|
||||
#endif /* CONFIG_MN10300_CACHE_WBACK */
|
||||
|
||||
|
||||
###############################################################################
|
||||
#
|
||||
# Data areas
|
||||
#
|
||||
###############################################################################
|
||||
.data
|
||||
.align 4
|
||||
param_save_area:
|
||||
|
||||
@@ -12,6 +12,8 @@ CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
# CONFIG_BLOCK is not set
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_MN10300_RTC=y
|
||||
CONFIG_MN10300_TTYSM_CONSOLE=y
|
||||
CONFIG_MN10300_TTYSM0=y
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_TASKSTATS=y
|
||||
CONFIG_TASK_DELAY_ACCT=y
|
||||
CONFIG_TASK_XACCT=y
|
||||
CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_NS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_RESOURCE_COUNTERS=y
|
||||
CONFIG_RELAY=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_KALLSYMS is not set
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLOCK is not set
|
||||
CONFIG_MN10300_UNIT_ASB2364=y
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_MN10300_USING_JTAG is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_MN10300_TTYSM_CONSOLE=y
|
||||
CONFIG_MN10300_TTYSM0=y
|
||||
CONFIG_MN10300_TTYSM0_TIMER2=y
|
||||
CONFIG_MN10300_TTYSM1=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_DEBUG=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
CONFIG_MTD_CFI_I4=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_PROC_KCORE=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
@@ -1 +1,351 @@
|
||||
/* MN10300 Atomic counter operations
|
||||
*
|
||||
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
|
||||
* Written by David Howells (dhowells@redhat.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public Licence
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the Licence, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef _ASM_ATOMIC_H
|
||||
#define _ASM_ATOMIC_H
|
||||
|
||||
#include <asm/irqflags.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
|
||||
static inline
|
||||
unsigned long __xchg(volatile unsigned long *m, unsigned long val)
|
||||
{
|
||||
unsigned long status;
|
||||
unsigned long oldval;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %4,(_AAR,%3) \n"
|
||||
" mov (_ADR,%3),%1 \n"
|
||||
" mov %5,(_ADR,%3) \n"
|
||||
" mov (_ADR,%3),%0 \n" /* flush */
|
||||
" mov (_ASR,%3),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=&r"(oldval), "=m"(*m)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), "r"(val)
|
||||
: "memory", "cc");
|
||||
|
||||
return oldval;
|
||||
}
|
||||
|
||||
static inline unsigned long __cmpxchg(volatile unsigned long *m,
|
||||
unsigned long old, unsigned long new)
|
||||
{
|
||||
unsigned long status;
|
||||
unsigned long oldval;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %4,(_AAR,%3) \n"
|
||||
" mov (_ADR,%3),%1 \n"
|
||||
" cmp %5,%1 \n"
|
||||
" bne 2f \n"
|
||||
" mov %6,(_ADR,%3) \n"
|
||||
"2: mov (_ADR,%3),%0 \n" /* flush */
|
||||
" mov (_ASR,%3),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=&r"(oldval), "=m"(*m)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m),
|
||||
"r"(old), "r"(new)
|
||||
: "memory", "cc");
|
||||
|
||||
return oldval;
|
||||
}
|
||||
#else /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
|
||||
#error "No SMP atomic operation support!"
|
||||
#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
|
||||
|
||||
#else /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* Emulate xchg for non-SMP MN10300
|
||||
*/
|
||||
struct __xchg_dummy { unsigned long a[100]; };
|
||||
#define __xg(x) ((struct __xchg_dummy *)(x))
|
||||
|
||||
static inline
|
||||
unsigned long __xchg(volatile unsigned long *m, unsigned long val)
|
||||
{
|
||||
unsigned long oldval;
|
||||
unsigned long flags;
|
||||
|
||||
flags = arch_local_cli_save();
|
||||
oldval = *m;
|
||||
*m = val;
|
||||
arch_local_irq_restore(flags);
|
||||
return oldval;
|
||||
}
|
||||
|
||||
/*
|
||||
* Emulate cmpxchg for non-SMP MN10300
|
||||
*/
|
||||
static inline unsigned long __cmpxchg(volatile unsigned long *m,
|
||||
unsigned long old, unsigned long new)
|
||||
{
|
||||
unsigned long oldval;
|
||||
unsigned long flags;
|
||||
|
||||
flags = arch_local_cli_save();
|
||||
oldval = *m;
|
||||
if (oldval == old)
|
||||
*m = new;
|
||||
arch_local_irq_restore(flags);
|
||||
return oldval;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#define xchg(ptr, v) \
|
||||
((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
|
||||
(unsigned long)(v)))
|
||||
|
||||
#define cmpxchg(ptr, o, n) \
|
||||
((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
|
||||
(unsigned long)(o), \
|
||||
(unsigned long)(n)))
|
||||
|
||||
#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
|
||||
#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#include <asm-generic/atomic.h>
|
||||
#else
|
||||
|
||||
/*
|
||||
* Atomic operations that C can't guarantee us. Useful for
|
||||
* resource counting etc..
|
||||
*/
|
||||
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/**
|
||||
* atomic_read - read atomic variable
|
||||
* @v: pointer of type atomic_t
|
||||
*
|
||||
* Atomically reads the value of @v. Note that the guaranteed
|
||||
* useful range of an atomic_t is only 24 bits.
|
||||
*/
|
||||
#define atomic_read(v) ((v)->counter)
|
||||
|
||||
/**
|
||||
* atomic_set - set atomic variable
|
||||
* @v: pointer of type atomic_t
|
||||
* @i: required value
|
||||
*
|
||||
* Atomically sets the value of @v to @i. Note that the guaranteed
|
||||
* useful range of an atomic_t is only 24 bits.
|
||||
*/
|
||||
#define atomic_set(v, i) (((v)->counter) = (i))
|
||||
|
||||
/**
|
||||
* atomic_add_return - add integer to atomic variable
|
||||
* @i: integer value to add
|
||||
* @v: pointer of type atomic_t
|
||||
*
|
||||
* Atomically adds @i to @v and returns the result
|
||||
* Note that the guaranteed useful range of an atomic_t is only 24 bits.
|
||||
*/
|
||||
static inline int atomic_add_return(int i, atomic_t *v)
|
||||
{
|
||||
int retval;
|
||||
#ifdef CONFIG_SMP
|
||||
int status;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %4,(_AAR,%3) \n"
|
||||
" mov (_ADR,%3),%1 \n"
|
||||
" add %5,%1 \n"
|
||||
" mov %1,(_ADR,%3) \n"
|
||||
" mov (_ADR,%3),%0 \n" /* flush */
|
||||
" mov (_ASR,%3),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=&r"(retval), "=m"(v->counter)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i)
|
||||
: "memory", "cc");
|
||||
|
||||
#else
|
||||
unsigned long flags;
|
||||
|
||||
flags = arch_local_cli_save();
|
||||
retval = v->counter;
|
||||
retval += i;
|
||||
v->counter = retval;
|
||||
arch_local_irq_restore(flags);
|
||||
#endif
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* atomic_sub_return - subtract integer from atomic variable
|
||||
* @i: integer value to subtract
|
||||
* @v: pointer of type atomic_t
|
||||
*
|
||||
* Atomically subtracts @i from @v and returns the result
|
||||
* Note that the guaranteed useful range of an atomic_t is only 24 bits.
|
||||
*/
|
||||
static inline int atomic_sub_return(int i, atomic_t *v)
|
||||
{
|
||||
int retval;
|
||||
#ifdef CONFIG_SMP
|
||||
int status;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %4,(_AAR,%3) \n"
|
||||
" mov (_ADR,%3),%1 \n"
|
||||
" sub %5,%1 \n"
|
||||
" mov %1,(_ADR,%3) \n"
|
||||
" mov (_ADR,%3),%0 \n" /* flush */
|
||||
" mov (_ASR,%3),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=&r"(retval), "=m"(v->counter)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i)
|
||||
: "memory", "cc");
|
||||
|
||||
#else
|
||||
unsigned long flags;
|
||||
flags = arch_local_cli_save();
|
||||
retval = v->counter;
|
||||
retval -= i;
|
||||
v->counter = retval;
|
||||
arch_local_irq_restore(flags);
|
||||
#endif
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline int atomic_add_negative(int i, atomic_t *v)
|
||||
{
|
||||
return atomic_add_return(i, v) < 0;
|
||||
}
|
||||
|
||||
static inline void atomic_add(int i, atomic_t *v)
|
||||
{
|
||||
atomic_add_return(i, v);
|
||||
}
|
||||
|
||||
static inline void atomic_sub(int i, atomic_t *v)
|
||||
{
|
||||
atomic_sub_return(i, v);
|
||||
}
|
||||
|
||||
static inline void atomic_inc(atomic_t *v)
|
||||
{
|
||||
atomic_add_return(1, v);
|
||||
}
|
||||
|
||||
static inline void atomic_dec(atomic_t *v)
|
||||
{
|
||||
atomic_sub_return(1, v);
|
||||
}
|
||||
|
||||
#define atomic_dec_return(v) atomic_sub_return(1, (v))
|
||||
#define atomic_inc_return(v) atomic_add_return(1, (v))
|
||||
|
||||
#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
|
||||
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
|
||||
#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
|
||||
|
||||
#define atomic_add_unless(v, a, u) \
|
||||
({ \
|
||||
int c, old; \
|
||||
c = atomic_read(v); \
|
||||
while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
|
||||
c = old; \
|
||||
c != (u); \
|
||||
})
|
||||
|
||||
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
|
||||
|
||||
/**
|
||||
* atomic_clear_mask - Atomically clear bits in memory
|
||||
* @mask: Mask of the bits to be cleared
|
||||
* @v: pointer to word in memory
|
||||
*
|
||||
* Atomically clears the bits set in mask from the memory word specified.
|
||||
*/
|
||||
static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int status;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %3,(_AAR,%2) \n"
|
||||
" mov (_ADR,%2),%0 \n"
|
||||
" and %4,%0 \n"
|
||||
" mov %0,(_ADR,%2) \n"
|
||||
" mov (_ADR,%2),%0 \n" /* flush */
|
||||
" mov (_ASR,%2),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=m"(*addr)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(~mask)
|
||||
: "memory", "cc");
|
||||
#else
|
||||
unsigned long flags;
|
||||
|
||||
mask = ~mask;
|
||||
flags = arch_local_cli_save();
|
||||
*addr &= mask;
|
||||
arch_local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* atomic_set_mask - Atomically set bits in memory
|
||||
* @mask: Mask of the bits to be set
|
||||
* @v: pointer to word in memory
|
||||
*
|
||||
* Atomically sets the bits set in mask from the memory word specified.
|
||||
*/
|
||||
static inline void atomic_set_mask(unsigned long mask, unsigned long *addr)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int status;
|
||||
|
||||
asm volatile(
|
||||
"1: mov %3,(_AAR,%2) \n"
|
||||
" mov (_ADR,%2),%0 \n"
|
||||
" or %4,%0 \n"
|
||||
" mov %0,(_ADR,%2) \n"
|
||||
" mov (_ADR,%2),%0 \n" /* flush */
|
||||
" mov (_ASR,%2),%0 \n"
|
||||
" or %0,%0 \n"
|
||||
" bne 1b \n"
|
||||
: "=&r"(status), "=m"(*addr)
|
||||
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(mask)
|
||||
: "memory", "cc");
|
||||
#else
|
||||
unsigned long flags;
|
||||
|
||||
flags = arch_local_cli_save();
|
||||
*addr |= mask;
|
||||
arch_local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Atomic operations are already serializing on MN10300??? */
|
||||
#define smp_mb__before_atomic_dec() barrier()
|
||||
#define smp_mb__after_atomic_dec() barrier()
|
||||
#define smp_mb__before_atomic_inc() barrier()
|
||||
#define smp_mb__after_atomic_inc() barrier()
|
||||
|
||||
#include <asm-generic/atomic-long.h>
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* CONFIG_SMP */
|
||||
#endif /* _ASM_ATOMIC_H */
|
||||
|
||||
@@ -57,7 +57,7 @@
|
||||
#define clear_bit(nr, addr) ___clear_bit((nr), (addr))
|
||||
|
||||
|
||||
static inline void __clear_bit(int nr, volatile void *addr)
|
||||
static inline void __clear_bit(unsigned long nr, volatile void *addr)
|
||||
{
|
||||
unsigned int *a = (unsigned int *) addr;
|
||||
int mask;
|
||||
@@ -70,15 +70,15 @@ static inline void __clear_bit(int nr, volatile void *addr)
|
||||
/*
|
||||
* test bit
|
||||
*/
|
||||
static inline int test_bit(int nr, const volatile void *addr)
|
||||
static inline int test_bit(unsigned long nr, const volatile void *addr)
|
||||
{
|
||||
return 1UL & (((const unsigned int *) addr)[nr >> 5] >> (nr & 31));
|
||||
return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
|
||||
}
|
||||
|
||||
/*
|
||||
* change bit
|
||||
*/
|
||||
static inline void __change_bit(int nr, volatile void *addr)
|
||||
static inline void __change_bit(unsigned long nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
unsigned int *a = (unsigned int *) addr;
|
||||
@@ -88,7 +88,7 @@ static inline void __change_bit(int nr, volatile void *addr)
|
||||
*a ^= mask;
|
||||
}
|
||||
|
||||
extern void change_bit(int nr, volatile void *addr);
|
||||
extern void change_bit(unsigned long nr, volatile void *addr);
|
||||
|
||||
/*
|
||||
* test and set bit
|
||||
@@ -135,7 +135,7 @@ extern void change_bit(int nr, volatile void *addr);
|
||||
/*
|
||||
* test and change bit
|
||||
*/
|
||||
static inline int __test_and_change_bit(int nr, volatile void *addr)
|
||||
static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
unsigned int *a = (unsigned int *)addr;
|
||||
@@ -148,7 +148,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
|
||||
return retval;
|
||||
}
|
||||
|
||||
extern int test_and_change_bit(int nr, volatile void *addr);
|
||||
extern int test_and_change_bit(unsigned long nr, volatile void *addr);
|
||||
|
||||
#include <asm-generic/bitops/lock.h>
|
||||
|
||||
|
||||
@@ -43,14 +43,18 @@
|
||||
|
||||
/* instruction cache access registers */
|
||||
#define ICACHE_DATA(WAY, ENTRY, OFF) \
|
||||
__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
|
||||
__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \
|
||||
(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
|
||||
#define ICACHE_TAG(WAY, ENTRY) \
|
||||
__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
|
||||
__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \
|
||||
(ENTRY) * L1_CACHE_BYTES, u32)
|
||||
|
||||
/* instruction cache access registers */
|
||||
/* data cache access registers */
|
||||
#define DCACHE_DATA(WAY, ENTRY, OFF) \
|
||||
__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
|
||||
__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \
|
||||
(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
|
||||
#define DCACHE_TAG(WAY, ENTRY) \
|
||||
__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
|
||||
__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \
|
||||
(ENTRY) * L1_CACHE_BYTES, u32)
|
||||
|
||||
#endif /* _ASM_CACHE_H */
|
||||
|
||||
@@ -17,7 +17,104 @@
|
||||
#include <linux/mm.h>
|
||||
|
||||
/*
|
||||
* virtually-indexed cache management (our cache is physically indexed)
|
||||
* Primitive routines
|
||||
*/
|
||||
#ifdef CONFIG_MN10300_CACHE_ENABLED
|
||||
extern void mn10300_local_icache_inv(void);
|
||||
extern void mn10300_local_icache_inv_page(unsigned long start);
|
||||
extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_local_dcache_inv(void);
|
||||
extern void mn10300_local_dcache_inv_page(unsigned long start);
|
||||
extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_icache_inv(void);
|
||||
extern void mn10300_icache_inv_page(unsigned long start);
|
||||
extern void mn10300_icache_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_icache_inv_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_dcache_inv(void);
|
||||
extern void mn10300_dcache_inv_page(unsigned long start);
|
||||
extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_dcache_inv_range2(unsigned long start, unsigned long size);
|
||||
#ifdef CONFIG_MN10300_CACHE_WBACK
|
||||
extern void mn10300_local_dcache_flush(void);
|
||||
extern void mn10300_local_dcache_flush_page(unsigned long start);
|
||||
extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_local_dcache_flush_inv(void);
|
||||
extern void mn10300_local_dcache_flush_inv_page(unsigned long start);
|
||||
extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_dcache_flush(void);
|
||||
extern void mn10300_dcache_flush_page(unsigned long start);
|
||||
extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_dcache_flush_range2(unsigned long start, unsigned long size);
|
||||
extern void mn10300_dcache_flush_inv(void);
|
||||
extern void mn10300_dcache_flush_inv_page(unsigned long start);
|
||||
extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end);
|
||||
extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size);
|
||||
#else
|
||||
#define mn10300_local_dcache_flush() do {} while (0)
|
||||
#define mn10300_local_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_inv() \
|
||||
mn10300_local_dcache_inv()
|
||||
#define mn10300_local_dcache_flush_inv_page(start) \
|
||||
mn10300_local_dcache_inv_page(start)
|
||||
#define mn10300_local_dcache_flush_inv_range(start, end) \
|
||||
mn10300_local_dcache_inv_range(start, end)
|
||||
#define mn10300_local_dcache_flush_inv_range2(start, size) \
|
||||
mn10300_local_dcache_inv_range2(start, size)
|
||||
#define mn10300_dcache_flush() do {} while (0)
|
||||
#define mn10300_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
|
||||
#define mn10300_dcache_flush_inv_page(start) \
|
||||
mn10300_dcache_inv_page((start))
|
||||
#define mn10300_dcache_flush_inv_range(start, end) \
|
||||
mn10300_dcache_inv_range((start), (end))
|
||||
#define mn10300_dcache_flush_inv_range2(start, size) \
|
||||
mn10300_dcache_inv_range2((start), (size))
|
||||
#endif /* CONFIG_MN10300_CACHE_WBACK */
|
||||
#else
|
||||
#define mn10300_local_icache_inv() do {} while (0)
|
||||
#define mn10300_local_icache_inv_page(start) do {} while (0)
|
||||
#define mn10300_local_icache_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_local_icache_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_local_dcache_inv() do {} while (0)
|
||||
#define mn10300_local_dcache_inv_page(start) do {} while (0)
|
||||
#define mn10300_local_dcache_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_local_dcache_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_local_dcache_flush() do {} while (0)
|
||||
#define mn10300_local_dcache_flush_inv_page(start) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_inv() do {} while (0)
|
||||
#define mn10300_local_dcache_flush_inv_range(start, end)do {} while (0)
|
||||
#define mn10300_local_dcache_flush_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
|
||||
#define mn10300_icache_inv() do {} while (0)
|
||||
#define mn10300_icache_inv_page(start) do {} while (0)
|
||||
#define mn10300_icache_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_icache_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_inv() do {} while (0)
|
||||
#define mn10300_dcache_inv_page(start) do {} while (0)
|
||||
#define mn10300_dcache_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush() do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv() do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
|
||||
#endif /* CONFIG_MN10300_CACHE_ENABLED */
|
||||
|
||||
/*
|
||||
* Virtually-indexed cache management (our cache is physically indexed)
|
||||
*/
|
||||
#define flush_cache_all() do {} while (0)
|
||||
#define flush_cache_mm(mm) do {} while (0)
|
||||
@@ -32,20 +129,24 @@
|
||||
#define flush_dcache_mmap_unlock(mapping) do {} while (0)
|
||||
|
||||
/*
|
||||
* physically-indexed cache management
|
||||
* Physically-indexed cache management
|
||||
*/
|
||||
#ifndef CONFIG_MN10300_CACHE_DISABLED
|
||||
|
||||
#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)
|
||||
extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
|
||||
extern void flush_icache_range(unsigned long start, unsigned long end);
|
||||
#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)
|
||||
static inline void flush_icache_page(struct vm_area_struct *vma,
|
||||
struct page *page)
|
||||
{
|
||||
mn10300_icache_inv_page(page_to_phys(page));
|
||||
}
|
||||
extern void flush_icache_range(unsigned long start, unsigned long end);
|
||||
extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
|
||||
|
||||
#else
|
||||
|
||||
#define flush_icache_range(start, end) do {} while (0)
|
||||
#define flush_icache_page(vma, pg) do {} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define flush_icache_user_range(vma, pg, adr, len) \
|
||||
flush_icache_range(adr, adr + len)
|
||||
|
||||
@@ -59,54 +160,7 @@ extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
|
||||
memcpy(dst, src, len)
|
||||
|
||||
/*
|
||||
* primitive routines
|
||||
*/
|
||||
#ifndef CONFIG_MN10300_CACHE_DISABLED
|
||||
extern void mn10300_icache_inv(void);
|
||||
extern void mn10300_dcache_inv(void);
|
||||
extern void mn10300_dcache_inv_page(unsigned start);
|
||||
extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
|
||||
extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
|
||||
#ifdef CONFIG_MN10300_CACHE_WBACK
|
||||
extern void mn10300_dcache_flush(void);
|
||||
extern void mn10300_dcache_flush_page(unsigned start);
|
||||
extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
|
||||
extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
|
||||
extern void mn10300_dcache_flush_inv(void);
|
||||
extern void mn10300_dcache_flush_inv_page(unsigned start);
|
||||
extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
|
||||
extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
|
||||
#else
|
||||
#define mn10300_dcache_flush() do {} while (0)
|
||||
#define mn10300_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
|
||||
#define mn10300_dcache_flush_inv_page(start) \
|
||||
mn10300_dcache_inv_page((start))
|
||||
#define mn10300_dcache_flush_inv_range(start, end) \
|
||||
mn10300_dcache_inv_range((start), (end))
|
||||
#define mn10300_dcache_flush_inv_range2(start, size) \
|
||||
mn10300_dcache_inv_range2((start), (size))
|
||||
#endif /* CONFIG_MN10300_CACHE_WBACK */
|
||||
#else
|
||||
#define mn10300_icache_inv() do {} while (0)
|
||||
#define mn10300_dcache_inv() do {} while (0)
|
||||
#define mn10300_dcache_inv_page(start) do {} while (0)
|
||||
#define mn10300_dcache_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush() do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv() do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
|
||||
#define mn10300_dcache_flush_page(start) do {} while (0)
|
||||
#define mn10300_dcache_flush_range(start, end) do {} while (0)
|
||||
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
|
||||
#endif /* CONFIG_MN10300_CACHE_DISABLED */
|
||||
|
||||
/*
|
||||
* internal debugging function
|
||||
* Internal debugging function
|
||||
*/
|
||||
#ifdef CONFIG_DEBUG_PAGEALLOC
|
||||
extern void kernel_map_pages(struct page *page, int numpages, int enable);
|
||||
|
||||
@@ -15,7 +15,6 @@
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MN10300_CPU_AM33V2
|
||||
/* we tell the compiler to pretend to be AM33 so that it doesn't try and use
|
||||
* the FP regs, but tell the assembler that we're actually allowed AM33v2
|
||||
* instructions */
|
||||
@@ -24,7 +23,6 @@ asm(" .am33_2\n");
|
||||
#else
|
||||
.am33_2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
@@ -58,6 +56,9 @@ asm(" .am33_2\n");
|
||||
#define EPSW_nAR 0x00040000 /* register bank control */
|
||||
#define EPSW_ML 0x00080000 /* monitor level */
|
||||
#define EPSW_FE 0x00100000 /* FPU enable */
|
||||
#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */
|
||||
|
||||
#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT)
|
||||
|
||||
/* FPU registers */
|
||||
#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
|
||||
@@ -99,9 +100,11 @@ asm(" .am33_2\n");
|
||||
#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
|
||||
#define CPUREV_TYPE 0x0000000f /* CPU type */
|
||||
#define CPUREV_TYPE_S 0
|
||||
#define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */
|
||||
#define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */
|
||||
#define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */
|
||||
#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */
|
||||
#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */
|
||||
#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */
|
||||
#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */
|
||||
#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */
|
||||
#define CPUREV_REVISION 0x000000f0 /* CPU revision */
|
||||
#define CPUREV_REVISION_S 4
|
||||
#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
|
||||
@@ -180,6 +183,21 @@ asm(" .am33_2\n");
|
||||
#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
|
||||
#define CHCTR_DCWMD 0xf000 /* data cache way mode */
|
||||
|
||||
#ifdef CONFIG_AM34_2
|
||||
#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */
|
||||
#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */
|
||||
#define ICIVCR_ICI 0x00000001 /* icache area invalidate */
|
||||
|
||||
#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */
|
||||
|
||||
#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */
|
||||
#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */
|
||||
#define DCPGCR_DCP 0x00000002 /* data cache area purge */
|
||||
#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */
|
||||
|
||||
#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */
|
||||
#endif /* CONFIG_AM34_2 */
|
||||
|
||||
/* MMU control registers */
|
||||
#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
|
||||
#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
|
||||
@@ -203,6 +221,9 @@ asm(" .am33_2\n");
|
||||
#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
|
||||
#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
|
||||
#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
|
||||
#ifdef CONFIG_AM34_2
|
||||
#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */
|
||||
#endif
|
||||
|
||||
#define PIDR __SYSREG(0xc0000094, u16) /* PID register */
|
||||
#define PIDR_PID 0x00ff /* process identifier */
|
||||
@@ -231,14 +252,6 @@ asm(" .am33_2\n");
|
||||
#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
|
||||
#define xPTEL_PPN 0xfffff006 /* physical page number */
|
||||
|
||||
#define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */
|
||||
#define xPTEL_UNUSED1_BIT 1
|
||||
#define xPTEL_UNUSED2_BIT 2
|
||||
#define xPTEL_C_BIT 3
|
||||
#define xPTEL_PV_BIT 4
|
||||
#define xPTEL_D_BIT 5
|
||||
#define xPTEL_G_BIT 9
|
||||
|
||||
#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
|
||||
#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
|
||||
#define xPTEU_VPN 0xfffffc00 /* virtual page number */
|
||||
@@ -262,7 +275,16 @@ asm(" .am33_2\n");
|
||||
#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
|
||||
#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
|
||||
#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
|
||||
#define xPTEL2_PPN 0xfffffc00 /* physical page number */
|
||||
#define xPTEL2_CWT 0x00000400 /* cacheable write-through */
|
||||
#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */
|
||||
#define xPTEL2_PPN 0xfffff000 /* physical page number */
|
||||
|
||||
#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */
|
||||
#define xPTEL2_C_BIT 1
|
||||
#define xPTEL2_PV_BIT 2
|
||||
#define xPTEL2_D_BIT 3
|
||||
#define xPTEL2_G_BIT 7
|
||||
#define xPTEL2_UNUSED1_BIT 11
|
||||
|
||||
#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
|
||||
#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
|
||||
@@ -285,6 +307,47 @@ asm(" .am33_2\n");
|
||||
#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
|
||||
#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
|
||||
|
||||
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
|
||||
/* atomic operation registers */
|
||||
#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */
|
||||
#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */
|
||||
#define ADR __SYSREG(0xc0000a08, u32) /* data */
|
||||
#define ASR __SYSREG(0xc0000a0c, u32) /* status */
|
||||
#define AARU __SYSREG(0xd400aa00, u32) /* user address */
|
||||
#define ADRU __SYSREG(0xd400aa08, u32) /* user data */
|
||||
#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */
|
||||
|
||||
#define ASR_RW 0x00000008 /* read */
|
||||
#define ASR_BW 0x00000004 /* bus error */
|
||||
#define ASR_IW 0x00000002 /* interrupt */
|
||||
#define ASR_LW 0x00000001 /* bus lock */
|
||||
|
||||
#define ASRU_RW ASR_RW /* read */
|
||||
#define ASRU_BW ASR_BW /* bus error */
|
||||
#define ASRU_IW ASR_IW /* interrupt */
|
||||
#define ASRU_LW ASR_LW /* bus lock */
|
||||
|
||||
/* in inline ASM, we stick the base pointer in to a reg and use offsets from
|
||||
* it */
|
||||
#define ATOMIC_OPS_BASE_ADDR 0xc0000a00
|
||||
#ifndef __ASSEMBLY__
|
||||
asm(
|
||||
"_AAR = 0\n"
|
||||
"_AAR2 = 4\n"
|
||||
"_ADR = 8\n"
|
||||
"_ASR = 12\n");
|
||||
#else
|
||||
#define _AAR 0
|
||||
#define _AAR2 4
|
||||
#define _ADR 8
|
||||
#define _ASR 12
|
||||
#endif
|
||||
|
||||
/* physical page address for userspace atomic operations registers */
|
||||
#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000
|
||||
|
||||
#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ASM_CPU_REGS_H */
|
||||
|
||||
@@ -11,91 +11,6 @@
|
||||
#ifndef _ASM_DMACTL_REGS_H
|
||||
#define _ASM_DMACTL_REGS_H
|
||||
|
||||
#include <asm/cpu-regs.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/* DMA registers */
|
||||
#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
|
||||
#define DMxCTR_BG 0x0000001f /* transfer request source */
|
||||
#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
|
||||
#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
|
||||
#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
|
||||
#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
|
||||
#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
|
||||
#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
|
||||
#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
|
||||
#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
|
||||
#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
|
||||
#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
|
||||
#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
|
||||
#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
|
||||
#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */
|
||||
#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */
|
||||
#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */
|
||||
#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */
|
||||
#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */
|
||||
#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */
|
||||
#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */
|
||||
#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */
|
||||
#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
|
||||
#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
|
||||
#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
|
||||
#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
|
||||
#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
|
||||
#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
|
||||
#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
|
||||
#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
|
||||
#define DMxCTR_TM 0x00001800 /* DMA transfer mode */
|
||||
#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
|
||||
#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
|
||||
#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
|
||||
#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
|
||||
#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
|
||||
#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
|
||||
#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
|
||||
#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
|
||||
#define DMxCTR_RQM 0x00060000 /* external request input source mode */
|
||||
#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
|
||||
#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
|
||||
#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
|
||||
#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
|
||||
#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
|
||||
#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
|
||||
|
||||
#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
|
||||
|
||||
#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
|
||||
|
||||
#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
|
||||
#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
|
||||
|
||||
#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
|
||||
* size reg */
|
||||
#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
|
||||
|
||||
#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
|
||||
#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
|
||||
#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
|
||||
#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
|
||||
|
||||
#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
|
||||
#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
|
||||
#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
|
||||
#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct mn10300_dmactl_regs {
|
||||
u32 ctr;
|
||||
const void *src;
|
||||
void *dst;
|
||||
u32 siz;
|
||||
u32 cyc;
|
||||
} __attribute__((aligned(0x100)));
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#include <proc/dmactl-regs.h>
|
||||
|
||||
#endif /* _ASM_DMACTL_REGS_H */
|
||||
|
||||
@@ -31,6 +31,12 @@
|
||||
#define R_MN10300_SYM_DIFF 33 /* Adjustment when relaxing. */
|
||||
#define R_MN10300_ALIGN 34 /* Alignment requirement. */
|
||||
|
||||
/*
|
||||
* AM33/AM34 HW Capabilities
|
||||
*/
|
||||
#define HWCAP_MN10300_ATOMIC_OP_UNIT 1 /* Has AM34 Atomic Operations */
|
||||
|
||||
|
||||
/*
|
||||
* ELF register definitions..
|
||||
*/
|
||||
@@ -47,8 +53,6 @@ typedef struct {
|
||||
u_int32_t fpcr;
|
||||
} elf_fpregset_t;
|
||||
|
||||
extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
|
||||
|
||||
/*
|
||||
* This is used to ensure we don't load something for the wrong architecture
|
||||
*/
|
||||
@@ -130,7 +134,11 @@ do { \
|
||||
* instruction set this CPU supports. This could be done in user space,
|
||||
* but it's not easy, and we've already done it here.
|
||||
*/
|
||||
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
|
||||
#define ELF_HWCAP (HWCAP_MN10300_ATOMIC_OP_UNIT)
|
||||
#else
|
||||
#define ELF_HWCAP (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This yields a string that ld.so will use to load implementation
|
||||
|
||||
@@ -15,8 +15,8 @@
|
||||
|
||||
/*
|
||||
* define the breakpoint instruction opcode to use
|
||||
* - note that the JTAG unit steals 0xFF, so we want to avoid that if we can
|
||||
* (can use 0xF7)
|
||||
* - note that the JTAG unit steals 0xFF, so you can't use JTAG and GDBSTUB at
|
||||
* the same time.
|
||||
*/
|
||||
#define GDBSTUB_BKPT 0xFF
|
||||
|
||||
@@ -90,7 +90,6 @@ enum exception_code {
|
||||
|
||||
extern void __set_intr_stub(enum exception_code code, void *handler);
|
||||
extern void set_intr_stub(enum exception_code code, void *handler);
|
||||
extern void set_jtag_stub(enum exception_code code, void *handler);
|
||||
|
||||
struct pt_regs;
|
||||
|
||||
@@ -102,7 +101,6 @@ extern asmlinkage void dtlb_aerror(void);
|
||||
extern asmlinkage void raw_bus_error(void);
|
||||
extern asmlinkage void double_fault(void);
|
||||
extern asmlinkage int system_call(struct pt_regs *);
|
||||
extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
|
||||
extern asmlinkage void nmi(struct pt_regs *, enum exception_code);
|
||||
extern asmlinkage void uninitialised_exception(struct pt_regs *,
|
||||
enum exception_code);
|
||||
@@ -116,6 +114,8 @@ extern void die(const char *, struct pt_regs *, enum exception_code)
|
||||
|
||||
extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code);
|
||||
|
||||
#define NUM2EXCEP_IRQ_LEVEL(num) (EXCEP_IRQ_LEVEL0 + (num) * 8)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_EXCEPTIONS_H */
|
||||
|
||||
+104
-53
@@ -12,74 +12,125 @@
|
||||
#ifndef _ASM_FPU_H
|
||||
#define _ASM_FPU_H
|
||||
|
||||
#include <asm/processor.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <asm/exceptions.h>
|
||||
#include <asm/sigcontext.h>
|
||||
#include <asm/user.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/* the task that owns the FPU state */
|
||||
extern asmlinkage void fpu_disabled(void);
|
||||
|
||||
#ifdef CONFIG_FPU
|
||||
|
||||
#ifdef CONFIG_LAZY_SAVE_FPU
|
||||
/* the task that currently owns the FPU state */
|
||||
extern struct task_struct *fpu_state_owner;
|
||||
#endif
|
||||
|
||||
#define set_using_fpu(tsk) \
|
||||
do { \
|
||||
(tsk)->thread.fpu_flags |= THREAD_USING_FPU; \
|
||||
} while (0)
|
||||
#if (THREAD_USING_FPU & ~0xff)
|
||||
#error THREAD_USING_FPU must be smaller than 0x100.
|
||||
#endif
|
||||
|
||||
#define clear_using_fpu(tsk) \
|
||||
do { \
|
||||
(tsk)->thread.fpu_flags &= ~THREAD_USING_FPU; \
|
||||
} while (0)
|
||||
static inline void set_using_fpu(struct task_struct *tsk)
|
||||
{
|
||||
asm volatile(
|
||||
"bset %0,(0,%1)"
|
||||
:
|
||||
: "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
|
||||
: "memory", "cc");
|
||||
}
|
||||
|
||||
static inline void clear_using_fpu(struct task_struct *tsk)
|
||||
{
|
||||
asm volatile(
|
||||
"bclr %0,(0,%1)"
|
||||
:
|
||||
: "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
|
||||
: "memory", "cc");
|
||||
}
|
||||
|
||||
#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU)
|
||||
|
||||
#define unlazy_fpu(tsk) \
|
||||
do { \
|
||||
preempt_disable(); \
|
||||
if (fpu_state_owner == (tsk)) \
|
||||
fpu_save(&tsk->thread.fpu_state); \
|
||||
preempt_enable(); \
|
||||
} while (0)
|
||||
|
||||
#define exit_fpu() \
|
||||
do { \
|
||||
struct task_struct *__tsk = current; \
|
||||
preempt_disable(); \
|
||||
if (fpu_state_owner == __tsk) \
|
||||
fpu_state_owner = NULL; \
|
||||
preempt_enable(); \
|
||||
} while (0)
|
||||
|
||||
#define flush_fpu() \
|
||||
do { \
|
||||
struct task_struct *__tsk = current; \
|
||||
preempt_disable(); \
|
||||
if (fpu_state_owner == __tsk) { \
|
||||
fpu_state_owner = NULL; \
|
||||
__tsk->thread.uregs->epsw &= ~EPSW_FE; \
|
||||
} \
|
||||
preempt_enable(); \
|
||||
clear_using_fpu(__tsk); \
|
||||
} while (0)
|
||||
|
||||
extern asmlinkage void fpu_init_state(void);
|
||||
extern asmlinkage void fpu_kill_state(struct task_struct *);
|
||||
extern asmlinkage void fpu_disabled(struct pt_regs *, enum exception_code);
|
||||
extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
|
||||
|
||||
#ifdef CONFIG_FPU
|
||||
extern asmlinkage void fpu_invalid_op(struct pt_regs *, enum exception_code);
|
||||
extern asmlinkage void fpu_init_state(void);
|
||||
extern asmlinkage void fpu_save(struct fpu_state_struct *);
|
||||
extern asmlinkage void fpu_restore(struct fpu_state_struct *);
|
||||
#else
|
||||
#define fpu_save(a)
|
||||
#define fpu_restore(a)
|
||||
#endif /* CONFIG_FPU */
|
||||
|
||||
/*
|
||||
* signal frame handlers
|
||||
*/
|
||||
extern int fpu_setup_sigcontext(struct fpucontext *buf);
|
||||
extern int fpu_restore_sigcontext(struct fpucontext *buf);
|
||||
|
||||
static inline void unlazy_fpu(struct task_struct *tsk)
|
||||
{
|
||||
preempt_disable();
|
||||
#ifndef CONFIG_LAZY_SAVE_FPU
|
||||
if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
|
||||
fpu_save(&tsk->thread.fpu_state);
|
||||
tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
|
||||
tsk->thread.uregs->epsw &= ~EPSW_FE;
|
||||
}
|
||||
#else
|
||||
if (fpu_state_owner == tsk)
|
||||
fpu_save(&tsk->thread.fpu_state);
|
||||
#endif
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
static inline void exit_fpu(void)
|
||||
{
|
||||
#ifdef CONFIG_LAZY_SAVE_FPU
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
preempt_disable();
|
||||
if (fpu_state_owner == tsk)
|
||||
fpu_state_owner = NULL;
|
||||
preempt_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void flush_fpu(void)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
preempt_disable();
|
||||
#ifndef CONFIG_LAZY_SAVE_FPU
|
||||
if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
|
||||
tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
|
||||
tsk->thread.uregs->epsw &= ~EPSW_FE;
|
||||
}
|
||||
#else
|
||||
if (fpu_state_owner == tsk) {
|
||||
fpu_state_owner = NULL;
|
||||
tsk->thread.uregs->epsw &= ~EPSW_FE;
|
||||
}
|
||||
#endif
|
||||
preempt_enable();
|
||||
clear_using_fpu(tsk);
|
||||
}
|
||||
|
||||
#else /* CONFIG_FPU */
|
||||
|
||||
extern asmlinkage
|
||||
void unexpected_fpu_exception(struct pt_regs *, enum exception_code);
|
||||
#define fpu_invalid_op unexpected_fpu_exception
|
||||
#define fpu_exception unexpected_fpu_exception
|
||||
|
||||
struct task_struct;
|
||||
struct fpu_state_struct;
|
||||
static inline bool is_using_fpu(struct task_struct *tsk) { return false; }
|
||||
static inline void set_using_fpu(struct task_struct *tsk) {}
|
||||
static inline void clear_using_fpu(struct task_struct *tsk) {}
|
||||
static inline void fpu_init_state(void) {}
|
||||
static inline void fpu_save(struct fpu_state_struct *s) {}
|
||||
static inline void fpu_kill_state(struct task_struct *tsk) {}
|
||||
static inline void unlazy_fpu(struct task_struct *tsk) {}
|
||||
static inline void exit_fpu(void) {}
|
||||
static inline void flush_fpu(void) {}
|
||||
static inline int fpu_setup_sigcontext(struct fpucontext *buf) { return 0; }
|
||||
static inline int fpu_restore_sigcontext(struct fpucontext *buf) { return 0; }
|
||||
#endif /* CONFIG_FPU */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* _ASM_FPU_H */
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#ifndef __ASM_OFFSETS_H__
|
||||
#include <asm/asm-offsets.h>
|
||||
#endif
|
||||
#include <asm/thread_info.h>
|
||||
|
||||
#define pi break
|
||||
|
||||
@@ -37,11 +38,15 @@
|
||||
movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp)
|
||||
mov sp,fp # FRAME pointer in A3
|
||||
add -12,sp # allow for calls to be made
|
||||
mov (__frame),a1
|
||||
mov a1,(REG_NEXT,fp)
|
||||
mov fp,(__frame)
|
||||
|
||||
and ~EPSW_FE,epsw # disable the FPU inside the kernel
|
||||
# push the exception frame onto the front of the list
|
||||
GET_THREAD_INFO a1
|
||||
mov (TI_frame,a1),a0
|
||||
mov a0,(REG_NEXT,fp)
|
||||
mov fp,(TI_frame,a1)
|
||||
|
||||
# disable the FPU inside the kernel
|
||||
and ~EPSW_FE,epsw
|
||||
|
||||
# we may be holding current in E2
|
||||
#ifdef CONFIG_MN10300_CURRENT_IN_E2
|
||||
@@ -57,10 +62,11 @@
|
||||
.macro RESTORE_ALL
|
||||
# peel back the stack to the calling frame
|
||||
# - this permits execve() to discard extra frames due to kernel syscalls
|
||||
mov (__frame),fp
|
||||
GET_THREAD_INFO a0
|
||||
mov (TI_frame,a0),fp
|
||||
mov fp,sp
|
||||
mov (REG_NEXT,fp),d0 # userspace has regs->next == 0
|
||||
mov d0,(__frame)
|
||||
mov (REG_NEXT,fp),d0
|
||||
mov d0,(TI_frame,a0) # userspace has regs->next == 0
|
||||
|
||||
#ifndef CONFIG_MN10300_USING_JTAG
|
||||
mov (REG_EPSW,fp),d0
|
||||
|
||||
@@ -110,7 +110,7 @@ extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code);
|
||||
extern asmlinkage void __gdbstub_bug_trap(void);
|
||||
extern asmlinkage void __gdbstub_pause(void);
|
||||
|
||||
#ifndef CONFIG_MN10300_CACHE_DISABLED
|
||||
#ifdef CONFIG_MN10300_CACHE_ENABLED
|
||||
extern asmlinkage void gdbstub_purge_cache(void);
|
||||
#else
|
||||
#define gdbstub_purge_cache() do {} while (0)
|
||||
|
||||
@@ -19,9 +19,10 @@
|
||||
/* assembly code in softirq.h is sensitive to the offsets of these fields */
|
||||
typedef struct {
|
||||
unsigned int __softirq_pending;
|
||||
unsigned long idle_timestamp;
|
||||
#ifdef CONFIG_MN10300_WD_TIMER
|
||||
unsigned int __nmi_count; /* arch dependent */
|
||||
unsigned int __irq_count; /* arch dependent */
|
||||
#endif
|
||||
} ____cacheline_aligned irq_cpustat_t;
|
||||
|
||||
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
|
||||
|
||||
@@ -87,7 +87,7 @@ static inline unsigned long __kmap_atomic(struct page *page)
|
||||
BUG();
|
||||
#endif
|
||||
set_pte(kmap_pte - idx, mk_pte(page, kmap_prot));
|
||||
__flush_tlb_one(vaddr);
|
||||
local_flush_tlb_one(vaddr);
|
||||
|
||||
return vaddr;
|
||||
}
|
||||
@@ -116,7 +116,7 @@ static inline void __kunmap_atomic(unsigned long vaddr)
|
||||
* this pte without first remap it
|
||||
*/
|
||||
pte_clear(kmap_pte - idx);
|
||||
__flush_tlb_one(vaddr);
|
||||
local_flush_tlb_one(vaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user