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Merge tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform conversion patches from Olof Johansson: "Here are more patches in the progression towards multiplatform, sparse irq conversions in particular. Tegra has a handful of cleanups and general groundwork, but is not quite there yet on full enablement. Platforms that are enabled through this branch are VT8500 and Zynq. Note that i.MX was converted in one of the earlier cleanup branches as well (before we started a separate topic for multiplatform). And both new platforms for this merge window, sunxi and bcm, were merged with multiplatform support enabled." Fix up conflicts mostly as per Olof. * tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: zynq: Remove all unused mach headers ARM: zynq: add support for ARCH_MULTIPLATFORM ARM: zynq: make use of debug_ll_io_init() ARM: zynq: remove TTC early mapping ARM: tegra: move debug-macro.S to include/debug ARM: tegra: don't include iomap.h from debug-macro.S ARM: tegra: decouple uncompress.h and debug-macro.S ARM: tegra: simplify DEBUG_LL UART selection options ARM: tegra: select SPARSE_IRQ ARM: tegra: enhance timer.c to get IO address from device tree ARM: tegra: enhance timer.c to get IRQ info from device tree ARM: timer: fix checkpatch warnings ARM: tegra: add TWD to device tree ARM: tegra: define DT bindings for and instantiate RTC ARM: tegra: define DT bindings for and instantiate timer clocksource/mtu-nomadik: use apb_pclk clk: ux500: Register mtu apb_pclocks ARM: plat-nomadik: convert platforms to SPARSE_IRQ mfd/db8500-prcmu: use the irq_domain_add_simple() mfd/ab8500-core: use irq_domain_add_simple() ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,19 @@
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||||
NVIDIA Tegra20 real-time clock
|
||||
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
|
||||
registers. The alarms and other interrupts may wake the system from low-power
|
||||
state.
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||||
|
||||
Required properties:
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||||
|
||||
- compatible : should be "nvidia,tegra20-rtc".
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||||
- reg : Specifies base physical address and size of the registers.
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- interrupts : A single interrupt specifier.
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|
||||
Example:
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|
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timer {
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compatible = "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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};
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@@ -0,0 +1,21 @@
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NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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|
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Required properties:
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||||
|
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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|
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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};
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@@ -0,0 +1,23 @@
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NVIDIA Tegra30 timer
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
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running counter, and 5 watchdog modules. The first two channels may also
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trigger a legacy watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
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+10
-14
@@ -650,6 +650,7 @@ config ARCH_TEGRA
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select HAVE_CLK
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select SPARSE_IRQ
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select USE_OF
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help
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This enables support for NVIDIA Tegra based systems (Tegra APX,
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@@ -891,6 +892,7 @@ config ARCH_U8500
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select GENERIC_CLOCKEVENTS
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select SPARSE_IRQ
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help
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Support for ST-Ericsson's Ux500 architecture
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@@ -905,6 +907,7 @@ config ARCH_NOMADIK
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select MIGHT_HAVE_CACHE_L2X0
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select PINCTRL
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select PINCTRL_STN8815
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select SPARSE_IRQ
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help
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Support for the Nomadik platform by ST-Ericsson
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@@ -948,7 +951,7 @@ config ARCH_OMAP
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help
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Support for TI's OMAP platform (OMAP1/2/3/4).
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config ARCH_VT8500
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config ARCH_VT8500_SINGLE
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bool "VIA/WonderMedia 85xx"
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select ARCH_HAS_CPUFREQ
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select ARCH_REQUIRE_GPIOLIB
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@@ -958,22 +961,12 @@ config ARCH_VT8500
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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select HAVE_CLK
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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select USE_OF
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help
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Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
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config ARCH_ZYNQ
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bool "Xilinx Zynq ARM Cortex A9 Platform"
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select ARM_AMBA
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select ARM_GIC
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select COMMON_CLK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select ICST
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select MIGHT_HAVE_CACHE_L2X0
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select USE_OF
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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endchoice
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menu "Multiple platform selection"
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@@ -1074,7 +1067,6 @@ source "arch/arm/mach-mxs/Kconfig"
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source "arch/arm/mach-netx/Kconfig"
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source "arch/arm/mach-nomadik/Kconfig"
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source "arch/arm/plat-nomadik/Kconfig"
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source "arch/arm/plat-omap/Kconfig"
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@@ -1137,8 +1129,12 @@ source "arch/arm/mach-versatile/Kconfig"
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source "arch/arm/mach-vexpress/Kconfig"
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source "arch/arm/plat-versatile/Kconfig"
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source "arch/arm/mach-vt8500/Kconfig"
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source "arch/arm/mach-w90x900/Kconfig"
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source "arch/arm/mach-zynq/Kconfig"
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# Definitions to make life easier
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config ARCH_ACORN
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bool
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@@ -379,6 +379,13 @@ choice
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Say Y here if you want kernel low-level debugging support
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on Allwinner A1X based platforms on the UART1.
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config DEBUG_TEGRA_UART
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depends on ARCH_TEGRA
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bool "Use Tegra UART for low-level debug"
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help
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||||
Say Y here if you want kernel low-level debugging support
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on Tegra based platforms.
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config DEBUG_VEXPRESS_UART0_DETECT
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bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
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depends on ARCH_VEXPRESS && CPU_CP15_MMU
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@@ -452,6 +459,36 @@ config DEBUG_IMX6Q_UART_PORT
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Choose UART port on which kernel low-level debug messages
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should be output.
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choice
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prompt "Low-level debug console UART"
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depends on DEBUG_LL && DEBUG_TEGRA_UART
|
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|
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config TEGRA_DEBUG_UART_AUTO_ODMDATA
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bool "Via ODMDATA"
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help
|
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Automatically determines which UART to use for low-level debug based
|
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on the ODMDATA value. This value is part of the BCT, and is written
|
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to the boot memory device using nvflash, or other flashing tool.
|
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When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
|
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0/1/2/3/4 are UART A/B/C/D/E.
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|
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config TEGRA_DEBUG_UARTA
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bool "UART A"
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|
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config TEGRA_DEBUG_UARTB
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bool "UART B"
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config TEGRA_DEBUG_UARTC
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bool "UART C"
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config TEGRA_DEBUG_UARTD
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bool "UART D"
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config TEGRA_DEBUG_UARTE
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bool "UART E"
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|
||||
endchoice
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config DEBUG_LL_INCLUDE
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string
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default "debug/icedcc.S" if DEBUG_ICEDCC
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@@ -469,6 +506,8 @@ config DEBUG_LL_INCLUDE
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default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
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default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
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DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
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default "debug/tegra.S" if DEBUG_TEGRA_UART
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default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
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default "mach/debug-macro.S"
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config EARLY_PRINTK
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@@ -202,7 +202,6 @@ machine-$(CONFIG_ARCH_SUNXI) += sunxi
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plat-$(CONFIG_ARCH_OMAP) += omap
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plat-$(CONFIG_ARCH_S3C64XX) += samsung
|
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plat-$(CONFIG_PLAT_IOP) += iop
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plat-$(CONFIG_PLAT_NOMADIK) += nomadik
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plat-$(CONFIG_PLAT_ORION) += orion
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plat-$(CONFIG_PLAT_PXA) += pxa
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plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung
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@@ -91,6 +91,12 @@
|
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};
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};
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|
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timer@50004600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x50040600 0x20>;
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interrupts = <1 13 0x304>;
|
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};
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||||
|
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cache-controller@50043000 {
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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@@ -108,6 +114,15 @@
|
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#interrupt-cells = <3>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
|
||||
0 1 0x04
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0 41 0x04
|
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0 42 0x04>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1200>;
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@@ -225,6 +240,12 @@
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#pwm-cells = <2>;
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};
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rtc {
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compatible = "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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@@ -91,6 +91,12 @@
|
||||
};
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};
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timer@50004600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x50040600 0x20>;
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interrupts = <1 13 0xf04>;
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};
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|
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cache-controller@50043000 {
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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@@ -108,6 +114,17 @@
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#interrupt-cells = <3>;
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||||
};
|
||||
|
||||
timer@60005000 {
|
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
|
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reg = <0x60005000 0x400>;
|
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interrupts = <0 0 0x04
|
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0 1 0x04
|
||||
0 41 0x04
|
||||
0 42 0x04
|
||||
0 121 0x04
|
||||
0 122 0x04>;
|
||||
};
|
||||
|
||||
apbdma: dma {
|
||||
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
||||
reg = <0x6000a000 0x1400>;
|
||||
@@ -219,6 +236,12 @@
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
|
||||
reg = <0x7000c000 0x100>;
|
||||
|
||||
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (C) 2010,2011 Google, Inc.
|
||||
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
* Doug Anderson <dianders@chromium.org>
|
||||
* Stephen Warren <swarren@nvidia.com>
|
||||
*
|
||||
* Portions based on mach-omap2's debug-macro.S
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#define UART_SHIFT 2
|
||||
|
||||
/* Physical addresses */
|
||||
#define TEGRA_CLK_RESET_BASE 0x60006000
|
||||
#define TEGRA_APB_MISC_BASE 0x70000000
|
||||
#define TEGRA_UARTA_BASE 0x70006000
|
||||
#define TEGRA_UARTB_BASE 0x70006040
|
||||
#define TEGRA_UARTC_BASE 0x70006200
|
||||
#define TEGRA_UARTD_BASE 0x70006300
|
||||
#define TEGRA_UARTE_BASE 0x70006400
|
||||
#define TEGRA_PMC_BASE 0x7000e400
|
||||
|
||||
#define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
|
||||
#define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
|
||||
#define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c)
|
||||
#define TEGRA_CLK_OUT_ENB_L (TEGRA_CLK_RESET_BASE + 0x10)
|
||||
#define TEGRA_CLK_OUT_ENB_H (TEGRA_CLK_RESET_BASE + 0x14)
|
||||
#define TEGRA_CLK_OUT_ENB_U (TEGRA_CLK_RESET_BASE + 0x18)
|
||||
#define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0)
|
||||
#define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804)
|
||||
|
||||
/*
|
||||
* Must be 1MB-aligned since a 1MB mapping is used early on.
|
||||
* Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
|
||||
*/
|
||||
#define UART_VIRTUAL_BASE 0xfe100000
|
||||
|
||||
#define checkuart(rp, rv, lhu, bit, uart) \
|
||||
/* Load address of CLK_RST register */ \
|
||||
movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
|
||||
movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
|
||||
/* Load value from CLK_RST register */ \
|
||||
ldr rp, [rp, #0] ; \
|
||||
/* Test UART's reset bit */ \
|
||||
tst rp, #(1 << bit) ; \
|
||||
/* If set, can't use UART; jump to save no UART */ \
|
||||
bne 90f ; \
|
||||
/* Load address of CLK_OUT_ENB register */ \
|
||||
movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
|
||||
movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
|
||||
/* Load value from CLK_OUT_ENB register */ \
|
||||
ldr rp, [rp, #0] ; \
|
||||
/* Test UART's clock enable bit */ \
|
||||
tst rp, #(1 << bit) ; \
|
||||
/* If clear, can't use UART; jump to save no UART */ \
|
||||
beq 90f ; \
|
||||
/* Passed all tests, load address of UART registers */ \
|
||||
movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
|
||||
movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
|
||||
/* Jump to save UART address */ \
|
||||
b 91f
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
adr \rp, 99f @ actual addr of 99f
|
||||
ldr \rv, [\rp] @ linked addr is stored there
|
||||
sub \rv, \rv, \rp @ offset between the two
|
||||
ldr \rp, [\rp, #4] @ linked tegra_uart_config
|
||||
sub \tmp, \rp, \rv @ actual tegra_uart_config
|
||||
ldr \rp, [\tmp] @ Load tegra_uart_config
|
||||
cmp \rp, #1 @ needs initialization?
|
||||
bne 100f @ no; go load the addresses
|
||||
mov \rv, #0 @ yes; record init is done
|
||||
str \rv, [\tmp]
|
||||
|
||||
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
|
||||
/* Check ODMDATA */
|
||||
10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
|
||||
movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
|
||||
ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
|
||||
ubfx \rv, \rp, #18, #2 @ 19:18 are console type
|
||||
cmp \rv, #2 @ 2 and 3 mean DCC, UART
|
||||
beq 11f @ some boards swap the meaning
|
||||
cmp \rv, #3 @ so accept either
|
||||
bne 90f
|
||||
11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
|
||||
cmp \rv, #0 @ UART 0?
|
||||
beq 20f
|
||||
cmp \rv, #1 @ UART 1?
|
||||
beq 21f
|
||||
cmp \rv, #2 @ UART 2?
|
||||
beq 22f
|
||||
cmp \rv, #3 @ UART 3?
|
||||
beq 23f
|
||||
cmp \rv, #4 @ UART 4?
|
||||
beq 24f
|
||||
b 90f @ invalid
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTA) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART A validity */
|
||||
20: checkuart(\rp, \rv, L, 6, A)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTB) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART B validity */
|
||||
21: checkuart(\rp, \rv, L, 7, B)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTC) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART C validity */
|
||||
22: checkuart(\rp, \rv, H, 23, C)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTD) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART D validity */
|
||||
23: checkuart(\rp, \rv, U, 1, D)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTE) || \
|
||||
defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
/* Check UART E validity */
|
||||
24:
|
||||
checkuart(\rp, \rv, U, 2, E)
|
||||
#endif
|
||||
|
||||
/* No valid UART found */
|
||||
90: mov \rp, #0
|
||||
/* fall through */
|
||||
|
||||
/* Record whichever UART we chose */
|
||||
91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
|
||||
cmp \rp, #0 @ Valid UART address?
|
||||
bne 92f @ Yes, go process it
|
||||
str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
|
||||
b 100f @ Done
|
||||
92: and \rv, \rp, #0xffffff @ offset within 1MB section
|
||||
add \rv, \rv, #UART_VIRTUAL_BASE
|
||||
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
|
||||
movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
|
||||
movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
|
||||
ldr \rv, [\rv, #0] @ Load HIDREV
|
||||
ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version
|
||||
cmp \rv, #0x20 @ Tegra20?
|
||||
moveq \rv, #0x75 @ Tegra20 divisor
|
||||
movne \rv, #0xdd @ Tegra30 divisor
|
||||
str \rv, [\tmp, #12] @ Save divisor to scratch
|
||||
/* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
|
||||
mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
|
||||
str \rv, [\rp, #UART_LCR << UART_SHIFT]
|
||||
/* uart[UART_DLL] = div & 0xff; */
|
||||
ldr \rv, [\tmp, #12]
|
||||
and \rv, \rv, #0xff
|
||||
str \rv, [\rp, #UART_DLL << UART_SHIFT]
|
||||
/* uart[UART_DLM] = div >> 8; */
|
||||
ldr \rv, [\tmp, #12]
|
||||
lsr \rv, \rv, #8
|
||||
str \rv, [\rp, #UART_DLM << UART_SHIFT]
|
||||
/* uart[UART_LCR] = UART_LCR_WLEN8; */
|
||||
mov \rv, #UART_LCR_WLEN8
|
||||
str \rv, [\rp, #UART_LCR << UART_SHIFT]
|
||||
b 100f
|
||||
|
||||
.align
|
||||
99: .word .
|
||||
.word tegra_uart_config
|
||||
.ltorg
|
||||
|
||||
/* Load previously selected UART address */
|
||||
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
|
||||
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
|
||||
* check to make sure that the UART address is actually valid.
|
||||
*/
|
||||
|
||||
.macro senduart, rd, rx
|
||||
cmp \rx, #0
|
||||
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
|
||||
1001:
|
||||
.endm
|
||||
|
||||
.macro busyuart, rd, rx
|
||||
cmp \rx, #0
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
|
||||
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
bne 1001b
|
||||
1002:
|
||||
.endm
|
||||
|
||||
.macro waituart, rd, rx
|
||||
#ifdef FLOW_CONTROL
|
||||
cmp \rx, #0
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
|
||||
tst \rd, #UART_MSR_CTS
|
||||
beq 1001b
|
||||
1002:
|
||||
#endif
|
||||
.endm
|
||||
@@ -1,5 +1,4 @@
|
||||
/* arch/arm/mach-zynq/include/mach/debug-macro.S
|
||||
*
|
||||
/*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 2011 Xilinx
|
||||
@@ -13,9 +12,25 @@
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
|
||||
#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
|
||||
#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
|
||||
|
||||
#include <mach/zynq_soc.h>
|
||||
#include <mach/uart.h>
|
||||
#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
|
||||
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
|
||||
|
||||
#define UART0_PHYS 0xE0000000
|
||||
#define UART1_PHYS 0xE0001000
|
||||
#define UART_SIZE SZ_4K
|
||||
#define UART_VIRT 0xF0001000
|
||||
|
||||
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
|
||||
# define LL_UART_PADDR UART1_PHYS
|
||||
#else
|
||||
# define LL_UART_PADDR UART0_PHYS
|
||||
#endif
|
||||
|
||||
#define LL_UART_VADDR UART_VIRT
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, =LL_UART_PADDR @ physical
|
||||
@@ -4,7 +4,7 @@ menu "Nomadik boards"
|
||||
|
||||
config MACH_NOMADIK_8815NHK
|
||||
bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
|
||||
select HAS_MTU
|
||||
select CLKSRC_NOMADIK_MTU
|
||||
select NOMADIK_8815
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -25,18 +25,16 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
#include <linux/platform_data/mtd-nomadik-nand.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/flash.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <plat/mtu.h>
|
||||
|
||||
#include <linux/platform_data/mtd-nomadik-nand.h>
|
||||
#include <mach/fsmc.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "cpu-8815.h"
|
||||
|
||||
@@ -260,7 +258,7 @@ static void __init nomadik_timer_init(void)
|
||||
src_cr |= SRC_CR_INIT_VAL;
|
||||
writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
|
||||
|
||||
nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE));
|
||||
nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0);
|
||||
}
|
||||
|
||||
static struct sys_timer nomadik_timer = {
|
||||
|
||||
@@ -72,7 +72,7 @@
|
||||
#define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */
|
||||
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET)
|
||||
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET)
|
||||
#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
|
||||
#define NOMADIK_NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
|
||||
|
||||
/* Following two are used by entry_macro.S, to access our dual-vic */
|
||||
#define VIC_REG_IRQSR0 0
|
||||
|
||||
@@ -57,57 +57,6 @@ config TEGRA_AHB
|
||||
which controls AHB bus master arbitration and some
|
||||
perfomance parameters(priority, prefech size).
|
||||
|
||||
choice
|
||||
prompt "Default low-level debug console UART"
|
||||
default TEGRA_DEBUG_UART_NONE
|
||||
|
||||
config TEGRA_DEBUG_UART_NONE
|
||||
bool "None"
|
||||
|
||||
config TEGRA_DEBUG_UARTA
|
||||
bool "UART-A"
|
||||
|
||||
config TEGRA_DEBUG_UARTB
|
||||
bool "UART-B"
|
||||
|
||||
config TEGRA_DEBUG_UARTC
|
||||
bool "UART-C"
|
||||
|
||||
config TEGRA_DEBUG_UARTD
|
||||
bool "UART-D"
|
||||
|
||||
config TEGRA_DEBUG_UARTE
|
||||
bool "UART-E"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Automatic low-level debug console UART"
|
||||
default TEGRA_DEBUG_UART_AUTO_NONE
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_NONE
|
||||
bool "None"
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_ODMDATA
|
||||
bool "Via ODMDATA"
|
||||
help
|
||||
Automatically determines which UART to use for low-level debug based
|
||||
on the ODMDATA value. This value is part of the BCT, and is written
|
||||
to the boot memory device using nvflash, or other flashing tool.
|
||||
When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
|
||||
0/1/2/3/4 are UART A/B/C/D/E.
|
||||
|
||||
config TEGRA_DEBUG_UART_AUTO_SCRATCH
|
||||
bool "Via UART scratch register"
|
||||
help
|
||||
Automatically determines which UART to use for low-level debug based
|
||||
on the UART scratch register value. Some bootloaders put ASCII 'D'
|
||||
in this register when they initialize their own console UART output.
|
||||
Using this option allows the kernel to automatically pick the same
|
||||
UART.
|
||||
|
||||
endchoice
|
||||
|
||||
config TEGRA_EMC_SCALING_ENABLE
|
||||
bool "Enable scaling the memory frequency"
|
||||
|
||||
|
||||
@@ -45,14 +45,15 @@
|
||||
* kernel is loaded. The data is declared here rather than debug-macro.S so
|
||||
* that multiple inclusions of debug-macro.S point at the same data.
|
||||
*/
|
||||
#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
|
||||
u32 tegra_uart_config[3] = {
|
||||
u32 tegra_uart_config[4] = {
|
||||
/* Debug UART initialization required */
|
||||
1,
|
||||
/* Debug UART physical address */
|
||||
(u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
|
||||
0,
|
||||
/* Debug UART virtual address */
|
||||
(u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
|
||||
0,
|
||||
/* Scratch space for debug macro */
|
||||
0,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
@@ -1,100 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-tegra/include/mach/debug-macro.S
|
||||
*
|
||||
* Copyright (C) 2010,2011 Google, Inc.
|
||||
* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
* Doug Anderson <dianders@chromium.org>
|
||||
* Stephen Warren <swarren@nvidia.com>
|
||||
*
|
||||
* Portions based on mach-omap2's debug-macro.S
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include "../../iomap.h"
|
||||
#include "../../irammap.h"
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
adr \rp, 99f @ actual addr of 99f
|
||||
ldr \rv, [\rp] @ linked addr is stored there
|
||||
sub \rv, \rv, \rp @ offset between the two
|
||||
ldr \rp, [\rp, #4] @ linked tegra_uart_config
|
||||
sub \tmp, \rp, \rv @ actual tegra_uart_config
|
||||
ldr \rp, [\tmp] @ Load tegra_uart_config
|
||||
cmp \rp, #1 @ needs intitialization?
|
||||
bne 100f @ no; go load the addresses
|
||||
mov \rv, #0 @ yes; record init is done
|
||||
str \rv, [\tmp]
|
||||
mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
|
||||
ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
|
||||
movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
|
||||
movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
|
||||
cmp \rv, \rp @ Cookie present?
|
||||
bne 100f @ No, use default UART
|
||||
mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
|
||||
ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
|
||||
str \rv, [\tmp, #4] @ Store in tegra_uart_phys
|
||||
sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
|
||||
add \rv, \rv, #IO_APB_VIRT
|
||||
str \rv, [\tmp, #8] @ Store in tegra_uart_virt
|
||||
b 100f
|
||||
|
||||
.align
|
||||
99: .word .
|
||||
.word tegra_uart_config
|
||||
.ltorg
|
||||
|
||||
100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
|
||||
ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
|
||||
/*
|
||||
* Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
|
||||
* check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
|
||||
* We use the fact that all 5 valid UART addresses all have something in the
|
||||
* 2nd-to-lowest byte.
|
||||
*/
|
||||
|
||||
.macro senduart, rd, rx
|
||||
tst \rx, #0x0000ff00
|
||||
strneb \rd, [\rx, #UART_TX << UART_SHIFT]
|
||||
1001:
|
||||
.endm
|
||||
|
||||
.macro busyuart, rd, rx
|
||||
tst \rx, #0x0000ff00
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
|
||||
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
|
||||
bne 1001b
|
||||
1002:
|
||||
.endm
|
||||
|
||||
.macro waituart, rd, rx
|
||||
#ifdef FLOW_CONTROL
|
||||
tst \rx, #0x0000ff00
|
||||
beq 1002f
|
||||
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
|
||||
tst \rd, #UART_MSR_CTS
|
||||
beq 1001b
|
||||
1002:
|
||||
#endif
|
||||
.endm
|
||||
@@ -1,182 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-tegra/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (C) 2010 Google, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
* Erik Gilling <konkers@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MACH_TEGRA_IRQS_H
|
||||
#define __MACH_TEGRA_IRQS_H
|
||||
|
||||
#define INT_GIC_BASE 0
|
||||
|
||||
#define IRQ_LOCALTIMER 29
|
||||
|
||||
/* Primary Interrupt Controller */
|
||||
#define INT_PRI_BASE (INT_GIC_BASE + 32)
|
||||
#define INT_TMR1 (INT_PRI_BASE + 0)
|
||||
#define INT_TMR2 (INT_PRI_BASE + 1)
|
||||
#define INT_RTC (INT_PRI_BASE + 2)
|
||||
#define INT_I2S2 (INT_PRI_BASE + 3)
|
||||
#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
|
||||
#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
|
||||
#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
|
||||
#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
|
||||
#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
|
||||
#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
|
||||
#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
|
||||
#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
|
||||
#define INT_VDE_SXE (INT_PRI_BASE + 12)
|
||||
#define INT_I2S1 (INT_PRI_BASE + 13)
|
||||
#define INT_SDMMC1 (INT_PRI_BASE + 14)
|
||||
#define INT_SDMMC2 (INT_PRI_BASE + 15)
|
||||
#define INT_XIO (INT_PRI_BASE + 16)
|
||||
#define INT_VDE (INT_PRI_BASE + 17)
|
||||
#define INT_AVP_UCQ (INT_PRI_BASE + 18)
|
||||
#define INT_SDMMC3 (INT_PRI_BASE + 19)
|
||||
#define INT_USB (INT_PRI_BASE + 20)
|
||||
#define INT_USB2 (INT_PRI_BASE + 21)
|
||||
#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
|
||||
#define INT_EIDE (INT_PRI_BASE + 23)
|
||||
#define INT_NANDFLASH (INT_PRI_BASE + 24)
|
||||
#define INT_VCP (INT_PRI_BASE + 25)
|
||||
#define INT_APB_DMA (INT_PRI_BASE + 26)
|
||||
#define INT_AHB_DMA (INT_PRI_BASE + 27)
|
||||
#define INT_GNT_0 (INT_PRI_BASE + 28)
|
||||
#define INT_GNT_1 (INT_PRI_BASE + 29)
|
||||
#define INT_OWR (INT_PRI_BASE + 30)
|
||||
#define INT_SDMMC4 (INT_PRI_BASE + 31)
|
||||
|
||||
/* Secondary Interrupt Controller */
|
||||
#define INT_SEC_BASE (INT_PRI_BASE + 32)
|
||||
#define INT_GPIO1 (INT_SEC_BASE + 0)
|
||||
#define INT_GPIO2 (INT_SEC_BASE + 1)
|
||||
#define INT_GPIO3 (INT_SEC_BASE + 2)
|
||||
#define INT_GPIO4 (INT_SEC_BASE + 3)
|
||||
#define INT_UARTA (INT_SEC_BASE + 4)
|
||||
#define INT_UARTB (INT_SEC_BASE + 5)
|
||||
#define INT_I2C (INT_SEC_BASE + 6)
|
||||
#define INT_SPI (INT_SEC_BASE + 7)
|
||||
#define INT_TWC (INT_SEC_BASE + 8)
|
||||
#define INT_TMR3 (INT_SEC_BASE + 9)
|
||||
#define INT_TMR4 (INT_SEC_BASE + 10)
|
||||
#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
|
||||
#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
|
||||
#define INT_SPDIF (INT_SEC_BASE + 13)
|
||||
#define INT_UARTC (INT_SEC_BASE + 14)
|
||||
#define INT_MIPI (INT_SEC_BASE + 15)
|
||||
#define INT_EVENTA (INT_SEC_BASE + 16)
|
||||
#define INT_EVENTB (INT_SEC_BASE + 17)
|
||||
#define INT_EVENTC (INT_SEC_BASE + 18)
|
||||
#define INT_EVENTD (INT_SEC_BASE + 19)
|
||||
#define INT_VFIR (INT_SEC_BASE + 20)
|
||||
#define INT_DVC (INT_SEC_BASE + 21)
|
||||
#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
|
||||
#define INT_GPIO5 (INT_SEC_BASE + 23)
|
||||
#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
|
||||
#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25)
|
||||
#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
|
||||
#define INT_S_LINK1 (INT_SEC_BASE + 27)
|
||||
#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
|
||||
#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
|
||||
#define INT_DMA_TX (INT_SEC_BASE + 30)
|
||||
#define INT_DMA_RX (INT_SEC_BASE + 31)
|
||||
|
||||
/* Tertiary Interrupt Controller */
|
||||
#define INT_TRI_BASE (INT_SEC_BASE + 32)
|
||||
#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
|
||||
#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
|
||||
#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
|
||||
#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
|
||||
#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
|
||||
#define INT_VI_GENERAL (INT_TRI_BASE + 5)
|
||||
#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
|
||||
#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
|
||||
#define INT_2D_GENERAL (INT_TRI_BASE + 8)
|
||||
#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
|
||||
#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
|
||||
#define INT_HDMI (INT_TRI_BASE + 11)
|
||||
#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
|
||||
#define INT_MC_GENERAL (INT_TRI_BASE + 13)
|
||||
#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
|
||||
#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
|
||||
#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
|
||||
#define INT_AC97 (INT_TRI_BASE + 17)
|
||||
#define INT_SPI_2 (INT_TRI_BASE + 18)
|
||||
#define INT_SPI_3 (INT_TRI_BASE + 19)
|
||||
#define INT_I2C2 (INT_TRI_BASE + 20)
|
||||
#define INT_KBC (INT_TRI_BASE + 21)
|
||||
#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
|
||||
#define INT_GPIO6 (INT_TRI_BASE + 23)
|
||||
#define INT_TVDAC (INT_TRI_BASE + 24)
|
||||
#define INT_GPIO7 (INT_TRI_BASE + 25)
|
||||
#define INT_UARTD (INT_TRI_BASE + 26)
|
||||
#define INT_UARTE (INT_TRI_BASE + 27)
|
||||
#define INT_I2C3 (INT_TRI_BASE + 28)
|
||||
#define INT_SPI_4 (INT_TRI_BASE + 29)
|
||||
#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
|
||||
#define INT_SW_RESERVED (INT_TRI_BASE + 31)
|
||||
|
||||
/* Quaternary Interrupt Controller */
|
||||
#define INT_QUAD_BASE (INT_TRI_BASE + 32)
|
||||
#define INT_SNOR (INT_QUAD_BASE + 0)
|
||||
#define INT_USB3 (INT_QUAD_BASE + 1)
|
||||
#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
|
||||
#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
|
||||
#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
|
||||
#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
|
||||
#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
|
||||
#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
|
||||
#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
|
||||
#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
|
||||
#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
|
||||
#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
|
||||
#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
|
||||
#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
|
||||
#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
|
||||
#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
|
||||
#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
|
||||
#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
|
||||
#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
|
||||
#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
|
||||
#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
|
||||
#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
|
||||
#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
|
||||
#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
|
||||
#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
|
||||
#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
|
||||
#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
|
||||
#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
|
||||
#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
|
||||
#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
|
||||
#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
|
||||
#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
|
||||
|
||||
/* Tegra30 has 5 banks of 32 IRQs */
|
||||
#define INT_MAIN_NR (32 * 5)
|
||||
#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
|
||||
|
||||
/* Tegra30 has 8 banks of 32 GPIOs */
|
||||
#define INT_GPIO_NR (32 * 8)
|
||||
|
||||
#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
|
||||
|
||||
#define INT_BOARD_BASE TEGRA_NR_IRQS
|
||||
#define NR_BOARD_IRQS 32
|
||||
|
||||
#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
|
||||
|
||||
#endif
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <linux/serial_reg.h>
|
||||
|
||||
#include "../../iomap.h"
|
||||
#include "../../irammap.h"
|
||||
|
||||
#define BIT(x) (1 << (x))
|
||||
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
|
||||
@@ -52,17 +51,6 @@ static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void save_uart_address(void)
|
||||
{
|
||||
u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
|
||||
|
||||
if (uart) {
|
||||
buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
|
||||
buf[1] = (u32)uart;
|
||||
} else
|
||||
buf[0] = 0;
|
||||
}
|
||||
|
||||
static const struct {
|
||||
u32 base;
|
||||
u32 reset_reg;
|
||||
@@ -139,51 +127,19 @@ int auto_odmdata(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
|
||||
int auto_scratch(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Look for the first UART that:
|
||||
* a) Is not in reset.
|
||||
* b) Is clocked.
|
||||
* c) Has a 'D' in the scratchpad register.
|
||||
*
|
||||
* Note that on Tegra30, the first two conditions are required, since
|
||||
* if not true, accesses to the UART scratch register will hang.
|
||||
* Tegra20 doesn't have this issue.
|
||||
*
|
||||
* The intent is that the bootloader will tell the kernel which UART
|
||||
* to use by setting up those conditions. If nothing found, we'll fall
|
||||
* back to what's specified in TEGRA_DEBUG_UART_BASE.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(uarts); i++) {
|
||||
if (!uart_clocked(i))
|
||||
continue;
|
||||
|
||||
uart = (volatile u8 *)uarts[i].base;
|
||||
if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
|
||||
continue;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Setup before decompression. This is where we do UART selection for
|
||||
* earlyprintk and init the uart_base register.
|
||||
*/
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int uart_id, auto_uart_id;
|
||||
int uart_id;
|
||||
volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
|
||||
u32 chip, div;
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
uart_id = auto_odmdata();
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
uart_id = 0;
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
|
||||
uart_id = 1;
|
||||
@@ -193,27 +149,14 @@ static inline void arch_decomp_setup(void)
|
||||
uart_id = 3;
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
|
||||
uart_id = 4;
|
||||
#else
|
||||
uart_id = -1;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
|
||||
auto_uart_id = auto_odmdata();
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
|
||||
auto_uart_id = auto_scratch();
|
||||
#else
|
||||
auto_uart_id = -1;
|
||||
#endif
|
||||
if (auto_uart_id != -1)
|
||||
uart_id = auto_uart_id;
|
||||
|
||||
if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
|
||||
!uart_clocked(uart_id))
|
||||
uart = NULL;
|
||||
else
|
||||
uart = (volatile u8 *)uarts[uart_id].base;
|
||||
|
||||
save_uart_address();
|
||||
if (uart == NULL)
|
||||
return;
|
||||
|
||||
|
||||
@@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = {
|
||||
|
||||
void __init tegra_map_common_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
|
||||
}
|
||||
|
||||
@@ -261,20 +261,6 @@
|
||||
#define TEGRA_SDMMC4_BASE 0xC8000600
|
||||
#define TEGRA_SDMMC4_SIZE SZ_512
|
||||
|
||||
#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
|
||||
# define TEGRA_DEBUG_UART_BASE 0
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
|
||||
#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
|
||||
# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
|
||||
#endif
|
||||
|
||||
/* On TEGRA, many peripherals are very closely packed in
|
||||
* two 256MB io windows (that actually only use about 64KB
|
||||
* at the start of each).
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user