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intel_th: Add Global Trace Hub driver
Global Trace Hub (GTH) is the central component of Intel TH architecture; it carries out switching between the trace sources and trace outputs, can enable/disable tracing, perform STP encoding, internal buffering, control backpressure from outputs to sources and so on. This property is also reflected in the software model; GTH (switch) driver is required for the other subdevices to probe, because it matches trace output devices against its output ports and configures them accordingly. It also implements an interface for output ports to request trace enabling or disabling and a few other useful things. For userspace, it provides an attribute group "masters", which allows configuration of per-master trace output destinations for up to master 255 and "256+" meaning "masters 256 and above". It also provides an attribute group to discover and configure some of the parameters of its output ports, called "outputs". Via these the user can set up data retention policy for an individual output port or check if it is in reset state. Signed-off-by: Laurent Fert <laurent.fert@intel.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Shishkin
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
2b0b16d329
commit
b27a6a3f97
@@ -0,0 +1,49 @@
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/masters/*
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) Configure output ports for STP masters. Writing -1
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disables a master; any
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_port
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RO) Output port type:
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0: not present,
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1: MSU (Memory Storage Unit)
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2: CTP (Common Trace Port)
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4: PTI (MIPI PTI).
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_drop
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) Data retention policy setting: keep (0) or drop (1)
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incoming data while output port is in reset.
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_null
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) STP NULL packet generation: enabled (1) or disabled (0).
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_flush
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) Force flush data from byte packing buffer for the output
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port.
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_reset
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RO) Output port is in reset (1).
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What: /sys/bus/intel_th/devices/<intel_th_id>-gth/outputs/[0-7]_smcfreq
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Date: June 2015
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KernelVersion: 4.3
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) STP sync packet frequency for the port. Specifies the
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number of clocks between mainenance packets.
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@@ -24,6 +24,16 @@ config INTEL_TH_PCI
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Say Y here to enable PCI Intel TH support.
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config INTEL_TH_GTH
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tristate "Intel(R) Trace Hub Global Trace Hub"
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help
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Global Trace Hub (GTH) is the central component of the
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Intel TH infrastructure and acts as a switch for source
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and output devices. This driver is required for other
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Intel TH subdevices to initialize.
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Say Y here to enable GTH subdevice of Intel(R) Trace Hub.
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config INTEL_TH_DEBUG
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bool "Intel(R) Trace Hub debugging"
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depends on DEBUG_FS
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@@ -4,3 +4,6 @@ intel_th-$(CONFIG_INTEL_TH_DEBUG) += debug.o
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obj-$(CONFIG_INTEL_TH_PCI) += intel_th_pci.o
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intel_th_pci-y := pci.o
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obj-$(CONFIG_INTEL_TH_GTH) += intel_th_gth.o
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intel_th_gth-y := gth.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,66 @@
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/*
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* Intel(R) Trace Hub Global Trace Hub (GTH) data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __INTEL_TH_GTH_H__
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#define __INTEL_TH_GTH_H__
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/* Map output port parameter bits to symbolic names */
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#define TH_OUTPUT_PARM(name) \
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TH_OUTPUT_ ## name
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enum intel_th_output_parm {
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/* output port type */
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TH_OUTPUT_PARM(port),
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/* generate NULL packet */
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TH_OUTPUT_PARM(null),
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/* packet drop */
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TH_OUTPUT_PARM(drop),
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/* port in reset state */
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TH_OUTPUT_PARM(reset),
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/* flush out data */
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TH_OUTPUT_PARM(flush),
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/* mainenance packet frequency */
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TH_OUTPUT_PARM(smcfreq),
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};
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/*
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* Register offsets
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*/
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enum {
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REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */
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REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */
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REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */
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REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */
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REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */
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REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */
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REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */
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REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */
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REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
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REG_GTH_STAT = 0xd4, /* GTH status */
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REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */
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REG_GTH_DESTOVR = 0xdc, /* Destination override */
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REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */
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REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */
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REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */
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REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */
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};
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/* Externall debugger is using Intel TH */
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#define SCRPD_DEBUGGER_IN_USE BIT(24)
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/* waiting for Pipeline Empty bit(s) to assert for GTH */
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#define GTH_PLE_WAITLOOP_DEPTH 10000
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#endif /* __INTEL_TH_GTH_H__ */
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