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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
Pull rdma qedr RoCE driver from Doug Ledford: "Early on in the merge window I mentioned I had a backlog of new drivers waiting to be reviewed and that, in addition to the hns-roce driver, I wanted to get possible a couple more reviewed. I ended up only having the time to complete one of the additional drivers. During Dave Miller's pull request this go around, there were a series of 9 patches to the QLogic qed net driver that add basic support for a paired RoCE driver. That support is currently not functional because it is missing the matching RoCE driver in the RDMA subsystem. I managed to finish that review. However, because it goes against part of Dave's net pull, and a part that was accepted a day or two after the merge window opened, to apply cleanly it has to be applied to either the tip of Dave's net branch, or as I did in this case, I just applied it to your master after you had taken Dave's pull request." * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: qedr: Add events support and register IB device qedr: Add GSI support qedr: Add LL2 RoCE interface qedr: Add support for data path qedr: Add support for memory registeration verbs qedr: Add support for QP verbs qedr: Add support for PD,PKEY and CQ verbs qedr: Add support for user context verbs qedr: Add support for RoCE HW init qedr: Add RoCE driver framework
This commit is contained in:
Linus Torvalds
@@ -89,4 +89,6 @@ source "drivers/infiniband/sw/rxe/Kconfig"
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source "drivers/infiniband/hw/hfi1/Kconfig"
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source "drivers/infiniband/hw/qedr/Kconfig"
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endif # INFINIBAND
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@@ -10,3 +10,4 @@ obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/
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obj-$(CONFIG_INFINIBAND_USNIC) += usnic/
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obj-$(CONFIG_INFINIBAND_HFI1) += hfi1/
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obj-$(CONFIG_INFINIBAND_HNS) += hns/
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obj-$(CONFIG_INFINIBAND_QEDR) += qedr/
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@@ -0,0 +1,7 @@
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config INFINIBAND_QEDR
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tristate "QLogic RoCE driver"
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depends on 64BIT && QEDE
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select QED_LL2
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---help---
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This driver provides low-level InfiniBand over Ethernet
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support for QLogic QED host channel adapters (HCAs).
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@@ -0,0 +1,3 @@
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obj-$(CONFIG_INFINIBAND_QEDR) := qedr.o
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qedr-y := main.o verbs.o qedr_cm.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,495 @@
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/* QLogic qedr NIC Driver
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* Copyright (c) 2015-2016 QLogic Corporation
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and /or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __QEDR_H__
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#define __QEDR_H__
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#include <linux/pci.h>
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#include <rdma/ib_addr.h>
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#include <linux/qed/qed_if.h>
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#include <linux/qed/qed_chain.h>
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#include <linux/qed/qed_roce_if.h>
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#include <linux/qed/qede_roce.h>
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#include "qedr_hsi.h"
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#define QEDR_MODULE_VERSION "8.10.10.0"
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#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
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#define DP_NAME(dev) ((dev)->ibdev.name)
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#define DP_DEBUG(dev, module, fmt, ...) \
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pr_debug("(%s) " module ": " fmt, \
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DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
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#define QEDR_MSG_INIT "INIT"
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#define QEDR_MSG_MISC "MISC"
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#define QEDR_MSG_CQ " CQ"
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#define QEDR_MSG_MR " MR"
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#define QEDR_MSG_RQ " RQ"
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#define QEDR_MSG_SQ " SQ"
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#define QEDR_MSG_QP " QP"
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#define QEDR_MSG_GSI " GSI"
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#define QEDR_CQ_MAGIC_NUMBER (0x11223344)
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struct qedr_dev;
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struct qedr_cnq {
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struct qedr_dev *dev;
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struct qed_chain pbl;
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struct qed_sb_info *sb;
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char name[32];
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u64 n_comp;
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__le16 *hw_cons_ptr;
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u8 index;
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};
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#define QEDR_MAX_SGID 128
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struct qedr_device_attr {
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u32 vendor_id;
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u32 vendor_part_id;
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u32 hw_ver;
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u64 fw_ver;
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u64 node_guid;
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u64 sys_image_guid;
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u8 max_cnq;
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u8 max_sge;
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u16 max_inline;
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u32 max_sqe;
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u32 max_rqe;
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u8 max_qp_resp_rd_atomic_resc;
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u8 max_qp_req_rd_atomic_resc;
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u64 max_dev_resp_rd_atomic_resc;
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u32 max_cq;
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u32 max_qp;
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u32 max_mr;
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u64 max_mr_size;
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u32 max_cqe;
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u32 max_mw;
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u32 max_fmr;
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u32 max_mr_mw_fmr_pbl;
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u64 max_mr_mw_fmr_size;
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u32 max_pd;
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u32 max_ah;
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u8 max_pkey;
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u32 max_srq;
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u32 max_srq_wr;
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u8 max_srq_sge;
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u8 max_stats_queues;
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u32 dev_caps;
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u64 page_size_caps;
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u8 dev_ack_delay;
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u32 reserved_lkey;
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u32 bad_pkey_counter;
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struct qed_rdma_events events;
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};
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struct qedr_dev {
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struct ib_device ibdev;
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struct qed_dev *cdev;
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struct pci_dev *pdev;
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struct net_device *ndev;
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enum ib_atomic_cap atomic_cap;
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void *rdma_ctx;
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struct qedr_device_attr attr;
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const struct qed_rdma_ops *ops;
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struct qed_int_info int_info;
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struct qed_sb_info *sb_array;
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struct qedr_cnq *cnq_array;
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int num_cnq;
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int sb_start;
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void __iomem *db_addr;
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u64 db_phys_addr;
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u32 db_size;
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u16 dpi;
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union ib_gid *sgid_tbl;
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/* Lock for sgid table */
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spinlock_t sgid_lock;
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u64 guid;
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u32 dp_module;
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u8 dp_level;
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u8 num_hwfns;
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uint wq_multiplier;
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u8 gsi_ll2_mac_address[ETH_ALEN];
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int gsi_qp_created;
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struct qedr_cq *gsi_sqcq;
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struct qedr_cq *gsi_rqcq;
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struct qedr_qp *gsi_qp;
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};
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#define QEDR_MAX_SQ_PBL (0x8000)
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#define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
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#define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
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#define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
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QEDR_SQE_ELEMENT_SIZE)
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#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
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QEDR_SQE_ELEMENT_SIZE)
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#define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
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(RDMA_RING_PAGE_SIZE) / \
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(QEDR_SQE_ELEMENT_SIZE) /\
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(QEDR_MAX_SQE_ELEMENTS_PER_SQE))
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/* RQ */
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#define QEDR_MAX_RQ_PBL (0x2000)
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#define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
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#define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
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#define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
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#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
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QEDR_RQE_ELEMENT_SIZE)
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#define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
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(RDMA_RING_PAGE_SIZE) / \
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(QEDR_RQE_ELEMENT_SIZE) /\
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(QEDR_MAX_RQE_ELEMENTS_PER_RQE))
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#define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
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#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
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#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
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sizeof(u64)) - 1)
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#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
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(QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
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#define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
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#define QEDR_MAX_PORT (1)
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#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
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#define QEDR_ROCE_PKEY_MAX 1
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#define QEDR_ROCE_PKEY_TABLE_LEN 1
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#define QEDR_ROCE_PKEY_DEFAULT 0xffff
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struct qedr_pbl {
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struct list_head list_entry;
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void *va;
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dma_addr_t pa;
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};
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struct qedr_ucontext {
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struct ib_ucontext ibucontext;
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struct qedr_dev *dev;
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struct qedr_pd *pd;
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u64 dpi_addr;
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u64 dpi_phys_addr;
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u32 dpi_size;
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u16 dpi;
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struct list_head mm_head;
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/* Lock to protect mm list */
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struct mutex mm_list_lock;
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};
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union db_prod64 {
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struct rdma_pwm_val32_data data;
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u64 raw;
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};
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enum qedr_cq_type {
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QEDR_CQ_TYPE_GSI,
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QEDR_CQ_TYPE_KERNEL,
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QEDR_CQ_TYPE_USER,
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};
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struct qedr_pbl_info {
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u32 num_pbls;
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u32 num_pbes;
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u32 pbl_size;
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u32 pbe_size;
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bool two_layered;
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};
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struct qedr_userq {
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struct ib_umem *umem;
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struct qedr_pbl_info pbl_info;
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struct qedr_pbl *pbl_tbl;
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u64 buf_addr;
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size_t buf_len;
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};
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struct qedr_cq {
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struct ib_cq ibcq;
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enum qedr_cq_type cq_type;
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u32 sig;
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u16 icid;
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/* Lock to protect completion handler */
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spinlock_t comp_handler_lock;
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/* Lock to protect multiplem CQ's */
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spinlock_t cq_lock;
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u8 arm_flags;
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struct qed_chain pbl;
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void __iomem *db_addr;
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union db_prod64 db;
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u8 pbl_toggle;
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union rdma_cqe *latest_cqe;
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union rdma_cqe *toggle_cqe;
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u32 cq_cons;
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struct qedr_userq q;
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};
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struct qedr_pd {
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struct ib_pd ibpd;
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u32 pd_id;
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struct qedr_ucontext *uctx;
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};
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struct qedr_mm {
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struct {
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u64 phy_addr;
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unsigned long len;
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} key;
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struct list_head entry;
|
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};
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union db_prod32 {
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struct rdma_pwm_val16_data data;
|
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u32 raw;
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};
|
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|
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struct qedr_qp_hwq_info {
|
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/* WQE Elements */
|
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struct qed_chain pbl;
|
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u64 p_phys_addr_tbl;
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u32 max_sges;
|
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|
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/* WQE */
|
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u16 prod;
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u16 cons;
|
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u16 wqe_cons;
|
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u16 gsi_cons;
|
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u16 max_wr;
|
||||
|
||||
/* DB */
|
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void __iomem *db;
|
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union db_prod32 db_data;
|
||||
};
|
||||
|
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#define QEDR_INC_SW_IDX(p_info, index) \
|
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do { \
|
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p_info->index = (p_info->index + 1) & \
|
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qed_chain_get_capacity(p_info->pbl) \
|
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} while (0)
|
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|
||||
enum qedr_qp_err_bitmap {
|
||||
QEDR_QP_ERR_SQ_FULL = 1,
|
||||
QEDR_QP_ERR_RQ_FULL = 2,
|
||||
QEDR_QP_ERR_BAD_SR = 4,
|
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QEDR_QP_ERR_BAD_RR = 8,
|
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QEDR_QP_ERR_SQ_PBL_FULL = 16,
|
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QEDR_QP_ERR_RQ_PBL_FULL = 32,
|
||||
};
|
||||
|
||||
struct qedr_qp {
|
||||
struct ib_qp ibqp; /* must be first */
|
||||
struct qedr_dev *dev;
|
||||
|
||||
struct qedr_qp_hwq_info sq;
|
||||
struct qedr_qp_hwq_info rq;
|
||||
|
||||
u32 max_inline_data;
|
||||
|
||||
/* Lock for QP's */
|
||||
spinlock_t q_lock;
|
||||
struct qedr_cq *sq_cq;
|
||||
struct qedr_cq *rq_cq;
|
||||
struct qedr_srq *srq;
|
||||
enum qed_roce_qp_state state;
|
||||
u32 id;
|
||||
struct qedr_pd *pd;
|
||||
enum ib_qp_type qp_type;
|
||||
struct qed_rdma_qp *qed_qp;
|
||||
u32 qp_id;
|
||||
u16 icid;
|
||||
u16 mtu;
|
||||
int sgid_idx;
|
||||
u32 rq_psn;
|
||||
u32 sq_psn;
|
||||
u32 qkey;
|
||||
u32 dest_qp_num;
|
||||
|
||||
/* Relevant to qps created from kernel space only (ULPs) */
|
||||
u8 prev_wqe_size;
|
||||
u16 wqe_cons;
|
||||
u32 err_bitmap;
|
||||
bool signaled;
|
||||
|
||||
/* SQ shadow */
|
||||
struct {
|
||||
u64 wr_id;
|
||||
enum ib_wc_opcode opcode;
|
||||
u32 bytes_len;
|
||||
u8 wqe_size;
|
||||
bool signaled;
|
||||
dma_addr_t icrc_mapping;
|
||||
u32 *icrc;
|
||||
struct qedr_mr *mr;
|
||||
} *wqe_wr_id;
|
||||
|
||||
/* RQ shadow */
|
||||
struct {
|
||||
u64 wr_id;
|
||||
struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
|
||||
u8 wqe_size;
|
||||
|
||||
u8 smac[ETH_ALEN];
|
||||
u16 vlan_id;
|
||||
int rc;
|
||||
} *rqe_wr_id;
|
||||
|
||||
/* Relevant to qps created from user space only (applications) */
|
||||
struct qedr_userq usq;
|
||||
struct qedr_userq urq;
|
||||
};
|
||||
|
||||
struct qedr_ah {
|
||||
struct ib_ah ibah;
|
||||
struct ib_ah_attr attr;
|
||||
};
|
||||
|
||||
enum qedr_mr_type {
|
||||
QEDR_MR_USER,
|
||||
QEDR_MR_KERNEL,
|
||||
QEDR_MR_DMA,
|
||||
QEDR_MR_FRMR,
|
||||
};
|
||||
|
||||
struct mr_info {
|
||||
struct qedr_pbl *pbl_table;
|
||||
struct qedr_pbl_info pbl_info;
|
||||
struct list_head free_pbl_list;
|
||||
struct list_head inuse_pbl_list;
|
||||
u32 completed;
|
||||
u32 completed_handled;
|
||||
};
|
||||
|
||||
struct qedr_mr {
|
||||
struct ib_mr ibmr;
|
||||
struct ib_umem *umem;
|
||||
|
||||
struct qed_rdma_register_tid_in_params hw_mr;
|
||||
enum qedr_mr_type type;
|
||||
|
||||
struct qedr_dev *dev;
|
||||
struct mr_info info;
|
||||
|
||||
u64 *pages;
|
||||
u32 npages;
|
||||
};
|
||||
|
||||
#define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
|
||||
|
||||
#define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
|
||||
RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
|
||||
#define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
|
||||
RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
|
||||
#define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA)
|
||||
|
||||
static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
|
||||
{
|
||||
info->cons = (info->cons + 1) % info->max_wr;
|
||||
info->wqe_cons++;
|
||||
}
|
||||
|
||||
static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
|
||||
{
|
||||
info->prod = (info->prod + 1) % info->max_wr;
|
||||
}
|
||||
|
||||
static inline int qedr_get_dmac(struct qedr_dev *dev,
|
||||
struct ib_ah_attr *ah_attr, u8 *mac_addr)
|
||||
{
|
||||
union ib_gid zero_sgid = { { 0 } };
|
||||
struct in6_addr in6;
|
||||
|
||||
if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
|
||||
DP_ERR(dev, "Local port GID not supported\n");
|
||||
eth_zero_addr(mac_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
|
||||
ether_addr_copy(mac_addr, ah_attr->dmac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline
|
||||
struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
|
||||
{
|
||||
return container_of(ibucontext, struct qedr_ucontext, ibucontext);
|
||||
}
|
||||
|
||||
static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
|
||||
{
|
||||
return container_of(ibdev, struct qedr_dev, ibdev);
|
||||
}
|
||||
|
||||
static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
|
||||
{
|
||||
return container_of(ibpd, struct qedr_pd, ibpd);
|
||||
}
|
||||
|
||||
static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
|
||||
{
|
||||
return container_of(ibcq, struct qedr_cq, ibcq);
|
||||
}
|
||||
|
||||
static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
|
||||
{
|
||||
return container_of(ibqp, struct qedr_qp, ibqp);
|
||||
}
|
||||
|
||||
static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
|
||||
{
|
||||
return container_of(ibah, struct qedr_ah, ibah);
|
||||
}
|
||||
|
||||
static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
|
||||
{
|
||||
return container_of(ibmr, struct qedr_mr, ibmr);
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,61 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef LINUX_QEDR_CM_H_
|
||||
#define LINUX_QEDR_CM_H_
|
||||
|
||||
#define QEDR_GSI_MAX_RECV_WR (4096)
|
||||
#define QEDR_GSI_MAX_SEND_WR (4096)
|
||||
|
||||
#define QEDR_GSI_MAX_RECV_SGE (1) /* LL2 FW limitation */
|
||||
|
||||
#define ETH_P_ROCE (0x8915)
|
||||
#define QEDR_ROCE_V2_UDP_SPORT (0000)
|
||||
|
||||
static inline u32 qedr_get_ipv4_from_gid(u8 *gid)
|
||||
{
|
||||
return *(u32 *)(void *)&gid[12];
|
||||
}
|
||||
|
||||
/* RDMA CM */
|
||||
int qedr_gsi_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
|
||||
int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
||||
struct ib_recv_wr **bad_wr);
|
||||
int qedr_gsi_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
||||
struct ib_send_wr **bad_wr);
|
||||
struct ib_qp *qedr_create_gsi_qp(struct qedr_dev *dev,
|
||||
struct ib_qp_init_attr *attrs,
|
||||
struct qedr_qp *qp);
|
||||
void qedr_store_gsi_qp_cq(struct qedr_dev *dev,
|
||||
struct qedr_qp *qp, struct ib_qp_init_attr *attrs);
|
||||
int qedr_destroy_gsi_qp(struct qedr_dev *dev);
|
||||
void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info);
|
||||
#endif
|
||||
@@ -0,0 +1,56 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef __QED_HSI_ROCE__
|
||||
#define __QED_HSI_ROCE__
|
||||
|
||||
#include <linux/qed/common_hsi.h>
|
||||
#include <linux/qed/roce_common.h>
|
||||
#include "qedr_hsi_rdma.h"
|
||||
|
||||
/* Affiliated asynchronous events / errors enumeration */
|
||||
enum roce_async_events_type {
|
||||
ROCE_ASYNC_EVENT_NONE = 0,
|
||||
ROCE_ASYNC_EVENT_COMM_EST = 1,
|
||||
ROCE_ASYNC_EVENT_SQ_DRAINED,
|
||||
ROCE_ASYNC_EVENT_SRQ_LIMIT,
|
||||
ROCE_ASYNC_EVENT_LAST_WQE_REACHED,
|
||||
ROCE_ASYNC_EVENT_CQ_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR,
|
||||
ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR,
|
||||
ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR,
|
||||
ROCE_ASYNC_EVENT_SRQ_EMPTY,
|
||||
MAX_ROCE_ASYNC_EVENTS_TYPE
|
||||
};
|
||||
|
||||
#endif /* __QED_HSI_ROCE__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,101 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef __QEDR_VERBS_H__
|
||||
#define __QEDR_VERBS_H__
|
||||
|
||||
int qedr_query_device(struct ib_device *ibdev,
|
||||
struct ib_device_attr *attr, struct ib_udata *udata);
|
||||
int qedr_query_port(struct ib_device *, u8 port, struct ib_port_attr *props);
|
||||
int qedr_modify_port(struct ib_device *, u8 port, int mask,
|
||||
struct ib_port_modify *props);
|
||||
|
||||
int qedr_query_gid(struct ib_device *, u8 port, int index, union ib_gid *gid);
|
||||
|
||||
int qedr_query_pkey(struct ib_device *, u8 port, u16 index, u16 *pkey);
|
||||
|
||||
struct ib_ucontext *qedr_alloc_ucontext(struct ib_device *, struct ib_udata *);
|
||||
int qedr_dealloc_ucontext(struct ib_ucontext *);
|
||||
|
||||
int qedr_mmap(struct ib_ucontext *, struct vm_area_struct *vma);
|
||||
int qedr_del_gid(struct ib_device *device, u8 port_num,
|
||||
unsigned int index, void **context);
|
||||
int qedr_add_gid(struct ib_device *device, u8 port_num,
|
||||
unsigned int index, const union ib_gid *gid,
|
||||
const struct ib_gid_attr *attr, void **context);
|
||||
struct ib_pd *qedr_alloc_pd(struct ib_device *,
|
||||
struct ib_ucontext *, struct ib_udata *);
|
||||
int qedr_dealloc_pd(struct ib_pd *pd);
|
||||
|
||||
struct ib_cq *qedr_create_cq(struct ib_device *ibdev,
|
||||
const struct ib_cq_init_attr *attr,
|
||||
struct ib_ucontext *ib_ctx,
|
||||
struct ib_udata *udata);
|
||||
int qedr_resize_cq(struct ib_cq *, int cqe, struct ib_udata *);
|
||||
int qedr_destroy_cq(struct ib_cq *);
|
||||
int qedr_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
|
||||
struct ib_qp *qedr_create_qp(struct ib_pd *, struct ib_qp_init_attr *attrs,
|
||||
struct ib_udata *);
|
||||
int qedr_modify_qp(struct ib_qp *, struct ib_qp_attr *attr,
|
||||
int attr_mask, struct ib_udata *udata);
|
||||
int qedr_query_qp(struct ib_qp *, struct ib_qp_attr *qp_attr,
|
||||
int qp_attr_mask, struct ib_qp_init_attr *);
|
||||
int qedr_destroy_qp(struct ib_qp *ibqp);
|
||||
|
||||
struct ib_ah *qedr_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr);
|
||||
int qedr_destroy_ah(struct ib_ah *ibah);
|
||||
|
||||
int qedr_dereg_mr(struct ib_mr *);
|
||||
struct ib_mr *qedr_get_dma_mr(struct ib_pd *, int acc);
|
||||
|
||||
struct ib_mr *qedr_reg_user_mr(struct ib_pd *, u64 start, u64 length,
|
||||
u64 virt, int acc, struct ib_udata *);
|
||||
|
||||
int qedr_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
|
||||
int sg_nents, unsigned int *sg_offset);
|
||||
|
||||
struct ib_mr *qedr_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
|
||||
u32 max_num_sg);
|
||||
int qedr_poll_cq(struct ib_cq *, int num_entries, struct ib_wc *wc);
|
||||
int qedr_post_send(struct ib_qp *, struct ib_send_wr *,
|
||||
struct ib_send_wr **bad_wr);
|
||||
int qedr_post_recv(struct ib_qp *, struct ib_recv_wr *,
|
||||
struct ib_recv_wr **bad_wr);
|
||||
int qedr_process_mad(struct ib_device *ibdev, int process_mad_flags,
|
||||
u8 port_num, const struct ib_wc *in_wc,
|
||||
const struct ib_grh *in_grh,
|
||||
const struct ib_mad_hdr *in_mad,
|
||||
size_t in_mad_size, struct ib_mad_hdr *out_mad,
|
||||
size_t *out_mad_size, u16 *out_mad_pkey_index);
|
||||
|
||||
int qedr_port_immutable(struct ib_device *ibdev, u8 port_num,
|
||||
struct ib_port_immutable *immutable);
|
||||
#endif
|
||||
@@ -107,15 +107,4 @@ config QEDE
|
||||
---help---
|
||||
This enables the support for ...
|
||||
|
||||
config INFINIBAND_QEDR
|
||||
tristate "QLogic qede RoCE sources [debug]"
|
||||
depends on QEDE && 64BIT
|
||||
select QED_LL2
|
||||
default n
|
||||
---help---
|
||||
This provides a temporary node that allows the compilation
|
||||
and logical testing of the InfiniBand over Ethernet support
|
||||
for QLogic QED. This would be replaced by the 'real' option
|
||||
once the QEDR driver is added [+relocated].
|
||||
|
||||
endif # NET_VENDOR_QLOGIC
|
||||
|
||||
@@ -612,6 +612,8 @@
|
||||
*/
|
||||
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
|
||||
#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
|
||||
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */
|
||||
#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
|
||||
@@ -619,6 +621,7 @@
|
||||
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
||||
#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
|
||||
#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
|
||||
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
|
||||
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
|
||||
#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef __QEDR_USER_H__
|
||||
#define __QEDR_USER_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define QEDR_ABI_VERSION (8)
|
||||
|
||||
/* user kernel communication data structures. */
|
||||
|
||||
struct qedr_alloc_ucontext_resp {
|
||||
__u64 db_pa;
|
||||
__u32 db_size;
|
||||
|
||||
__u32 max_send_wr;
|
||||
__u32 max_recv_wr;
|
||||
__u32 max_srq_wr;
|
||||
__u32 sges_per_send_wr;
|
||||
__u32 sges_per_recv_wr;
|
||||
__u32 sges_per_srq_wr;
|
||||
__u32 max_cqes;
|
||||
};
|
||||
|
||||
struct qedr_alloc_pd_ureq {
|
||||
__u64 rsvd1;
|
||||
};
|
||||
|
||||
struct qedr_alloc_pd_uresp {
|
||||
__u32 pd_id;
|
||||
};
|
||||
|
||||
struct qedr_create_cq_ureq {
|
||||
__u64 addr;
|
||||
__u64 len;
|
||||
};
|
||||
|
||||
struct qedr_create_cq_uresp {
|
||||
__u32 db_offset;
|
||||
__u16 icid;
|
||||
};
|
||||
|
||||
struct qedr_create_qp_ureq {
|
||||
__u32 qp_handle_hi;
|
||||
__u32 qp_handle_lo;
|
||||
|
||||
/* SQ */
|
||||
/* user space virtual address of SQ buffer */
|
||||
__u64 sq_addr;
|
||||
|
||||
/* length of SQ buffer */
|
||||
__u64 sq_len;
|
||||
|
||||
/* RQ */
|
||||
/* user space virtual address of RQ buffer */
|
||||
__u64 rq_addr;
|
||||
|
||||
/* length of RQ buffer */
|
||||
__u64 rq_len;
|
||||
};
|
||||
|
||||
struct qedr_create_qp_uresp {
|
||||
__u32 qp_id;
|
||||
__u32 atomic_supported;
|
||||
|
||||
/* SQ */
|
||||
__u32 sq_db_offset;
|
||||
__u16 sq_icid;
|
||||
|
||||
/* RQ */
|
||||
__u32 rq_db_offset;
|
||||
__u16 rq_icid;
|
||||
|
||||
__u32 rq_db2_offset;
|
||||
};
|
||||
|
||||
#endif /* __QEDR_USER_H__ */
|
||||
Reference in New Issue
Block a user