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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from James Hogan:
"math-emu:
- Add missing clearing of BLTZALL and BGEZALL emulation counters
- Fix BC1EQZ and BC1NEZ condition handling
- Fix BLEZL and BGTZL identification
BPF:
- Add JIT support for SKF_AD_HATYPE
- Use unsigned access for unsigned SKB fields
- Quit clobbering callee saved registers in JIT code
- Fix multiple problems in JIT skb access helpers
Loongson 3:
- Select MIPS_L1_CACHE_SHIFT_6
Octeon:
- Remove vestiges of CONFIG_CAVIUM_OCTEON_2ND_KERNEL
- Remove unused L2C types and macros.
- Remove unused SLI types and macros.
- Fix compile error when USB is not enabled.
- Octeon: Remove unused PCIERCX types and macros.
- Octeon: Clean up platform code.
SNI:
- Remove recursive include of cpu-feature-overrides.h
Sibyte:
- Export symbol periph_rev to sb1250-mac network driver.
- Fix Kconfig warning.
Generic platform:
- Enable Root FS on NFS in generic_defconfig
SMP-MT:
- Use CPU interrupt controller IPI IRQ domain support
UASM:
- Add support for LHU for uasm.
- Remove needless ISA abstraction
mm:
- Add 48-bit VA space and 4-level page tables for 4K pages.
PCI:
- Add controllers before the specified head
irqchip driver for MIPS CPU:
- Replace magic 0x100 with IE_SW0
- Prepare for non-legacy IRQ domains
- Introduce IPI IRQ domain support
MAINTAINERS:
- Update email-id of Rahul Bedarkar
NET:
- sb1250-mac: Add missing MODULE_LICENSE()
CPUFREQ:
- Loongson2: drop set_cpus_allowed_ptr()
Misc:
- Disable Werror when W= is set
- Opt into HAVE_COPY_THREAD_TLS
- Enable GENERIC_CPU_AUTOPROBE
- Use common outgoing-CPU-notification code
- Remove dead define of ST_OFF
- Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
- Stengthen IPI IRQ domain sanity check
- Remove confusing else statement in __do_page_fault()
- Don't unnecessarily include kmalloc.h into <asm/cache.h>.
- Delete unused definition of SMP_CACHE_SHIFT.
- Delete redundant definition of SMP_CACHE_BYTES"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (39 commits)
MIPS: Sibyte: Fix Kconfig warning.
MIPS: Sibyte: Export symbol periph_rev to sb1250-mac network driver.
NET: sb1250-mac: Add missing MODULE_LICENSE()
MAINTAINERS: Update email-id of Rahul Bedarkar
MIPS: Remove confusing else statement in __do_page_fault()
MIPS: Stengthen IPI IRQ domain sanity check
MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support
irqchip: mips-cpu: Introduce IPI IRQ domain support
irqchip: mips-cpu: Prepare for non-legacy IRQ domains
irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
MIPS: Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
MIPS: generic: Enable Root FS on NFS in generic_defconfig
MIPS: mach-rm: Remove recursive include of cpu-feature-overrides.h
MIPS: Opt into HAVE_COPY_THREAD_TLS
CPUFREQ: Loongson2: drop set_cpus_allowed_ptr()
MIPS: uasm: Remove needless ISA abstraction
MIPS: Remove dead define of ST_OFF
MIPS: Use common outgoing-CPU-notification code
MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling
MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs counters
...
This commit is contained in:
Linus Torvalds
+1
-1
@@ -7923,7 +7923,7 @@ L: linux-man@vger.kernel.org
|
||||
S: Maintained
|
||||
|
||||
MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
|
||||
M: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
|
||||
M: Rahul Bedarkar <rahulbedarkar89@gmail.com>
|
||||
L: linux-mips@linux-mips.org
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||||
S: Maintained
|
||||
F: arch/mips/boot/dts/img/pistachio_marduk.dts
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
# Fail on warnings - also for files referenced in subdirs
|
||||
# -Werror can be disabled for specific files using:
|
||||
# CFLAGS_<file.o> := -Wno-error
|
||||
ifeq ($(W),)
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subdir-ccflags-y := -Werror
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||||
endif
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||||
|
||||
# platform specific definitions
|
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include arch/mips/Kbuild.platforms
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|
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+11
-13
@@ -46,6 +46,7 @@ config MIPS
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select ARCH_DISCARD_MEMBLOCK
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select GENERIC_SMP_IDLE_THREAD
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select BUILDTIME_EXTABLE_SORT
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||||
select GENERIC_CPU_AUTOPROBE
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select GENERIC_CLOCKEVENTS
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select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
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select GENERIC_CMOS_UPDATE
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@@ -68,6 +69,7 @@ config MIPS
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select HANDLE_DOMAIN_IRQ
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select HAVE_EXIT_THREAD
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_COPY_THREAD_TLS
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||||
menu "Machine selection"
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|
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@@ -1039,14 +1041,6 @@ config RWSEM_GENERIC_SPINLOCK
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config RWSEM_XCHGADD_ALGORITHM
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bool
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config ARCH_HAS_ILOG2_U32
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bool
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default n
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config ARCH_HAS_ILOG2_U64
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bool
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default n
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config GENERIC_HWEIGHT
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bool
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default y
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@@ -1372,6 +1366,7 @@ config CPU_LOONGSON3
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select WEAK_ORDERING
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select WEAK_REORDERING_BEYOND_LLSC
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select MIPS_PGD_C0_CONTEXT
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select MIPS_L1_CACHE_SHIFT_6
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select GPIOLIB
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help
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The Loongson 3 processor implements the MIPS64R2 instruction
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@@ -2120,10 +2115,13 @@ config MIPS_VA_BITS_48
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bool "48 bits virtual memory"
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depends on 64BIT
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help
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Support a maximum at least 48 bits of application virtual memory.
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Default is 40 bits or less, depending on the CPU.
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This option result in a small memory overhead for page tables.
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This option is only supported with 16k and 64k page sizes.
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Support a maximum at least 48 bits of application virtual
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memory. Default is 40 bits or less, depending on the CPU.
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||||
For page sizes 16k and above, this option results in a small
|
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memory overhead for page tables. For 4k page size, a fourth
|
||||
level of page tables is added which imposes both a memory
|
||||
overhead as well as slower TLB fault handling.
|
||||
|
||||
If unsure, say N.
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||||
|
||||
choice
|
||||
@@ -2133,7 +2131,6 @@ choice
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config PAGE_SIZE_4KB
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bool "4kB"
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depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
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depends on !MIPS_VA_BITS_48
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help
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This option select the standard 4kB Linux page size. On some
|
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R3000-family processors this is the only available page size. Using
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@@ -2982,6 +2979,7 @@ config HAVE_LATENCYTOP_SUPPORT
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config PGTABLE_LEVELS
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int
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default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
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default 3 if 64BIT && !PAGE_SIZE_64KB
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default 2
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@@ -82,7 +82,7 @@ config CMDLINE_OVERRIDE
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config SB1XXX_CORELIS
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bool "Corelis Debugger"
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depends on SIBYTE_SB1xxx_SOC
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select DEBUG_INFO
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select DEBUG_INFO if !COMPILE_TEST
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help
|
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Select compile flags that produce code that can be processed by the
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Corelis mksym utility and UDB Emulator.
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@@ -25,15 +25,6 @@ endif # CPU_CAVIUM_OCTEON
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if CAVIUM_OCTEON_SOC
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config CAVIUM_OCTEON_2ND_KERNEL
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bool "Build the kernel to be used as a 2nd kernel on the same chip"
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default "n"
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help
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This option configures this kernel to be linked at a different
|
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address and use the 2nd uart for output. This allows a kernel built
|
||||
with this option to be run at the same time as one built without this
|
||||
option.
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||||
|
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config CAVIUM_OCTEON_LOCK_L2
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bool "Lock often used kernel code in the L2"
|
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default "y"
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|
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@@ -4,8 +4,4 @@
|
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platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
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cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \
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-I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
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ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
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||||
load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000
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else
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load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000
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endif
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@@ -4,7 +4,7 @@
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* Contact: support@caviumnetworks.com
|
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* This file is part of the OCTEON SDK
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||||
*
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||||
* Copyright (c) 2003-2010 Cavium Networks
|
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* Copyright (c) 2003-2017 Cavium, Inc.
|
||||
*
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||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
@@ -239,6 +239,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
|
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else {
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uint64_t counter = 0;
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int tad;
|
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|
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for (tad = 0; tad < CVMX_L2C_TADS; tad++)
|
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counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
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return counter;
|
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@@ -249,6 +250,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
|
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else {
|
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uint64_t counter = 0;
|
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int tad;
|
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|
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for (tad = 0; tad < CVMX_L2C_TADS; tad++)
|
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counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
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return counter;
|
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@@ -259,6 +261,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
|
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else {
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uint64_t counter = 0;
|
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int tad;
|
||||
|
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for (tad = 0; tad < CVMX_L2C_TADS; tad++)
|
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counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
|
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return counter;
|
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@@ -270,6 +273,7 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
|
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else {
|
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uint64_t counter = 0;
|
||||
int tad;
|
||||
|
||||
for (tad = 0; tad < CVMX_L2C_TADS; tad++)
|
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counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
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return counter;
|
||||
@@ -301,7 +305,7 @@ static void fault_in(uint64_t addr, int len)
|
||||
*/
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||||
CVMX_DCACHE_INVALIDATE;
|
||||
while (len > 0) {
|
||||
ACCESS_ONCE(*ptr);
|
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READ_ONCE(*ptr);
|
||||
len -= CVMX_CACHE_LINE_SIZE;
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ptr += CVMX_CACHE_LINE_SIZE;
|
||||
}
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||||
@@ -375,7 +379,9 @@ int cvmx_l2c_lock_line(uint64_t addr)
|
||||
if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
|
||||
int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
|
||||
uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
|
||||
|
||||
lckbase.s.lck_base = addr_tmp >> 7;
|
||||
|
||||
} else {
|
||||
lckbase.s.lck_base = addr >> 7;
|
||||
}
|
||||
@@ -435,6 +441,7 @@ void cvmx_l2c_flush(void)
|
||||
/* These may look like constants, but they aren't... */
|
||||
int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
|
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int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
|
||||
|
||||
for (set = 0; set < n_set; set++) {
|
||||
for (assoc = 0; assoc < n_assoc; assoc++) {
|
||||
address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
|
||||
@@ -519,89 +526,49 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
|
||||
union __cvmx_l2c_tag {
|
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uint64_t u64;
|
||||
struct cvmx_l2c_tag_cn50xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
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uint64_t reserved:40;
|
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uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
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uint64_t addr:20; /* Phys mem addr (33..14) */
|
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#else
|
||||
uint64_t addr:20; /* Phys mem addr (33..14) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
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uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:40;
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#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved:40,
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__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
|
||||
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
|
||||
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
|
||||
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
|
||||
__BITFIELD_FIELD(uint64_t addr:20, /* Phys addr (33..14) */
|
||||
;))))))
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||||
} cn50xx;
|
||||
struct cvmx_l2c_tag_cn30xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
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uint64_t reserved:41;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:19; /* Phys mem addr (33..15) */
|
||||
#else
|
||||
uint64_t addr:19; /* Phys mem addr (33..15) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:41;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved:41,
|
||||
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
|
||||
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
|
||||
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
|
||||
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
|
||||
__BITFIELD_FIELD(uint64_t addr:19, /* Phys addr (33..15) */
|
||||
;))))))
|
||||
} cn30xx;
|
||||
struct cvmx_l2c_tag_cn31xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:42;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:18; /* Phys mem addr (33..16) */
|
||||
#else
|
||||
uint64_t addr:18; /* Phys mem addr (33..16) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:42;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved:42,
|
||||
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
|
||||
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
|
||||
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
|
||||
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
|
||||
__BITFIELD_FIELD(uint64_t addr:18, /* Phys addr (33..16) */
|
||||
;))))))
|
||||
} cn31xx;
|
||||
struct cvmx_l2c_tag_cn38xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:43;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:17; /* Phys mem addr (33..17) */
|
||||
#else
|
||||
uint64_t addr:17; /* Phys mem addr (33..17) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:43;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved:43,
|
||||
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
|
||||
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
|
||||
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
|
||||
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
|
||||
__BITFIELD_FIELD(uint64_t addr:17, /* Phys addr (33..17) */
|
||||
;))))))
|
||||
} cn38xx;
|
||||
struct cvmx_l2c_tag_cn58xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:44;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:16; /* Phys mem addr (33..18) */
|
||||
#else
|
||||
uint64_t addr:16; /* Phys mem addr (33..18) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:44;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved:44,
|
||||
__BITFIELD_FIELD(uint64_t V:1, /* Line valid */
|
||||
__BITFIELD_FIELD(uint64_t D:1, /* Line dirty */
|
||||
__BITFIELD_FIELD(uint64_t L:1, /* Line locked */
|
||||
__BITFIELD_FIELD(uint64_t U:1, /* Use, LRU eviction */
|
||||
__BITFIELD_FIELD(uint64_t addr:16, /* Phys addr (33..18) */
|
||||
;))))))
|
||||
} cn58xx;
|
||||
struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
|
||||
struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
|
||||
@@ -629,8 +596,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
|
||||
union __cvmx_l2c_tag tag_val;
|
||||
uint64_t dbg_addr = CVMX_L2C_DBG;
|
||||
unsigned long flags;
|
||||
|
||||
union cvmx_l2c_dbg debug_val;
|
||||
|
||||
debug_val.u64 = 0;
|
||||
/*
|
||||
* For low core count parts, the core number is always small
|
||||
@@ -683,8 +650,8 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
|
||||
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
|
||||
{
|
||||
union cvmx_l2c_tag tag;
|
||||
tag.u64 = 0;
|
||||
|
||||
tag.u64 = 0;
|
||||
if ((int)association >= cvmx_l2c_get_num_assoc()) {
|
||||
cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
|
||||
return tag;
|
||||
@@ -767,10 +734,12 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr)
|
||||
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
|
||||
union cvmx_l2c_ctl l2c_ctl;
|
||||
|
||||
l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
|
||||
indxalias = !l2c_ctl.s.disidxalias;
|
||||
} else {
|
||||
union cvmx_l2c_cfg l2c_cfg;
|
||||
|
||||
l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
|
||||
indxalias = l2c_cfg.s.idxalias;
|
||||
}
|
||||
@@ -778,6 +747,7 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr)
|
||||
if (indxalias) {
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
|
||||
uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
|
||||
|
||||
idx ^= idx / cvmx_l2c_get_num_sets();
|
||||
idx ^= a_14_12;
|
||||
} else {
|
||||
@@ -801,6 +771,7 @@ int cvmx_l2c_get_cache_size_bytes(void)
|
||||
int cvmx_l2c_get_set_bits(void)
|
||||
{
|
||||
int l2_set_bits;
|
||||
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
|
||||
l2_set_bits = 11; /* 2048 sets */
|
||||
else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
|
||||
@@ -828,6 +799,7 @@ int cvmx_l2c_get_num_sets(void)
|
||||
int cvmx_l2c_get_num_assoc(void)
|
||||
{
|
||||
int l2_assoc;
|
||||
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN52XX) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN58XX) ||
|
||||
@@ -869,16 +841,17 @@ int cvmx_l2c_get_num_assoc(void)
|
||||
else if (mio_fus_dat3.s.l2c_crip == 1)
|
||||
l2_assoc = 12;
|
||||
} else {
|
||||
union cvmx_l2d_fus3 val;
|
||||
val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
|
||||
uint64_t l2d_fus3;
|
||||
|
||||
l2d_fus3 = cvmx_read_csr(CVMX_L2D_FUS3);
|
||||
/*
|
||||
* Using shifts here, as bit position names are
|
||||
* different for each model but they all mean the
|
||||
* same.
|
||||
*/
|
||||
if ((val.u64 >> 35) & 0x1)
|
||||
if ((l2d_fus3 >> 35) & 0x1)
|
||||
l2_assoc = l2_assoc >> 2;
|
||||
else if ((val.u64 >> 34) & 0x1)
|
||||
else if ((l2d_fus3 >> 34) & 0x1)
|
||||
l2_assoc = l2_assoc >> 1;
|
||||
}
|
||||
return l2_assoc;
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2010 Cavium Networks
|
||||
* Copyright (c) 2003-2017 Cavium, Inc.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
@@ -63,16 +63,15 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
char pass[4];
|
||||
int clock_mhz;
|
||||
const char *suffix;
|
||||
union cvmx_l2d_fus3 fus3;
|
||||
int num_cores;
|
||||
union cvmx_mio_fus_dat2 fus_dat2;
|
||||
union cvmx_mio_fus_dat3 fus_dat3;
|
||||
char fuse_model[10];
|
||||
uint32_t fuse_data = 0;
|
||||
uint64_t l2d_fus3 = 0;
|
||||
|
||||
fus3.u64 = 0;
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
|
||||
fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
|
||||
l2d_fus3 = (cvmx_read_csr(CVMX_L2D_FUS3) >> 34) & 0x3;
|
||||
fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
|
||||
fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
|
||||
num_cores = cvmx_octeon_num_cores();
|
||||
@@ -192,7 +191,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
/* Now figure out the family, the first two digits */
|
||||
switch ((chip_id >> 8) & 0xff) {
|
||||
case 0: /* CN38XX, CN37XX or CN36XX */
|
||||
if (fus3.cn38xx.crip_512k) {
|
||||
if (l2d_fus3) {
|
||||
/*
|
||||
* For some unknown reason, the 16 core one is
|
||||
* called 37 instead of 36.
|
||||
@@ -223,7 +222,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
}
|
||||
break;
|
||||
case 1: /* CN31XX or CN3020 */
|
||||
if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
|
||||
if ((chip_id & 0x10) || l2d_fus3)
|
||||
family = "30";
|
||||
else
|
||||
family = "31";
|
||||
@@ -246,7 +245,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
case 2: /* CN3010 or CN3005 */
|
||||
family = "30";
|
||||
/* A chip with half cache is an 05 */
|
||||
if (fus3.cn30xx.crip_64k)
|
||||
if (l2d_fus3)
|
||||
core_model = "05";
|
||||
/*
|
||||
* This series of chips didn't follow the standard
|
||||
@@ -267,7 +266,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
case 3: /* CN58XX */
|
||||
family = "58";
|
||||
/* Special case. 4 core, half cache (CP with half cache) */
|
||||
if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
|
||||
if ((num_cores == 4) && l2d_fus3 && !strncmp(suffix, "CP", 2))
|
||||
core_model = "29";
|
||||
|
||||
/* Pass 1 uses different encodings for pass numbers */
|
||||
@@ -290,7 +289,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
break;
|
||||
case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
|
||||
if (fus_dat2.cn56xx.raid_en) {
|
||||
if (fus3.cn56xx.crip_1024k)
|
||||
if (l2d_fus3)
|
||||
family = "55";
|
||||
else
|
||||
family = "57";
|
||||
@@ -309,7 +308,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
if (fus_dat3.cn56xx.bar2_en)
|
||||
suffix = "NSPB2";
|
||||
}
|
||||
if (fus3.cn56xx.crip_1024k)
|
||||
if (l2d_fus3)
|
||||
family = "54";
|
||||
else
|
||||
family = "56";
|
||||
@@ -319,7 +318,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
|
||||
family = "50";
|
||||
break;
|
||||
case 7: /* CN52XX */
|
||||
if (fus3.cn52xx.crip_256k)
|
||||
if (l2d_fus3)
|
||||
family = "51";
|
||||
else
|
||||
family = "52";
|
||||
|
||||
@@ -3,71 +3,27 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2004-2016 Cavium Networks
|
||||
* Copyright (C) 2004-2017 Cavium, Inc.
|
||||
* Copyright (C) 2008 Wind River Systems
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/usb/ehci_def.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-helper-board.h>
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
#include <linux/usb/ehci_def.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
#include <asm/octeon/cvmx-uctlx-defs.h>
|
||||
|
||||
#define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
|
||||
#define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
|
||||
|
||||
/* Octeon Random Number Generator. */
|
||||
static int __init octeon_rng_device_init(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
int ret = 0;
|
||||
|
||||
struct resource rng_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
|
||||
.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = cvmx_build_io_address(8, 0),
|
||||
.end = cvmx_build_io_address(8, 0) + 0x7
|
||||
}
|
||||
};
|
||||
|
||||
pd = platform_device_alloc("octeon_rng", -1);
|
||||
if (!pd) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = platform_device_add_resources(pd, rng_resources,
|
||||
ARRAY_SIZE(rng_resources));
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
return ret;
|
||||
fail:
|
||||
platform_device_put(pd);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
device_initcall(octeon_rng_device_init);
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
|
||||
static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
|
||||
|
||||
static int octeon2_usb_clock_start_cnt;
|
||||
@@ -440,8 +396,49 @@ device_initcall(octeon_ohci_device_init);
|
||||
|
||||
#endif /* CONFIG_USB */
|
||||
|
||||
/* Octeon Random Number Generator. */
|
||||
static int __init octeon_rng_device_init(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
int ret = 0;
|
||||
|
||||
static struct of_device_id __initdata octeon_ids[] = {
|
||||
struct resource rng_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
|
||||
.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = cvmx_build_io_address(8, 0),
|
||||
.end = cvmx_build_io_address(8, 0) + 0x7
|
||||
}
|
||||
};
|
||||
|
||||
pd = platform_device_alloc("octeon_rng", -1);
|
||||
if (!pd) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = platform_device_add_resources(pd, rng_resources,
|
||||
ARRAY_SIZE(rng_resources));
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
return ret;
|
||||
fail:
|
||||
platform_device_put(pd);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
device_initcall(octeon_rng_device_init);
|
||||
|
||||
const struct of_device_id octeon_ids[] __initconst = {
|
||||
{ .compatible = "simple-bus", },
|
||||
{ .compatible = "cavium,octeon-6335-uctl", },
|
||||
{ .compatible = "cavium,octeon-5750-usbn", },
|
||||
@@ -481,6 +478,7 @@ static void __init octeon_fdt_set_phy(int eth, int phy_addr)
|
||||
alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
|
||||
if (alt_phy_handle) {
|
||||
u32 alt_phandle = be32_to_cpup(alt_phy_handle);
|
||||
|
||||
alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
|
||||
} else {
|
||||
alt_phy = -1;
|
||||
@@ -579,6 +577,7 @@ static void __init octeon_fdt_rm_ethernet(int node)
|
||||
if (phy_handle) {
|
||||
u32 ph = be32_to_cpup(phy_handle);
|
||||
int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
|
||||
|
||||
if (p >= 0)
|
||||
fdt_nop_node(initial_boot_params, p);
|
||||
}
|
||||
@@ -728,6 +727,7 @@ int __init octeon_prune_device_tree(void)
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
int mgmt;
|
||||
|
||||
snprintf(name_buffer, sizeof(name_buffer),
|
||||
"mix%d", i);
|
||||
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
||||
@@ -743,6 +743,7 @@ int __init octeon_prune_device_tree(void)
|
||||
name_buffer);
|
||||
} else {
|
||||
int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
|
||||
|
||||
octeon_fdt_set_phy(mgmt, phy_addr);
|
||||
}
|
||||
}
|
||||
@@ -751,6 +752,7 @@ int __init octeon_prune_device_tree(void)
|
||||
pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
|
||||
if (pip_path) {
|
||||
int pip = fdt_path_offset(initial_boot_params, pip_path);
|
||||
|
||||
if (pip >= 0)
|
||||
for (i = 0; i <= 4; i++)
|
||||
octeon_fdt_pip_iface(pip, i);
|
||||
@@ -767,6 +769,7 @@ int __init octeon_prune_device_tree(void)
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
int i2c;
|
||||
|
||||
snprintf(name_buffer, sizeof(name_buffer),
|
||||
"twsi%d", i);
|
||||
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
||||
@@ -797,11 +800,11 @@ int __init octeon_prune_device_tree(void)
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
int i2c;
|
||||
|
||||
snprintf(name_buffer, sizeof(name_buffer),
|
||||
"smi%d", i);
|
||||
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
||||
name_buffer, NULL);
|
||||
|
||||
if (alias_prop) {
|
||||
i2c = fdt_path_offset(initial_boot_params, alias_prop);
|
||||
if (i2c < 0)
|
||||
@@ -824,6 +827,7 @@ int __init octeon_prune_device_tree(void)
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
int uart;
|
||||
|
||||
snprintf(name_buffer, sizeof(name_buffer),
|
||||
"uart%d", i);
|
||||
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
||||
@@ -863,6 +867,7 @@ int __init octeon_prune_device_tree(void)
|
||||
int len;
|
||||
|
||||
int cf = fdt_path_offset(initial_boot_params, alias_prop);
|
||||
|
||||
base_ptr = 0;
|
||||
if (octeon_bootinfo->major_version == 1
|
||||
&& octeon_bootinfo->minor_version >= 1) {
|
||||
@@ -912,6 +917,7 @@ int __init octeon_prune_device_tree(void)
|
||||
fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
|
||||
if (!is_16bit) {
|
||||
__be32 width = cpu_to_be32(8);
|
||||
|
||||
fdt_setprop_inplace(initial_boot_params, cf,
|
||||
"cavium,bus-width", &width, sizeof(width));
|
||||
}
|
||||
@@ -1004,6 +1010,7 @@ end_led:
|
||||
;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
/* OHCI/UHCI USB */
|
||||
alias_prop = fdt_getprop(initial_boot_params, aliases,
|
||||
"uctl", NULL);
|
||||
@@ -1036,6 +1043,7 @@ end_led:
|
||||
} else {
|
||||
__be32 new_f[1];
|
||||
enum cvmx_helper_board_usb_clock_types c;
|
||||
|
||||
c = __cvmx_helper_board_usb_get_clock_type();
|
||||
switch (c) {
|
||||
case USB_CLOCK_TYPE_REF_48:
|
||||
@@ -1052,6 +1060,7 @@ end_led:
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -374,14 +374,8 @@ void octeon_write_lcd(const char *s)
|
||||
*/
|
||||
int octeon_get_boot_uart(void)
|
||||
{
|
||||
int uart;
|
||||
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
|
||||
uart = 1;
|
||||
#else
|
||||
uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
|
||||
return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
|
||||
1 : 0;
|
||||
#endif
|
||||
return uart;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -901,14 +895,10 @@ void __init prom_init(void)
|
||||
}
|
||||
|
||||
if (strstr(arcs_cmdline, "console=") == NULL) {
|
||||
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
|
||||
strcat(arcs_cmdline, " console=ttyS0,115200");
|
||||
#else
|
||||
if (octeon_uart == 1)
|
||||
strcat(arcs_cmdline, " console=ttyS1,115200");
|
||||
else
|
||||
strcat(arcs_cmdline, " console=ttyS0,115200");
|
||||
#endif
|
||||
}
|
||||
|
||||
mips_hpt_frequency = octeon_get_clock_rate();
|
||||
|
||||
@@ -36,6 +36,8 @@ CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
@@ -80,6 +82,7 @@ CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_NFS_V4_2=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_INFO_REDUCED=y
|
||||
|
||||
@@ -9,14 +9,9 @@
|
||||
#ifndef _ASM_CACHE_H
|
||||
#define _ASM_CACHE_H
|
||||
|
||||
#include <kmalloc.h>
|
||||
|
||||
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
|
||||
#define SMP_CACHE_BYTES L1_CACHE_BYTES
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
#endif /* _ASM_CACHE_H */
|
||||
|
||||
@@ -12,10 +12,9 @@
|
||||
#ifndef __ASM_CPU_INFO_H
|
||||
#define __ASM_CPU_INFO_H
|
||||
|
||||
#include <linux/cache.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
|
||||
/*
|
||||
* Descriptor for a cache
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* CPU feature definitions for module loading, used by
|
||||
* module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_CPUFEATURE_H
|
||||
#define __ASM_CPUFEATURE_H
|
||||
|
||||
#include <uapi/asm/hwcap.h>
|
||||
#include <asm/elf.h>
|
||||
|
||||
#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
|
||||
|
||||
#define cpu_feature(x) ilog2(HWCAP_ ## x)
|
||||
|
||||
static inline bool cpu_have_feature(unsigned int num)
|
||||
{
|
||||
return elf_hwcap & (1UL << num);
|
||||
}
|
||||
|
||||
#endif /* __ASM_CPUFEATURE_H */
|
||||
@@ -10,8 +10,6 @@
|
||||
#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#include <cpu-feature-overrides.h>
|
||||
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_4k_cache 1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,7 +4,7 @@
|
||||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2010 Cavium Networks
|
||||
* Copyright (c) 2003-2017 Cavium, Inc.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
@@ -33,48 +33,39 @@
|
||||
#ifndef __CVMX_L2C_H__
|
||||
#define __CVMX_L2C_H__
|
||||
|
||||
#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
|
||||
#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
|
||||
#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
|
||||
#include <uapi/asm/bitfield.h>
|
||||
|
||||
#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro */
|
||||
#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro */
|
||||
#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro */
|
||||
|
||||
#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
|
||||
/* Based on 128 byte cache line size */
|
||||
#define CVMX_L2C_IDX_ADDR_SHIFT 7
|
||||
#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
|
||||
|
||||
/* Defines for index aliasing computations */
|
||||
#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
|
||||
#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + \
|
||||
cvmx_l2c_get_set_bits())
|
||||
#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
|
||||
#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
|
||||
|
||||
/* Defines for Virtualizations, valid only from Octeon II onwards. */
|
||||
#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
|
||||
#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
|
||||
|
||||
union cvmx_l2c_tag {
|
||||
uint64_t u64;
|
||||
struct {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:28;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:32; /* Phys mem (not all bits valid) */
|
||||
#else
|
||||
uint64_t addr:32; /* Phys mem (not all bits valid) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:28;
|
||||
#endif
|
||||
} s;
|
||||
};
|
||||
#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
|
||||
|
||||
/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
|
||||
#define CVMX_L2C_TADS 1
|
||||
|
||||
/* L2C Performance Counter events. */
|
||||
union cvmx_l2c_tag {
|
||||
uint64_t u64;
|
||||
struct {
|
||||
__BITFIELD_FIELD(uint64_t reserved:28,
|
||||
__BITFIELD_FIELD(uint64_t V:1,
|
||||
__BITFIELD_FIELD(uint64_t D:1,
|
||||
__BITFIELD_FIELD(uint64_t L:1,
|
||||
__BITFIELD_FIELD(uint64_t U:1,
|
||||
__BITFIELD_FIELD(uint64_t addr:32,
|
||||
;))))))
|
||||
} s;
|
||||
};
|
||||
|
||||
/* L2C Performance Counter events. */
|
||||
enum cvmx_l2c_event {
|
||||
CVMX_L2C_EVENT_CYCLES = 0,
|
||||
CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
|
||||
@@ -175,7 +166,8 @@ enum cvmx_l2c_tad_event {
|
||||
*
|
||||
* @note The routine does not clear the counter.
|
||||
*/
|
||||
void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
|
||||
void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
|
||||
uint32_t clear_on_read);
|
||||
|
||||
/**
|
||||
* Read the given L2 Cache performance counter. The counter must be configured
|
||||
@@ -307,8 +299,11 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
|
||||
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
|
||||
|
||||
/* Wrapper providing a deprecated old function name */
|
||||
static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
|
||||
static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
|
||||
static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
|
||||
uint32_t index)
|
||||
__attribute__((deprecated));
|
||||
static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
|
||||
uint32_t index)
|
||||
{
|
||||
return cvmx_l2c_get_tag(association, index);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,7 +4,7 @@
|
||||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2012 Cavium Networks
|
||||
* Copyright (c) 2003-2017 Cavium, Inc.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
@@ -28,210 +28,116 @@
|
||||
#ifndef __CVMX_L2T_DEFS_H__
|
||||
#define __CVMX_L2T_DEFS_H__
|
||||
|
||||
#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
|
||||
#include <uapi/asm/bitfield.h>
|
||||
|
||||
#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
|
||||
|
||||
|
||||
union cvmx_l2t_err {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2t_err_s {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_29_63:35;
|
||||
uint64_t fadru:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t fset:3;
|
||||
uint64_t fadr:10;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:10;
|
||||
uint64_t fset:3;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t fadru:1;
|
||||
uint64_t reserved_29_63:35;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_29_63:35,
|
||||
__BITFIELD_FIELD(uint64_t fadru:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:3,
|
||||
__BITFIELD_FIELD(uint64_t fadr:10,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;))))))))))))))
|
||||
} s;
|
||||
struct cvmx_l2t_err_cn30xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t fset:2;
|
||||
uint64_t reserved_19_20:2;
|
||||
uint64_t fadr:8;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:8;
|
||||
uint64_t reserved_19_20:2;
|
||||
uint64_t fset:2;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t reserved_28_63:36;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t reserved_23_23:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:2,
|
||||
__BITFIELD_FIELD(uint64_t reserved_19_20:2,
|
||||
__BITFIELD_FIELD(uint64_t fadr:8,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;)))))))))))))))
|
||||
} cn30xx;
|
||||
struct cvmx_l2t_err_cn31xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t fset:2;
|
||||
uint64_t reserved_20_20:1;
|
||||
uint64_t fadr:9;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:9;
|
||||
uint64_t reserved_20_20:1;
|
||||
uint64_t fset:2;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t reserved_28_63:36;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t reserved_23_23:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:2,
|
||||
__BITFIELD_FIELD(uint64_t reserved_20_20:1,
|
||||
__BITFIELD_FIELD(uint64_t fadr:9,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;)))))))))))))))
|
||||
} cn31xx;
|
||||
struct cvmx_l2t_err_cn38xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t fset:3;
|
||||
uint64_t fadr:10;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:10;
|
||||
uint64_t fset:3;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t reserved_28_63:36;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:3,
|
||||
__BITFIELD_FIELD(uint64_t fadr:10,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;)))))))))))))
|
||||
} cn38xx;
|
||||
struct cvmx_l2t_err_cn38xx cn38xxp2;
|
||||
struct cvmx_l2t_err_cn50xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t fset:3;
|
||||
uint64_t reserved_18_20:3;
|
||||
uint64_t fadr:7;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:7;
|
||||
uint64_t reserved_18_20:3;
|
||||
uint64_t fset:3;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t reserved_28_63:36;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:3,
|
||||
__BITFIELD_FIELD(uint64_t reserved_18_20:3,
|
||||
__BITFIELD_FIELD(uint64_t fadr:7,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;))))))))))))))
|
||||
} cn50xx;
|
||||
struct cvmx_l2t_err_cn52xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t fset:3;
|
||||
uint64_t reserved_20_20:1;
|
||||
uint64_t fadr:9;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ecc_ena:1;
|
||||
#else
|
||||
uint64_t ecc_ena:1;
|
||||
uint64_t sec_intena:1;
|
||||
uint64_t ded_intena:1;
|
||||
uint64_t sec_err:1;
|
||||
uint64_t ded_err:1;
|
||||
uint64_t fsyn:6;
|
||||
uint64_t fadr:9;
|
||||
uint64_t reserved_20_20:1;
|
||||
uint64_t fset:3;
|
||||
uint64_t lckerr:1;
|
||||
uint64_t lck_intena:1;
|
||||
uint64_t lckerr2:1;
|
||||
uint64_t lck_intena2:1;
|
||||
uint64_t reserved_28_63:36;
|
||||
#endif
|
||||
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena2:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr2:1,
|
||||
__BITFIELD_FIELD(uint64_t lck_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t lckerr:1,
|
||||
__BITFIELD_FIELD(uint64_t fset:3,
|
||||
__BITFIELD_FIELD(uint64_t reserved_20_20:1,
|
||||
__BITFIELD_FIELD(uint64_t fadr:9,
|
||||
__BITFIELD_FIELD(uint64_t fsyn:6,
|
||||
__BITFIELD_FIELD(uint64_t ded_err:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_err:1,
|
||||
__BITFIELD_FIELD(uint64_t ded_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t sec_intena:1,
|
||||
__BITFIELD_FIELD(uint64_t ecc_ena:1,
|
||||
;))))))))))))))
|
||||
} cn52xx;
|
||||
struct cvmx_l2t_err_cn52xx cn52xxp1;
|
||||
struct cvmx_l2t_err_s cn56xx;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user