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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6

Browse Source
This commit is contained in:
David S. Miller
2009-02-14 23:06:44 -08:00
parent f3a7c66b5c 6d08b9b9c6
commit ac178ef0ae
108 changed files with 19394 additions and 16983 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/wireless/ath5k/ath5k.h
+24 -49
View File
@@ -165,9 +165,6 @@
#define AR5K_INI_VAL_XR 0
#define AR5K_INI_VAL_MAX 5
#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
/* Used for BSSID etc manipulation */
#define AR5K_LOW_ID(_a)( \
(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
@@ -225,6 +222,7 @@
#endif
/* Initial values */
#define AR5K_INIT_CYCRSSI_THR1 2
#define AR5K_INIT_TX_LATENCY 502
#define AR5K_INIT_USEC 39
#define AR5K_INIT_USEC_TURBO 79
@@ -316,7 +314,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_AR5424 0x90 /* Condor */
#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
#define AR5K_SREV_AR5414 0xa0 /* Eagle */
#define AR5K_SREV_AR2415 0xb0 /* Cobra */
#define AR5K_SREV_AR2415 0xb0 /* Talon */
#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
#define AR5K_SREV_AR5418 0xca /* PCI-E */
#define AR5K_SREV_AR2425 0xe0 /* Swan */
@@ -334,7 +332,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_RAD_2112B 0x46
#define AR5K_SREV_RAD_2413 0x50
#define AR5K_SREV_RAD_5413 0x60
#define AR5K_SREV_RAD_2316 0x70
#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
#define AR5K_SREV_RAD_2317 0x80
#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
#define AR5K_SREV_RAD_2425 0xa2
@@ -342,7 +340,8 @@ struct ath5k_srev_name {
#define AR5K_SREV_PHY_5211 0x30
#define AR5K_SREV_PHY_5212 0x41
#define AR5K_SREV_PHY_2112B 0x43
#define AR5K_SREV_PHY_5212A 0x42
#define AR5K_SREV_PHY_5212B 0x43
#define AR5K_SREV_PHY_2413 0x45
#define AR5K_SREV_PHY_5413 0x61
#define AR5K_SREV_PHY_2425 0x70
@@ -649,49 +648,21 @@ struct ath5k_beacon_state {
enum ath5k_rfgain {
AR5K_RFGAIN_INACTIVE = 0,
AR5K_RFGAIN_ACTIVE,
AR5K_RFGAIN_READ_REQUESTED,
AR5K_RFGAIN_NEED_CHANGE,
};
#define AR5K_GAIN_CRN_FIX_BITS_5111 4
#define AR5K_GAIN_CRN_FIX_BITS_5112 7
#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
#define AR5K_GAIN_CCK_PROBE_CORR 5
#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
#define AR5K_GAIN_STEP_COUNT 10
#define AR5K_GAIN_PARAM_TX_CLIP 0
#define AR5K_GAIN_PARAM_PD_90 1
#define AR5K_GAIN_PARAM_PD_84 2
#define AR5K_GAIN_PARAM_GAIN_SEL 3
#define AR5K_GAIN_PARAM_MIX_ORN 0
#define AR5K_GAIN_PARAM_PD_138 1
#define AR5K_GAIN_PARAM_PD_137 2
#define AR5K_GAIN_PARAM_PD_136 3
#define AR5K_GAIN_PARAM_PD_132 4
#define AR5K_GAIN_PARAM_PD_131 5
#define AR5K_GAIN_PARAM_PD_130 6
#define AR5K_GAIN_CHECK_ADJUST(_g) \
((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
struct ath5k_gain_opt_step {
s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
s32 gos_gain;
};
struct ath5k_gain {
u32 g_step_idx;
u32 g_current;
u32 g_target;
u32 g_low;
u32 g_high;
u32 g_f_corr;
u32 g_active;
const struct ath5k_gain_opt_step *g_step;
u8 g_step_idx;
u8 g_current;
u8 g_target;
u8 g_low;
u8 g_high;
u8 g_f_corr;
u8 g_state;
};
/********************\
COMMON DEFINITIONS
\********************/
@@ -1053,7 +1024,6 @@ struct ath5k_hw {
bool ah_running;
bool ah_single_chip;
bool ah_combined_mic;
enum ath5k_rfgain ah_rf_gain;
u32 ah_mac_srev;
u16 ah_mac_version;
@@ -1061,7 +1031,6 @@ struct ath5k_hw {
u16 ah_phy_revision;
u16 ah_radio_5ghz_revision;
u16 ah_radio_2ghz_revision;
u32 ah_phy_spending;
enum ath5k_version ah_version;
enum ath5k_radio ah_radio;
@@ -1112,8 +1081,9 @@ struct ath5k_hw {
u32 ah_txq_isr;
u32 *ah_rf_banks;
size_t ah_rf_banks_size;
size_t ah_rf_regs_count;
struct ath5k_gain ah_gain;
u32 ah_offset[AR5K_MAX_RF_BANKS];
u8 ah_offset[AR5K_MAX_RF_BANKS];
struct {
u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
@@ -1186,6 +1156,7 @@ extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_l
/* EEPROM access functions */
extern int ath5k_eeprom_init(struct ath5k_hw *ah);
extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
/* Protocol Control Unit Functions */
extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
@@ -1261,10 +1232,12 @@ extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
/* Initialize RF */
extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
struct ieee80211_channel *channel,
unsigned int mode);
extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
/* PHY/RF channel functions */
extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
@@ -1286,6 +1259,7 @@ extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
/*
* Translate usec to hw clock units
* TODO: Half/quarter rate
*/
static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
{
@@ -1294,6 +1268,7 @@ static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
/*
* Translate hw clock units to usec
* TODO: Half/quarter rate
*/
static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
{
drivers/net/wireless/ath5k/attach.c
+3 -15
View File
@@ -169,7 +169,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_single_chip = false;
ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_2GHZ);
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
break;
case AR5K_SREV_RAD_5112:
case AR5K_SREV_RAD_2112:
@@ -177,38 +176,31 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_single_chip = false;
ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_2GHZ);
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
break;
case AR5K_SREV_RAD_2413:
ah->ah_radio = AR5K_RF2413;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
break;
case AR5K_SREV_RAD_5413:
ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
break;
case AR5K_SREV_RAD_2316:
ah->ah_radio = AR5K_RF2316;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
break;
case AR5K_SREV_RAD_2317:
ah->ah_radio = AR5K_RF2317;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
break;
case AR5K_SREV_RAD_5424:
if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
ah->ah_mac_version == AR5K_SREV_AR2417){
ah->ah_radio = AR5K_RF2425;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
} else {
ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
}
break;
default:
@@ -227,29 +219,25 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ah->ah_radio = AR5K_RF2425;
ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
} else if (srev == AR5K_SREV_AR5213A &&
ah->ah_phy_revision == AR5K_SREV_PHY_2112B) {
ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ah->ah_radio = AR5K_RF5112;
ah->ah_single_chip = false;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
ah->ah_radio = AR5K_RF2316;
ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
ah->ah_radio = AR5K_RF5413;
ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
ah->ah_radio = AR5K_RF2413;
ah->ah_single_chip = true;
ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
} else {
ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
ret = -ENODEV;
@@ -331,7 +319,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
ath5k_hw_set_opmode(ah);
ath5k_hw_set_rfgain_opt(ah);
ath5k_hw_rfgain_opt_init(ah);
return ah;
err_free:
drivers/net/wireless/ath5k/base.c
+4 -11
View File
@@ -2209,10 +2209,6 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
*
* @sc: struct ath5k_softc pointer we are operating on
*
* When operating in station mode we want to receive a BMISS interrupt when we
* stop seeing beacons from the AP we've associated with so we can look for
* another AP to associate with.
*
* In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
* interrupts to detect TSF updates only.
*/
@@ -2225,9 +2221,7 @@ ath5k_beacon_config(struct ath5k_softc *sc)
sc->bmisscount = 0;
sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
if (sc->opmode == NL80211_IFTYPE_STATION) {
sc->imask |= AR5K_INT_BMISS;
} else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
if (sc->opmode == NL80211_IFTYPE_ADHOC ||
sc->opmode == NL80211_IFTYPE_MESH_POINT ||
sc->opmode == NL80211_IFTYPE_AP) {
/*
@@ -2479,6 +2473,7 @@ ath5k_intr(int irq, void *dev_id)
| AR5K_INT_TXERR | AR5K_INT_TXEOL))
tasklet_schedule(&sc->txtq);
if (status & AR5K_INT_BMISS) {
/* TODO */
}
if (status & AR5K_INT_MIB) {
/*
@@ -2518,7 +2513,7 @@ ath5k_calibrate(unsigned long data)
ieee80211_frequency_to_channel(sc->curchan->center_freq),
sc->curchan->hw_value);
if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
/*
* Rfgain is out of bounds, reset the chip
* to load new gain values.
@@ -2889,7 +2884,7 @@ ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
{
struct ath5k_softc *sc = hw->priv;
struct ath5k_hw *ah = sc->ah;
int ret;
int ret = 0;
mutex_lock(&sc->lock);
if (sc->vif != vif) {
@@ -2915,9 +2910,7 @@ ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
}
ath5k_beacon_update(sc, beacon);
}
mutex_unlock(&sc->lock);
return ath5k_reset_wake(sc);
unlock:
mutex_unlock(&sc->lock);
return ret;
drivers/net/wireless/ath5k/eeprom.c
+15 -3
View File
@@ -204,7 +204,7 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
/* Get antenna modes */
ah->ah_antenna[mode][0] =
(ee->ee_ant_control[mode][0] << 4) | 0x1;
(ee->ee_ant_control[mode][0] << 4);
ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
ee->ee_ant_control[mode][1] |
(ee->ee_ant_control[mode][2] << 6) |
@@ -517,9 +517,9 @@ ath5k_eeprom_init_modes(struct ath5k_hw *ah)
static inline void
ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
{
const static u16 intercepts3[] =
static const u16 intercepts3[] =
{ 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
const static u16 intercepts3_2[] =
static const u16 intercepts3_2[] =
{ 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
const u16 *ip;
int i;
@@ -1412,6 +1412,7 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
return 0;
}
/*
* Read the MAC address from eeprom
*/
@@ -1448,3 +1449,14 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
return 0;
}
bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
{
u16 data;
ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
return true;
else
return false;
}
drivers/net/wireless/ath5k/eeprom.h
+1
View File
@@ -25,6 +25,7 @@
#define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
drivers/net/wireless/ath5k/initvals.c
+662 -915
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath5k/phy.c
+577 -1522
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath5k/reg.h
+51 -73
View File
@@ -187,6 +187,7 @@
#define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
/*
@@ -753,7 +754,7 @@
*/
#define AR5K_DCU_SEQNUM_BASE 0x1140
#define AR5K_DCU_SEQNUM_M 0x00000fff
#define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
/*
* DCU global IFS SIFS register
@@ -811,6 +812,8 @@
/*
* DCU transmit filter table 0 (32 entries)
* each entry contains a 32bit slice of the
* 128bit tx filter for each DCU (4 slices per DCU)
*/
#define AR5K_DCU_TX_FILTER_0_BASE 0x1038
#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
@@ -819,7 +822,7 @@
* DCU transmit filter table 1 (16 entries)
*/
#define AR5K_DCU_TX_FILTER_1_BASE 0x103c
#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64))
#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
/*
* DCU clear transmit filter register
@@ -1447,7 +1450,7 @@
AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
/*
* Last beacon timestamp register
* Last beacon timestamp register (Read Only)
*/
#define AR5K_LAST_TSTP 0x8080
@@ -1465,7 +1468,7 @@
#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */
#define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */
#define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */
#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* Test ARM (Adaptive Radio Mode ?) */
#define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */
/*
* Default antenna register [5211+]
@@ -1677,7 +1680,7 @@
* TSF parameter register
*/
#define AR5K_TSF_PARM 0x8104 /* Register Address */
#define AR5K_TSF_PARM_INC_M 0x000000ff /* Mask for TSF increment */
#define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */
#define AR5K_TSF_PARM_INC_S 0
/*
@@ -1689,7 +1692,7 @@
#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */
#define AR5K_QOS_NOACK_BIT_OFFSET_S 4
#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */
#define AR5K_QOS_NOACK_BYTE_OFFSET_S 8
#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
/*
* PHY error filter register
@@ -1848,15 +1851,14 @@
* TST_2 (Misc config parameters)
*/
#define AR5K_PHY_TST2 0x9800 /* Register Address */
#define AR5K_PHY_TST2_TRIG_SEL 0x00000001 /* Trigger select (?) (field ?) */
#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) (field ?) */
#define AR5K_PHY_TST2_CBUS_MODE 0x00000100 /* Cardbus mode (?) */
/* bit reserved */
#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/
#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */
#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */
#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */
#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch) */
#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */
#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */
#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */
@@ -1926,8 +1928,8 @@
#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
#define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* TX end to XLNA on */
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 0
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */
#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
#define AR5K_PHY_ADC_CTL 0x982c
#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
@@ -1961,7 +1963,7 @@
#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */
#define AR5K_PHY_SETTLING_AGC_S 0
#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */
#define AR5K_PHY_SETTLINK_SWITCH_S 7
#define AR5K_PHY_SETTLING_SWITCH_S 7
/*
* PHY Gain registers
@@ -2067,14 +2069,14 @@
* PHY sleep registers [5112+]
*/
#define AR5K_PHY_SCR 0x9870
#define AR5K_PHY_SCR_32MHZ 0x0000001f
#define AR5K_PHY_SLMT 0x9874
#define AR5K_PHY_SLMT_32MHZ 0x0000007f
#define AR5K_PHY_SCAL 0x9878
#define AR5K_PHY_SCAL_32MHZ 0x0000000e
#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
/*
* PHY PLL (Phase Locked Loop) control register
@@ -2101,34 +2103,10 @@
/*
* RF Buffer register
*
* There are some special control registers on the RF chip
* that hold various operation settings related mostly to
* the analog parts (channel, gain adjustment etc).
*
* We don't write on those registers directly but
* we send a data packet on the buffer register and
* then write on another special register to notify hw
* to apply the settings. This is done so that control registers
* can be dynamicaly programmed during operation and the settings
* are applied faster on the hw.
*
* We sent such data packets during rf initialization and channel change
* through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions.
*
* The data packets we send during initializadion are inside ath5k_ini_rf
* struct (see ath5k_hw.h) and each one is related to an "rf register bank".
* We use *rfregs functions to modify them acording to current operation
* mode and eeprom values and pass them all together to the chip.
*
* It's obvious from the code that 0x989c is the buffer register but
* for the other special registers that we write to after sending each
* packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers
* for now. It's interesting that they are also used for some other operations.
*
* Also check out hw.h and U.S. Patent 6677779 B1 (about buffer
* registers and control registers):
*
* http://www.google.com/patents?id=qNURAAAAEBAJ
*/
#define AR5K_RF_BUFFER 0x989c
@@ -2178,7 +2156,8 @@
#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */
#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */
#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x00000010 /* Switch table idle (?) */
#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */
#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
/*
* PHY receiver delay register [5111+]
@@ -2218,7 +2197,7 @@
#define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 0
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */
#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */
#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */
@@ -2243,9 +2222,7 @@
#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
/*
* PHY PAPD probe register [5111+ (?)]
* Is this only present in 5212 ?
* Because it's always 0 in 5211 initialization code
* PHY PAPD probe register [5111+]
*/
#define AR5K_PHY_PAPD_PROBE 0x9930
#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
@@ -2302,6 +2279,15 @@
AR5K_PHY_FRAME_CTL_PARITY_ERR | \
AR5K_PHY_FRAME_CTL_TIMING_ERR
/*
* PHY Tx Power adjustment register [5212A+]
*/
#define AR5K_PHY_TX_PWR_ADJ 0x994c
#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
/*
* PHY radar detection register [5111+]
*/
@@ -2355,7 +2341,7 @@
#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ff3000
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
/*
@@ -2387,21 +2373,21 @@
#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
#define AR_PHY_TIMING_9 0x9998
#define AR_PHY_TIMING_10 0x999c
#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0
#define AR5K_PHY_TIMING_9 0x9998
#define AR5K_PHY_TIMING_10 0x999c
#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
/*
* Spur mitigation control
*/
#define AR_PHY_TIMING_11 0x99a0 /* Register address */
#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20
#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
/*
* Gain tables
@@ -2483,17 +2469,7 @@
#define AR5K_PHY_SDELAY 0x99f4
#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
#define AR5K_PHY_SPENDING 0x99f8
#define AR5K_PHY_SPENDING_14 0x00000014
#define AR5K_PHY_SPENDING_18 0x00000018
#define AR5K_PHY_SPENDING_RF5111 0x00000018
#define AR5K_PHY_SPENDING_RF5112 0x00000014
/* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */
/* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */
#define AR5K_PHY_SPENDING_RF5413 0x00000018
#define AR5K_PHY_SPENDING_RF2413 0x00000018
#define AR5K_PHY_SPENDING_RF2316 0x00000018
#define AR5K_PHY_SPENDING_RF2317 0x00000018
#define AR5K_PHY_SPENDING_RF2425 0x00000014
/*
* PHY PAPD I (power?) table (?)
@@ -2505,11 +2481,7 @@
/*
* PHY PCDAC TX power table
*/
#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180
#define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280
#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \
AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\
AR5K_PHY_PCDAC_TXPOWER_BASE_5211)
#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
/*
@@ -2590,3 +2562,9 @@
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
/*
* PHY PDADC Tx power table
*/
#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
drivers/net/wireless/ath5k/reset.c
+685 -265
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath5k/rfbuffer.h
+1181
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath5k/rfgain.h
+516
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath9k/ahb.c
+7 -9
View File
@@ -19,9 +19,7 @@
#include <linux/nl80211.h>
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include "core.h"
#include "reg.h"
#include "hw.h"
#include "ath9k.h"
/* return bus cachesize in 4B word units */
static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz)
@@ -34,7 +32,7 @@ static void ath_ahb_cleanup(struct ath_softc *sc)
iounmap(sc->mem);
}
static bool ath_ahb_eeprom_read(struct ath_hal *ah, u32 off, u16 *data)
static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
{
struct ath_softc *sc = ah->ah_sc;
struct platform_device *pdev = to_platform_device(sc->dev);
@@ -67,7 +65,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
struct resource *res;
int irq;
int ret = 0;
struct ath_hal *ah;
struct ath_hw *ah;
if (!pdev->dev.platform_data) {
dev_err(&pdev->dev, "no platform data specified\n");
@@ -134,10 +132,10 @@ static int ath_ahb_probe(struct platform_device *pdev)
"%s: Atheros AR%s MAC/BB Rev:%x, "
"AR%s RF Rev:%x, mem=0x%lx, irq=%d\n",
wiphy_name(hw->wiphy),
ath_mac_bb_name(ah->ah_macVersion),
ah->ah_macRev,
ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
ah->ah_phyRev,
ath_mac_bb_name(ah->hw_version.macVersion),
ah->hw_version.macRev,
ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
ah->hw_version.phyRev,
(unsigned long)mem, irq);
return 0;
drivers/net/wireless/ath9k/ani.c
+119 -142
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath9k/ani.h
+138
View File
@@ -0,0 +1,138 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef ANI_H
#define ANI_H
#define HAL_PROCESS_ANI 0x00000001
#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI))
#define HAL_EP_RND(x, mul) \
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
#define BEACON_RSSI(ahp) \
HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \
ATH9K_RSSI_EP_MULTIPLIER)
#define ATH9K_ANI_OFDM_TRIG_HIGH 500
#define ATH9K_ANI_OFDM_TRIG_LOW 200
#define ATH9K_ANI_CCK_TRIG_HIGH 200
#define ATH9K_ANI_CCK_TRIG_LOW 100
#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
#define ATH9K_ANI_CCK_WEAK_SIG_THR false
#define ATH9K_ANI_SPUR_IMMUNE_LVL 7
#define ATH9K_ANI_FIRSTEP_LVL 0
#define ATH9K_ANI_RSSI_THR_HIGH 40
#define ATH9K_ANI_RSSI_THR_LOW 7
#define ATH9K_ANI_PERIOD 100
#define HAL_NOISE_IMMUNE_MAX 4
#define HAL_SPUR_IMMUNE_MAX 7
#define HAL_FIRST_STEP_MAX 2
enum ath9k_ani_cmd {
ATH9K_ANI_PRESENT = 0x1,
ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
ATH9K_ANI_MODE = 0x40,
ATH9K_ANI_PHYERR_RESET = 0x80,
ATH9K_ANI_ALL = 0xff
};
struct ath9k_mib_stats {
u32 ackrcv_bad;
u32 rts_bad;
u32 rts_good;
u32 fcs_bad;
u32 beacons;
};
struct ath9k_node_stats {
u32 ns_avgbrssi;
u32 ns_avgrssi;
u32 ns_avgtxrssi;
u32 ns_avgtxrate;
};
struct ar5416AniState {
struct ath9k_channel *c;
u8 noiseImmunityLevel;
u8 spurImmunityLevel;
u8 firstepLevel;
u8 ofdmWeakSigDetectOff;
u8 cckWeakSigThreshold;
u32 listenTime;
u32 ofdmTrigHigh;
u32 ofdmTrigLow;
int32_t cckTrigHigh;
int32_t cckTrigLow;
int32_t rssiThrLow;
int32_t rssiThrHigh;
u32 noiseFloor;
u32 txFrameCount;
u32 rxFrameCount;
u32 cycleCount;
u32 ofdmPhyErrCount;
u32 cckPhyErrCount;
u32 ofdmPhyErrBase;
u32 cckPhyErrBase;
int16_t pktRssi[2];
int16_t ofdmErrRssi[2];
int16_t cckErrRssi[2];
};
struct ar5416Stats {
u32 ast_ani_niup;
u32 ast_ani_nidown;
u32 ast_ani_spurup;
u32 ast_ani_spurdown;
u32 ast_ani_ofdmon;
u32 ast_ani_ofdmoff;
u32 ast_ani_cckhigh;
u32 ast_ani_ccklow;
u32 ast_ani_stepup;
u32 ast_ani_stepdown;
u32 ast_ani_ofdmerrs;
u32 ast_ani_cckerrs;
u32 ast_ani_reset;
u32 ast_ani_lzero;
u32 ast_ani_lneg;
struct ath9k_mib_stats ast_mibstats;
struct ath9k_node_stats ast_nodestats;
};
#define ah_mibStats stats.ast_mibstats
void ath9k_ani_reset(struct ath_hw *ah);
void ath9k_hw_ani_monitor(struct ath_hw *ah,
const struct ath9k_node_stats *stats,
struct ath9k_channel *chan);
bool ath9k_hw_phycounters(struct ath_hw *ah);
void ath9k_enable_mib_counters(struct ath_hw *ah);
void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
u32 *rxf_pcnt, u32 *txf_pcnt);
void ath9k_hw_procmibevent(struct ath_hw *ah,
const struct ath9k_node_stats *stats);
void ath9k_hw_ani_setup(struct ath_hw *ah);
void ath9k_hw_ani_attach(struct ath_hw *ah);
void ath9k_hw_ani_detach(struct ath_hw *ah);
#endif /* ANI_H */
drivers/net/wireless/ath9k/ath9k.h
+631 -989
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath9k/beacon.c
+48 -48
View File
@@ -14,7 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "core.h"
#include "ath9k.h"
/*
* This function will modify certain transmit queue properties depending on
@@ -23,11 +23,11 @@
*/
static int ath_beaconq_config(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
struct ath9k_tx_queue_info qi;
ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/* Always burst out beacon and CAB traffic. */
qi.tqi_aifs = 1;
qi.tqi_cwmin = 0;
@@ -63,10 +63,10 @@ static void ath_bstuck_process(struct ath_softc *sc)
* Beacons are always sent out at the lowest rate, and are not retried.
*/
static void ath_beacon_setup(struct ath_softc *sc,
struct ath_vap *avp, struct ath_buf *bf)
struct ath_vif *avp, struct ath_buf *bf)
{
struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
struct ath_desc *ds;
struct ath9k_11n_rate_series series[4];
struct ath_rate_table *rt;
@@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
flags = ATH9K_TXDESC_NOACK;
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
ds->ds_link = bf->bf_daddr; /* self-linked */
flags |= ATH9K_TXDESC_VEOL;
/* Let hardware handle antenna switching. */
@@ -96,7 +96,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
* SWBA's
* XXX assumes two antenna
*/
antenna = ((sc->beacon.ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
}
ds->ds_data = bf->bf_buf_addr;
@@ -132,24 +132,24 @@ static void ath_beacon_setup(struct ath_softc *sc,
memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
series[0].Tries = 1;
series[0].Rate = rate;
series[0].ChSel = sc->sc_tx_chainmask;
series[0].ChSel = sc->tx_chainmask;
series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
ctsrate, ctsduration, series, 4, 0);
}
/* Generate beacon frame and queue cab data for a vap */
/* Generate beacon frame and queue cab data for a VIF */
static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
{
struct ath_buf *bf;
struct ath_vap *avp;
struct ath_vif *avp;
struct sk_buff *skb;
struct ath_txq *cabq;
struct ieee80211_vif *vif;
struct ieee80211_tx_info *info;
int cabq_depth;
vif = sc->sc_vaps[if_id];
vif = sc->vifs[if_id];
ASSERT(vif);
avp = (void *)vif->drv_priv;
@@ -204,10 +204,10 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
/*
* if the CABQ traffic from previous DTIM is pending and the current
* beacon is also a DTIM.
* 1) if there is only one vap let the cab traffic continue.
* 2) if there are more than one vap and we are using staggered
* 1) if there is only one vif let the cab traffic continue.
* 2) if there are more than one vif and we are using staggered
* beacons, then drain the cabq by dropping all the frames in
* the cabq so that the current vaps cab traffic can be scheduled.
* the cabq so that the current vifs cab traffic can be scheduled.
*/
spin_lock_bh(&cabq->axq_lock);
cabq_depth = cabq->axq_depth;
@@ -219,7 +219,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
* the lock again which is a common function and that
* acquires txq lock inside.
*/
if (sc->sc_nvaps > 1) {
if (sc->nvifs > 1) {
ath_draintxq(sc, cabq, false);
DPRINTF(sc, ATH_DBG_BEACON,
"flush previous cabq traffic\n");
@@ -248,12 +248,12 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
{
struct ieee80211_vif *vif;
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
struct ath_buf *bf;
struct ath_vap *avp;
struct ath_vif *avp;
struct sk_buff *skb;
vif = sc->sc_vaps[if_id];
vif = sc->vifs[if_id];
ASSERT(vif);
avp = (void *)vif->drv_priv;
@@ -276,7 +276,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
}
int ath_beaconq_setup(struct ath_hal *ah)
int ath_beaconq_setup(struct ath_hw *ah)
{
struct ath9k_tx_queue_info qi;
@@ -291,13 +291,13 @@ int ath_beaconq_setup(struct ath_hal *ah)
int ath_beacon_alloc(struct ath_softc *sc, int if_id)
{
struct ieee80211_vif *vif;
struct ath_vap *avp;
struct ath_vif *avp;
struct ieee80211_hdr *hdr;
struct ath_buf *bf;
struct sk_buff *skb;
__le64 tstamp;
vif = sc->sc_vaps[if_id];
vif = sc->vifs[if_id];
ASSERT(vif);
avp = (void *)vif->drv_priv;
@@ -310,11 +310,11 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
struct ath_buf, list);
list_del(&avp->av_bcbuf->list);
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
int slot;
/*
* Assign the vap to a beacon xmit slot. As
* Assign the vif to a beacon xmit slot. As
* above, this cannot fail to find one.
*/
avp->av_bslot = 0;
@@ -335,7 +335,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
}
BUG_ON(sc->beacon.bslot[avp->av_bslot] != ATH_IF_ID_ANY);
sc->beacon.bslot[avp->av_bslot] = if_id;
sc->sc_nbcnvaps++;
sc->nbcnvifs++;
}
}
@@ -384,8 +384,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
* timestamp then convert to TSF units and handle
* byte swapping before writing it in the frame.
* The hardware will then add this each time a beacon
* frame is sent. Note that we align vap's 1..N
* and leave vap 0 untouched. This means vap 0
* frame is sent. Note that we align vif's 1..N
* and leave vif 0 untouched. This means vap 0
* has a timestamp in one beacon interval while the
* others get a timestamp aligned to the next interval.
*/
@@ -416,14 +416,14 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
return 0;
}
void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
{
if (avp->av_bcbuf != NULL) {
struct ath_buf *bf;
if (avp->av_bslot != -1) {
sc->beacon.bslot[avp->av_bslot] = ATH_IF_ID_ANY;
sc->sc_nbcnvaps--;
sc->nbcnvifs--;
}
bf = avp->av_bcbuf;
@@ -444,7 +444,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
void ath9k_beacon_tasklet(unsigned long data)
{
struct ath_softc *sc = (struct ath_softc *)data;
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
struct ath_buf *bf = NULL;
int slot, if_id;
u32 bfaddr;
@@ -597,7 +597,7 @@ void ath9k_beacon_tasklet(unsigned long data)
ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
ath9k_hw_txstart(ah, sc->beacon.beaconq);
sc->beacon.ast_be_xmit += bc; /* XXX per-vap? */
sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
}
}
@@ -619,19 +619,19 @@ void ath9k_beacon_tasklet(unsigned long data)
void ath_beacon_config(struct ath_softc *sc, int if_id)
{
struct ieee80211_vif *vif;
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
struct ath_beacon_config conf;
struct ath_vap *avp;
struct ath_vif *avp;
enum nl80211_iftype opmode;
u32 nexttbtt, intval;
if (if_id != ATH_IF_ID_ANY) {
vif = sc->sc_vaps[if_id];
vif = sc->vifs[if_id];
ASSERT(vif);
avp = (void *)vif->drv_priv;
opmode = avp->av_opmode;
} else {
opmode = sc->sc_ah->ah_opmode;
opmode = sc->sc_ah->opmode;
}
memset(&conf, 0, sizeof(struct ath_beacon_config));
@@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
/* XXX conditionalize multi-bss support? */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/*
* For multi-bss ap support beacons are either staggered
* evenly over N slots or burst together. For the former
@@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
nexttbtt, intval, conf.beacon_interval);
/* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
struct ath9k_beacon_state bs;
u64 tsf;
u32 tsftu;
@@ -781,15 +781,15 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
ath9k_hw_set_interrupts(ah, 0);
ath9k_hw_set_sta_beacon_timers(ah, &bs);
sc->sc_imask |= ATH9K_INT_BMISS;
ath9k_hw_set_interrupts(ah, sc->sc_imask);
sc->imask |= ATH9K_INT_BMISS;
ath9k_hw_set_interrupts(ah, sc->imask);
} else {
u64 tsf;
u32 tsftu;
ath9k_hw_set_interrupts(ah, 0);
if (nexttbtt == intval)
intval |= ATH9K_BEACON_RESET_TSF;
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
/*
* Pull nexttbtt forward to reflect the current
* TSF
@@ -818,27 +818,27 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
* deal with things.
*/
intval |= ATH9K_BEACON_ENA;
if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
sc->sc_imask |= ATH9K_INT_SWBA;
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
sc->imask |= ATH9K_INT_SWBA;
ath_beaconq_config(sc);
} else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
} else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
/*
* In AP mode we enable the beacon timers and
* SWBA interrupts to prepare beacon frames.
*/
intval |= ATH9K_BEACON_ENA;
sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */
sc->imask |= ATH9K_INT_SWBA; /* beacon prepare */
ath_beaconq_config(sc);
}
ath9k_hw_beaconinit(ah, nexttbtt, intval);
sc->beacon.bmisscnt = 0;
ath9k_hw_set_interrupts(ah, sc->sc_imask);
ath9k_hw_set_interrupts(ah, sc->imask);
/*
* When using a self-linked beacon descriptor in
* ibss mode load it once here.
*/
if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC &&
(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC &&
(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL))
ath_beacon_start_adhoc(sc, 0);
}
}
drivers/net/wireless/ath9k/calib.c
+86 -104
View File
@@ -14,10 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "core.h"
#include "hw.h"
#include "reg.h"
#include "phy.h"
#include "ath9k.h"
/* We can tune this as we go by monitoring really low values */
#define ATH9K_NF_TOO_LOW -60
@@ -26,7 +23,7 @@
* is incorrect and we should use the static NF value. Later we can try to
* find out why they are reporting these values */
static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
{
if (nf > ATH9K_NF_TOO_LOW) {
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
@@ -89,7 +86,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
return;
}
static void ath9k_hw_do_getnf(struct ath_hal *ah,
static void ath9k_hw_do_getnf(struct ath_hw *ah,
int16_t nfarray[NUM_NF_READINGS])
{
int16_t nf;
@@ -169,16 +166,16 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
}
}
static bool getNoiseFloorThresh(struct ath_hal *ah,
static bool getNoiseFloorThresh(struct ath_hw *ah,
enum ieee80211_band band,
int16_t *nft)
{
switch (band) {
case IEEE80211_BAND_5GHZ:
*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
break;
case IEEE80211_BAND_2GHZ:
*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
break;
default:
BUG_ON(1);
@@ -188,7 +185,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah,
return true;
}
static void ath9k_hw_setup_calibration(struct ath_hal *ah,
static void ath9k_hw_setup_calibration(struct ath_hw *ah,
struct hal_cal_list *currCal)
{
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
@@ -222,10 +219,9 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah,
AR_PHY_TIMING_CTRL4_DO_CAL);
}
static void ath9k_hw_reset_calibration(struct ath_hal *ah,
static void ath9k_hw_reset_calibration(struct ath_hw *ah,
struct hal_cal_list *currCal)
{
struct ath_hal_5416 *ahp = AH5416(ah);
int i;
ath9k_hw_setup_calibration(ah, currCal);
@@ -233,23 +229,21 @@ static void ath9k_hw_reset_calibration(struct ath_hal *ah,
currCal->calState = CAL_RUNNING;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ahp->ah_Meas0.sign[i] = 0;
ahp->ah_Meas1.sign[i] = 0;
ahp->ah_Meas2.sign[i] = 0;
ahp->ah_Meas3.sign[i] = 0;
ah->meas0.sign[i] = 0;
ah->meas1.sign[i] = 0;
ah->meas2.sign[i] = 0;
ah->meas3.sign[i] = 0;
}
ahp->ah_CalSamples = 0;
ah->cal_samples = 0;
}
static void ath9k_hw_per_calibration(struct ath_hal *ah,
static void ath9k_hw_per_calibration(struct ath_hw *ah,
struct ath9k_channel *ichan,
u8 rxchainmask,
struct hal_cal_list *currCal,
bool *isCalDone)
{
struct ath_hal_5416 *ahp = AH5416(ah);
*isCalDone = false;
if (currCal->calState == CAL_RUNNING) {
@@ -257,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
AR_PHY_TIMING_CTRL4_DO_CAL)) {
currCal->calData->calCollect(ah);
ahp->ah_CalSamples++;
ah->cal_samples++;
if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) {
if (ah->cal_samples >= currCal->calData->calNumSamples) {
int i, numChains = 0;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
if (rxchainmask & (1 << i))
@@ -280,13 +274,12 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
}
/* Assumes you are talking about the currently configured channel */
static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
enum hal_cal_types calType)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
switch (calType & ahp->ah_suppCals) {
switch (calType & ah->supp_cals) {
case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
return true;
case ADC_GAIN_CAL:
@@ -299,90 +292,86 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
return false;
}
static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ahp->ah_totalPowerMeasI[i] +=
ah->totalPowerMeasI[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ahp->ah_totalPowerMeasQ[i] +=
ah->totalPowerMeasQ[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ahp->ah_totalIqCorrMeas[i] +=
ah->totalIqCorrMeas[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
ahp->ah_totalPowerMeasQ[i],
ahp->ah_totalIqCorrMeas[i]);
ah->cal_samples, i, ah->totalPowerMeasI[i],
ah->totalPowerMeasQ[i],
ah->totalIqCorrMeas[i]);
}
}
static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ahp->ah_totalAdcIOddPhase[i] +=
ah->totalAdcIOddPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ahp->ah_totalAdcIEvenPhase[i] +=
ah->totalAdcIEvenPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ahp->ah_totalAdcQOddPhase[i] +=
ah->totalAdcQOddPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
ahp->ah_totalAdcQEvenPhase[i] +=
ah->totalAdcQEvenPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n",
ahp->ah_CalSamples, i,
ahp->ah_totalAdcIOddPhase[i],
ahp->ah_totalAdcIEvenPhase[i],
ahp->ah_totalAdcQOddPhase[i],
ahp->ah_totalAdcQEvenPhase[i]);
ah->cal_samples, i,
ah->totalAdcIOddPhase[i],
ah->totalAdcIEvenPhase[i],
ah->totalAdcQOddPhase[i],
ah->totalAdcQEvenPhase[i]);
}
}
static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
int i;
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
ah->totalAdcDcOffsetIOddPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
ah->totalAdcDcOffsetIEvenPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
ah->totalAdcDcOffsetQOddPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
ah->totalAdcDcOffsetQEvenPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n",
ahp->ah_CalSamples, i,
ahp->ah_totalAdcDcOffsetIOddPhase[i],
ahp->ah_totalAdcDcOffsetIEvenPhase[i],
ahp->ah_totalAdcDcOffsetQOddPhase[i],
ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
ah->cal_samples, i,
ah->totalAdcDcOffsetIOddPhase[i],
ah->totalAdcDcOffsetIEvenPhase[i],
ah->totalAdcDcOffsetQOddPhase[i],
ah->totalAdcDcOffsetQEvenPhase[i]);
}
}
static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
{
struct ath_hal_5416 *ahp = AH5416(ah);
u32 powerMeasQ, powerMeasI, iqCorrMeas;
u32 qCoffDenom, iCoffDenom;
int32_t qCoff, iCoff;
int iqCorrNeg, i;
for (i = 0; i < numChains; i++) {
powerMeasI = ahp->ah_totalPowerMeasI[i];
powerMeasQ = ahp->ah_totalPowerMeasQ[i];
iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
powerMeasI = ah->totalPowerMeasI[i];
powerMeasQ = ah->totalPowerMeasQ[i];
iqCorrMeas = ah->totalIqCorrMeas[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting IQ Cal and Correction for Chain %d\n",
@@ -390,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Orignal: Chn %diq_corr_meas = 0x%08x\n",
i, ahp->ah_totalIqCorrMeas[i]);
i, ah->totalIqCorrMeas[i]);
iqCorrNeg = 0;
@@ -448,17 +437,16 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
}
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
{
struct ath_hal_5416 *ahp = AH5416(ah);
u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
u32 qGainMismatch, iGainMismatch, val, i;
for (i = 0; i < numChains; i++) {
iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
iOddMeasOffset = ah->totalAdcIOddPhase[i];
iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
qOddMeasOffset = ah->totalAdcQOddPhase[i];
qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting ADC Gain Cal for Chain %d\n", i);
@@ -506,21 +494,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
}
static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
{
struct ath_hal_5416 *ahp = AH5416(ah);
u32 iOddMeasOffset, iEvenMeasOffset, val, i;
int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
const struct hal_percal_data *calData =
ahp->ah_cal_list_curr->calData;
ah->cal_list_curr->calData;
u32 numSamples =
(1 << (calData->calCountMax + 5)) * calData->calNumSamples;
for (i = 0; i < numChains; i++) {
iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"Starting ADC DC Offset Cal for Chain %d\n", i);
@@ -565,13 +552,12 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
}
/* This is done for the currently configured channel */
bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
struct hal_cal_list *currCal = ah->cal_list_curr;
if (!ah->ah_curchan)
if (!ah->curchan)
return true;
if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
@@ -594,13 +580,13 @@ bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
"Resetting Cal %d state for channel %u\n",
currCal->calData->calType, conf->channel->center_freq);
ah->ah_curchan->CalValid &= ~currCal->calData->calType;
ah->curchan->CalValid &= ~currCal->calData->calType;
currCal->calState = CAL_WAITING;
return false;
}
void ath9k_hw_start_nfcal(struct ath_hal *ah)
void ath9k_hw_start_nfcal(struct ath_hw *ah)
{
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_ENABLE_NF);
@@ -609,7 +595,7 @@ void ath9k_hw_start_nfcal(struct ath_hal *ah)
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
}
void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
{
struct ath9k_nfcal_hist *h;
int i, j;
@@ -665,7 +651,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
}
}
int16_t ath9k_hw_getnf(struct ath_hal *ah,
int16_t ath9k_hw_getnf(struct ath_hw *ah,
struct ath9k_channel *chan)
{
int16_t nf, nfThresh;
@@ -701,7 +687,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
return chan->rawNoiseFloor;
}
void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
{
int i, j;
@@ -715,10 +701,9 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
AR_PHY_CCA_MAX_GOOD_VALUE;
}
}
return;
}
s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
{
s16 nf;
@@ -733,12 +718,11 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
return nf;
}
bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
u8 rxchainmask, bool longcal,
bool *isCalDone)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
struct hal_cal_list *currCal = ah->cal_list_curr;
*isCalDone = true;
@@ -748,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
isCalDone);
if (*isCalDone) {
ahp->ah_cal_list_curr = currCal = currCal->calNext;
ah->cal_list_curr = currCal = currCal->calNext;
if (currCal->calState == CAL_WAITING) {
*isCalDone = false;
@@ -759,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
if (longcal) {
ath9k_hw_getnf(ah, chan);
ath9k_hw_loadnf(ah, ah->ah_curchan);
ath9k_hw_loadnf(ah, ah->curchan);
ath9k_hw_start_nfcal(ah);
if (chan->channelFlags & CHANNEL_CW_INT)
@@ -769,7 +753,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
return true;
}
static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
{
u32 regVal;
@@ -864,11 +848,9 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
}
bool ath9k_hw_init_cal(struct ath_hal *ah,
bool ath9k_hw_init_cal(struct ath_hw *ah,
struct ath9k_channel *chan)
{
struct ath_hal_5416 *ahp = AH5416(ah);
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
REG_READ(ah, AR_PHY_AGC_CONTROL) |
AR_PHY_AGC_CONTROL_CAL);
@@ -887,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
REG_READ(ah, AR_PHY_AGC_CONTROL) |
AR_PHY_AGC_CONTROL_NF);
ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
INIT_CAL(&ahp->ah_adcGainCalData);
INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
INIT_CAL(&ah->adcgain_caldata);
INSERT_CAL(ah, &ah->adcgain_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling ADC Gain Calibration.\n");
}
if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
INIT_CAL(&ahp->ah_adcDcCalData);
INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
INIT_CAL(&ah->adcdc_caldata);
INSERT_CAL(ah, &ah->adcdc_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling ADC DC Calibration.\n");
}
if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
INIT_CAL(&ahp->ah_iqCalData);
INSERT_CAL(ahp, &ahp->ah_iqCalData);
INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata);
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n");
}
ahp->ah_cal_list_curr = ahp->ah_cal_list;
ah->cal_list_curr = ah->cal_list;
if (ahp->ah_cal_list_curr)
ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
if (ah->cal_list_curr)
ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
}
chan->CalValid = 0;
drivers/net/wireless/ath9k/calib.h
+124
View File
@@ -0,0 +1,124 @@
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef CALIB_H
#define CALIB_H
extern const struct hal_percal_data iq_cal_multi_sample;
extern const struct hal_percal_data iq_cal_single_sample;
extern const struct hal_percal_data adc_gain_cal_multi_sample;
extern const struct hal_percal_data adc_gain_cal_single_sample;
extern const struct hal_percal_data adc_dc_cal_multi_sample;
extern const struct hal_percal_data adc_dc_cal_single_sample;
extern const struct hal_percal_data adc_init_dc_cal;
#define AR_PHY_CCA_MAX_GOOD_VALUE -85
#define AR_PHY_CCA_MAX_HIGH_VALUE -62
#define AR_PHY_CCA_MIN_BAD_VALUE -121
#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
#define NUM_NF_READINGS 6
#define ATH9K_NF_CAL_HIST_MAX 5
struct ar5416IniArray {
u32 *ia_array;
u32 ia_rows;
u32 ia_columns;
};
#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
(iniarray)->ia_array = (u32 *)(array); \
(iniarray)->ia_rows = (rows); \
(iniarray)->ia_columns = (columns); \
} while (0)
#define INI_RA(iniarray, row, column) \
(((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
#define INIT_CAL(_perCal) do { \
(_perCal)->calState = CAL_WAITING; \
(_perCal)->calNext = NULL; \
} while (0)
#define INSERT_CAL(_ahp, _perCal) \
do { \
if ((_ahp)->cal_list_last == NULL) { \
(_ahp)->cal_list = \
(_ahp)->cal_list_last = (_perCal); \
((_ahp)->cal_list_last)->calNext = (_perCal); \
} else { \
((_ahp)->cal_list_last)->calNext = (_perCal); \
(_ahp)->cal_list_last = (_perCal); \
(_perCal)->calNext = (_ahp)->cal_list; \
} \
} while (0)
enum hal_cal_types {
ADC_DC_INIT_CAL = 0x1,
ADC_GAIN_CAL = 0x2,
ADC_DC_CAL = 0x4,
IQ_MISMATCH_CAL = 0x8
};
enum hal_cal_state {
CAL_INACTIVE,
CAL_WAITING,
CAL_RUNNING,
CAL_DONE
};
#define MIN_CAL_SAMPLES 1
#define MAX_CAL_SAMPLES 64
#define INIT_LOG_COUNT 5
#define PER_MIN_LOG_COUNT 2
#define PER_MAX_LOG_COUNT 10
struct hal_percal_data {
enum hal_cal_types calType;
u32 calNumSamples;
u32 calCountMax;
void (*calCollect) (struct ath_hw *);
void (*calPostProc) (struct ath_hw *, u8);
};
struct hal_cal_list {
const struct hal_percal_data *calData;
enum hal_cal_state calState;
struct hal_cal_list *calNext;
};
struct ath9k_nfcal_hist {
int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
u8 currIndex;
int16_t privNF;
u8 invalidNFcount;
};
bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
void ath9k_hw_start_nfcal(struct ath_hw *ah);
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
int16_t ath9k_hw_getnf(struct ath_hw *ah,
struct ath9k_channel *chan);
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
u8 rxchainmask, bool longcal,
bool *isCalDone);
bool ath9k_hw_init_cal(struct ath_hw *ah,
struct ath9k_channel *chan);
#endif /* CALIB_H */
drivers/net/wireless/ath9k/core.h
-816
View File
File diff suppressed because it is too large Load Diff
drivers/net/wireless/ath9k/debug.c
+81 -68
View File
@@ -14,9 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "core.h"
#include "reg.h"
#include "hw.h"
#include "ath9k.h"
static unsigned int ath9k_debug = DBG_DEFAULT;
module_param_named(debug, ath9k_debug, uint, 0);
@@ -26,7 +24,7 @@ void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...)
if (!sc)
return;
if (sc->sc_debug.debug_mask & dbg_mask) {
if (sc->debug.debug_mask & dbg_mask) {
va_list args;
va_start(args, fmt);
@@ -46,7 +44,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath_softc *sc = file->private_data;
struct ath_hal *ah = sc->sc_ah;
struct ath_hw *ah = sc->sc_ah;
char buf[1024];
unsigned int len = 0;
u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
@@ -132,41 +130,41 @@ static const struct file_operations fops_dma = {
void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
{
if (status)
sc->sc_debug.stats.istats.total++;
sc->debug.stats.istats.total++;
if (status & ATH9K_INT_RX)
sc->sc_debug.stats.istats.rxok++;
sc->debug.stats.istats.rxok++;
if (status & ATH9K_INT_RXEOL)
sc->sc_debug.stats.istats.rxeol++;
sc->debug.stats.istats.rxeol++;
if (status & ATH9K_INT_RXORN)
sc->sc_debug.stats.istats.rxorn++;
sc->debug.stats.istats.rxorn++;
if (status & ATH9K_INT_TX)
sc->sc_debug.stats.istats.txok++;
sc->debug.stats.istats.txok++;
if (status & ATH9K_INT_TXURN)
sc->sc_debug.stats.istats.txurn++;
sc->debug.stats.istats.txurn++;
if (status & ATH9K_INT_MIB)
sc->sc_debug.stats.istats.mib++;
sc->debug.stats.istats.mib++;
if (status & ATH9K_INT_RXPHY)
sc->sc_debug.stats.istats.rxphyerr++;
sc->debug.stats.istats.rxphyerr++;
if (status & ATH9K_INT_RXKCM)
sc->sc_debug.stats.istats.rx_keycache_miss++;
sc->debug.stats.istats.rx_keycache_miss++;
if (status & ATH9K_INT_SWBA)
sc->sc_debug.stats.istats.swba++;
sc->debug.stats.istats.swba++;
if (status & ATH9K_INT_BMISS)
sc->sc_debug.stats.istats.bmiss++;
sc->debug.stats.istats.bmiss++;
if (status & ATH9K_INT_BNR)
sc->sc_debug.stats.istats.bnr++;
sc->debug.stats.istats.bnr++;
if (status & ATH9K_INT_CST)
sc->sc_debug.stats.istats.cst++;
sc->debug.stats.istats.cst++;
if (status & ATH9K_INT_GTT)
sc->sc_debug.stats.istats.gtt++;
sc->debug.stats.istats.gtt++;
if (status & ATH9K_INT_TIM)
sc->sc_debug.stats.istats.tim++;
sc->debug.stats.istats.tim++;
if (status & ATH9K_INT_CABEND)
sc->sc_debug.stats.istats.cabend++;
sc->debug.stats.istats.cabend++;
if (status & ATH9K_INT_DTIMSYNC)
sc->sc_debug.stats.istats.dtimsync++;
sc->debug.stats.istats.dtimsync++;
if (status & ATH9K_INT_DTIM)
sc->sc_debug.stats.istats.dtim++;
sc->debug.stats.istats.dtim++;
}
static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
@@ -177,41 +175,41 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
unsigned int len = 0;
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "RX", sc->sc_debug.stats.istats.rxok);
"%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "RXEOL", sc->sc_debug.stats.istats.rxeol);
"%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "RXORN", sc->sc_debug.stats.istats.rxorn);
"%8s: %10u\n", "RXORN", sc->debug.stats.istats.rxorn);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "TX", sc->sc_debug.stats.istats.txok);
"%8s: %10u\n", "TX", sc->debug.stats.istats.txok);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "TXURN", sc->sc_debug.stats.istats.txurn);
"%8s: %10u\n", "TXURN", sc->debug.stats.istats.txurn);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "MIB", sc->sc_debug.stats.istats.mib);
"%8s: %10u\n", "MIB", sc->debug.stats.istats.mib);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "RXPHY", sc->sc_debug.stats.istats.rxphyerr);
"%8s: %10u\n", "RXPHY", sc->debug.stats.istats.rxphyerr);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "RXKCM", sc->sc_debug.stats.istats.rx_keycache_miss);
"%8s: %10u\n", "RXKCM", sc->debug.stats.istats.rx_keycache_miss);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "SWBA", sc->sc_debug.stats.istats.swba);
"%8s: %10u\n", "SWBA", sc->debug.stats.istats.swba);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "BMISS", sc->sc_debug.stats.istats.bmiss);
"%8s: %10u\n", "BMISS", sc->debug.stats.istats.bmiss);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "BNR", sc->sc_debug.stats.istats.bnr);
"%8s: %10u\n", "BNR", sc->debug.stats.istats.bnr);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "CST", sc->sc_debug.stats.istats.cst);
"%8s: %10u\n", "CST", sc->debug.stats.istats.cst);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "GTT", sc->sc_debug.stats.istats.gtt);
"%8s: %10u\n", "GTT", sc->debug.stats.istats.gtt);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "TIM", sc->sc_debug.stats.istats.tim);
"%8s: %10u\n", "TIM", sc->debug.stats.istats.tim);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "CABEND", sc->sc_debug.stats.istats.cabend);
"%8s: %10u\n", "CABEND", sc->debug.stats.istats.cabend);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "DTIMSYNC", sc->sc_debug.stats.istats.dtimsync);
"%8s: %10u\n", "DTIMSYNC", sc->debug.stats.istats.dtimsync);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "DTIM", sc->sc_debug.stats.istats.dtim);
"%8s: %10u\n", "DTIM", sc->debug.stats.istats.dtim);
len += snprintf(buf + len, sizeof(buf) - len,
"%8s: %10u\n", "TOTAL", sc->sc_debug.stats.istats.total);
"%8s: %10u\n", "TOTAL", sc->debug.stats.istats.total);
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
@@ -233,7 +231,7 @@ static void ath_debug_stat_11n_rc(struct ath_softc *sc, struct sk_buff *skb)
final_ts_idx = tx_info_priv->tx.ts_rateindex;
idx = sc->cur_rate_table->info[rates[final_ts_idx].idx].dot11rate;
sc->sc_debug.stats.n_rcstats[idx].success++;
sc->debug.stats.n_rcstats[idx].success++;
}
static void ath_debug_stat_legacy_rc(struct ath_softc *sc, struct sk_buff *skb)
@@ -247,7 +245,7 @@ static void ath_debug_stat_legacy_rc(struct ath_softc *sc, struct sk_buff *skb)
final_ts_idx = tx_info_priv->tx.ts_rateindex;
idx = rates[final_ts_idx].idx;
sc->sc_debug.stats.legacy_rcstats[idx].success++;
sc->debug.stats.legacy_rcstats[idx].success++;
}
void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb)
@@ -258,21 +256,36 @@ void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb)
ath_debug_stat_legacy_rc(sc, skb);
}
/* FIXME: legacy rates, later on .. */
void ath_debug_stat_retries(struct ath_softc *sc, int rix,
int xretries, int retries)
{
if (conf_is_ht(&sc->hw->conf)) {
int idx = sc->cur_rate_table->info[rix].dot11rate;
sc->debug.stats.n_rcstats[idx].xretries += xretries;
sc->debug.stats.n_rcstats[idx].retries += retries;
}
}
static ssize_t ath_read_file_stat_11n_rc(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath_softc *sc = file->private_data;
char buf[512];
char buf[1024];
unsigned int len = 0;
int i = 0;
len += sprintf(buf, "%7s %13s\n\n", "Rate", "Success");
len += sprintf(buf, "%7s %13s %8s %8s\n\n", "Rate", "Success",
"Retries", "XRetries");
for (i = 0; i <= 15; i++) {
len += snprintf(buf + len, sizeof(buf) - len,
"%5s%3d: %8u\n", "MCS", i,
sc->sc_debug.stats.n_rcstats[i].success);
"%5s%3d: %8u %8u %8u\n", "MCS", i,
sc->debug.stats.n_rcstats[i].success,
sc->debug.stats.n_rcstats[i].retries,
sc->debug.stats.n_rcstats[i].xretries);
}
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
@@ -292,7 +305,7 @@ static ssize_t ath_read_file_stat_legacy_rc(struct file *file,
for (i = 0; i < sc->cur_rate_table->rate_cnt; i++) {
len += snprintf(buf + len, sizeof(buf) - len, "%5u: %12u\n",
sc->cur_rate_table->info[i].ratekbps / 1000,
sc->sc_debug.stats.legacy_rcstats[i].success);
sc->debug.stats.legacy_rcstats[i].success);
}
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
@@ -317,34 +330,34 @@ static const struct file_operations fops_rcstat = {
int ath9k_init_debug(struct ath_softc *sc)
{
sc->sc_debug.debug_mask = ath9k_debug;
sc->debug.debug_mask = ath9k_debug;
sc->sc_debug.debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
if (!sc->sc_debug.debugfs_root)
sc->debug.debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
if (!sc->debug.debugfs_root)
goto err;
sc->sc_debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
sc->sc_debug.debugfs_root);
if (!sc->sc_debug.debugfs_phy)
sc->debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
sc->debug.debugfs_root);
if (!sc->debug.debugfs_phy)
goto err;
sc->sc_debug.debugfs_dma = debugfs_create_file("dma", S_IRUGO,
sc->sc_debug.debugfs_phy, sc, &fops_dma);
if (!sc->sc_debug.debugfs_dma)
sc->debug.debugfs_dma = debugfs_create_file("dma", S_IRUGO,
sc->debug.debugfs_phy, sc, &fops_dma);
if (!sc->debug.debugfs_dma)
goto err;
sc->sc_debug.debugfs_interrupt = debugfs_create_file("interrupt",
sc->debug.debugfs_interrupt = debugfs_create_file("interrupt",
S_IRUGO,
sc->sc_debug.debugfs_phy,
sc->debug.debugfs_phy,
sc, &fops_interrupt);
if (!sc->sc_debug.debugfs_interrupt)
if (!sc->debug.debugfs_interrupt)
goto err;
sc->sc_debug.debugfs_rcstat = debugfs_create_file("rcstat",
sc->debug.debugfs_rcstat = debugfs_create_file("rcstat",
S_IRUGO,
sc->sc_debug.debugfs_phy,
sc->debug.debugfs_phy,
sc, &fops_rcstat);
if (!sc->sc_debug.debugfs_rcstat)
if (!sc->debug.debugfs_rcstat)
goto err;
return 0;
@@ -355,9 +368,9 @@ err:
void ath9k_exit_debug(struct ath_softc *sc)
{
debugfs_remove(sc->sc_debug.debugfs_rcstat);
debugfs_remove(sc->sc_debug.debugfs_interrupt);
debugfs_remove(sc->sc_debug.debugfs_dma);
debugfs_remove(sc->sc_debug.debugfs_phy);
debugfs_remove(sc->sc_debug.debugfs_root);
debugfs_remove(sc->debug.debugfs_rcstat);
debugfs_remove(sc->debug.debugfs_interrupt);
debugfs_remove(sc->debug.debugfs_dma);
debugfs_remove(sc->debug.debugfs_phy);
debugfs_remove(sc->debug.debugfs_root);
}

Some files were not shown because too many files have changed in this diff Show More