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CRIS v32: remove old GPIO and LEDs code
Since we now have a gpiolib driver, remove this code: The gpio-etraxfs driver (along with things like gpio-keys-polled for polling support) replaces the GIO driver implementations in mach-a3 and mach-fs. The various generic external chip drivers replace the "virtual gpio" parts. The generic gpio-leds driver replaces the LED handling. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
This commit is contained in:
Rabin Vincent
committed by
Jesper Nilsson
Jesper Nilsson
parent
79b863c68e
commit
ab28e96fd1
@@ -10,95 +10,6 @@ config ETRAX_DRAM_VIRTUAL_BASE
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depends on ETRAX_ARCH_V32
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default "c0000000"
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choice
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prompt "Nbr of Ethernet LED groups"
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depends on ETRAX_ARCH_V32
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default ETRAX_NBR_LED_GRP_ONE
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help
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Select how many Ethernet LED groups that can be used. Usually one per Ethernet
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interface is a good choice.
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config ETRAX_NBR_LED_GRP_ZERO
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bool "Use zero LED groups"
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help
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Select this if you do not want any Ethernet LEDs.
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config ETRAX_NBR_LED_GRP_ONE
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bool "Use one LED group"
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help
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Select this if you want one Ethernet LED group. This LED group
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can be used for one or more Ethernet interfaces. However, it is
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recommended that each Ethernet interface use a dedicated LED group.
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config ETRAX_NBR_LED_GRP_TWO
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bool "Use two LED groups"
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help
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Select this if you want two Ethernet LED groups. This is the
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best choice if you have more than one Ethernet interface and
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would like to have separate LEDs for the interfaces.
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endchoice
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config ETRAX_LED_G_NET0
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string "Ethernet LED group 0 green LED bit"
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depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
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default "PA3"
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help
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Bit to use for the green LED in Ethernet LED group 0.
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config ETRAX_LED_R_NET0
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string "Ethernet LED group 0 red LED bit"
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depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
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default "PA4"
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help
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Bit to use for the red LED in Ethernet LED group 0.
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config ETRAX_LED_G_NET1
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string "Ethernet group 1 green LED bit"
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depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
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default ""
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help
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Bit to use for the green LED in Ethernet LED group 1.
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config ETRAX_LED_R_NET1
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string "Ethernet group 1 red LED bit"
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depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
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default ""
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help
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Bit to use for the red LED in Ethernet LED group 1.
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config ETRAX_V32_LED2G
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string "Second green LED bit"
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depends on ETRAX_ARCH_V32
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default "PA5"
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help
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Bit to use for the first green LED (status LED).
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Most Axis products use bit A5 here.
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config ETRAX_V32_LED2R
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string "Second red LED bit"
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depends on ETRAX_ARCH_V32
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default "PA6"
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help
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Bit to use for the first red LED (network LED).
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Most Axis products use bit A6 here.
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config ETRAX_V32_LED3G
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string "Third green LED bit"
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depends on ETRAX_ARCH_V32
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default "PA7"
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help
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Bit to use for the first green LED (drive/power LED).
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Most Axis products use bit A7 here.
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config ETRAX_V32_LED3R
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string "Third red LED bit"
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depends on ETRAX_ARCH_V32
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default "PA7"
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help
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Bit to use for the first red LED (drive/power LED).
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Most Axis products use bit A7 here.
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choice
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prompt "Kernel GDB port"
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depends on ETRAX_KGDB
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@@ -149,155 +149,6 @@ config ETRAX_NANDBOOT
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Say Y if your boot code, kernel and root file system is in
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NAND flash. Say N if they are in NOR flash.
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config ETRAX_GPIO
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bool "GPIO support"
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depends on ETRAX_ARCH_V32
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---help---
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Enables the ETRAX general port device (major 120, minors 0-4).
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You can use this driver to access the general port bits. It supports
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these ioctl's:
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#include <linux/etraxgpio.h>
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fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
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ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
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ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
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err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
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Remember that you need to setup the port directions appropriately in
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the General configuration.
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config ETRAX_VIRTUAL_GPIO
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bool "Virtual GPIO support"
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depends on ETRAX_GPIO
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help
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Enables the virtual Etrax general port device (major 120, minor 6).
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It uses an I/O expander for the I2C-bus.
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config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
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int "Virtual GPIO interrupt pin on PA pin"
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range 0 7
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depends on ETRAX_VIRTUAL_GPIO
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help
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The pin to use on PA for virtual gpio interrupt.
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config ETRAX_PA_CHANGEABLE_DIR
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hex "PA user changeable dir mask"
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depends on ETRAX_GPIO
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default "0x00" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PA that a
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user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0 here, but it depends on your hardware.
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config ETRAX_PA_CHANGEABLE_BITS
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hex "PA user changeable bits mask"
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depends on ETRAX_GPIO
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default "0x00" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PA
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_PB_CHANGEABLE_DIR
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hex "PB user changeable dir mask"
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depends on ETRAX_GPIO
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default "0x00000" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PB
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that a user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0 here, but it depends on your hardware.
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config ETRAX_PB_CHANGEABLE_BITS
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hex "PB user changeable bits mask"
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depends on ETRAX_GPIO
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default "0x00000" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PB
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_PC_CHANGEABLE_DIR
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hex "PC user changeable dir mask"
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depends on ETRAX_GPIO
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default "0x00000" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PC
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that a user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0 here, but it depends on your hardware.
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config ETRAX_PC_CHANGEABLE_BITS
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hex "PC user changeable bits mask"
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depends on ETRAX_GPIO
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default "0x00000" if ETRAXFS
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default "0x00000000" if !ETRAXFS
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help
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This is a bitmask with information of what bits in PC
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_PD_CHANGEABLE_DIR
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hex "PD user changeable dir mask"
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depends on ETRAX_GPIO && ETRAXFS
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default "0x00000"
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help
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This is a bitmask with information of what bits in PD
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that a user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0x00000 here, but it depends on your hardware.
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config ETRAX_PD_CHANGEABLE_BITS
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hex "PD user changeable bits mask"
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depends on ETRAX_GPIO && ETRAXFS
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default "0x00000"
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help
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This is a bitmask (18 bits) with information of what bits in PD
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_PE_CHANGEABLE_DIR
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hex "PE user changeable dir mask"
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depends on ETRAX_GPIO && ETRAXFS
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default "0x00000"
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help
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This is a bitmask (18 bits) with information of what bits in PE
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that a user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0x00000 here, but it depends on your hardware.
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config ETRAX_PE_CHANGEABLE_BITS
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hex "PE user changeable bits mask"
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depends on ETRAX_GPIO && ETRAXFS
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default "0x00000"
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help
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This is a bitmask (18 bits) with information of what bits in PE
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_PV_CHANGEABLE_DIR
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hex "PV user changeable dir mask"
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depends on ETRAX_VIRTUAL_GPIO
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default "0x0000"
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help
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This is a bitmask (16 bits) with information of what bits in PV
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that a user can change direction on using ioctl's.
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Bit set = changeable.
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You probably want 0x0000 here, but it depends on your hardware.
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config ETRAX_PV_CHANGEABLE_BITS
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hex "PV user changeable bits mask"
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depends on ETRAX_VIRTUAL_GPIO
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default "0x0000"
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help
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This is a bitmask (16 bits) with information of what bits in PV
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that a user can change the value on using ioctl's.
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Bit set = changeable.
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config ETRAX_CARDBUS
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bool "Cardbus support"
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depends on ETRAX_ARCH_V32
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@@ -3,4 +3,3 @@
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#
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obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
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obj-$(CONFIG_ETRAX_GPIO) += gpio.o
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File diff suppressed because it is too large
Load Diff
@@ -3,4 +3,3 @@
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#
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obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
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obj-$(CONFIG_ETRAX_GPIO) += gpio.o
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File diff suppressed because it is too large
Load Diff
@@ -3,7 +3,6 @@
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#include <arch/dma.h>
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#include <arch/intmem.h>
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#include <mach/pinmux.h>
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#include <arch/io.h>
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/* Functions for allocating DMA channels */
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EXPORT_SYMBOL(crisv32_request_dma);
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@@ -20,8 +19,6 @@ EXPORT_SYMBOL(crisv32_pinmux_alloc);
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EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
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EXPORT_SYMBOL(crisv32_pinmux_dealloc);
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EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
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EXPORT_SYMBOL(crisv32_io_get_name);
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EXPORT_SYMBOL(crisv32_io_get);
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/* Functions masking/unmasking interrupts */
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EXPORT_SYMBOL(crisv32_mask_irq);
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@@ -2,7 +2,7 @@
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# Makefile for the linux kernel.
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#
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obj-y := dma.o pinmux.o io.o arbiter.o
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obj-y := dma.o pinmux.o arbiter.o
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clean:
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@@ -1,149 +0,0 @@
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/*
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* Helper functions for I/O pins.
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*
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* Copyright (c) 2005-2007 Axis Communications AB.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/ctype.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <mach/pinmux.h>
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#include <hwregs/gio_defs.h>
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struct crisv32_ioport crisv32_ioports[] = {
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
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32
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
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32
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},
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{
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
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(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
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(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
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16
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},
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};
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#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
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struct crisv32_iopin crisv32_led_net0_green;
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struct crisv32_iopin crisv32_led_net0_red;
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struct crisv32_iopin crisv32_led2_green;
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struct crisv32_iopin crisv32_led2_red;
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struct crisv32_iopin crisv32_led3_green;
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struct crisv32_iopin crisv32_led3_red;
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/* Dummy port used when green LED and red LED is on the same bit */
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static unsigned long io_dummy;
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static struct crisv32_ioport dummy_port = {
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&io_dummy,
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&io_dummy,
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&io_dummy,
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32
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};
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static struct crisv32_iopin dummy_led = {
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&dummy_port,
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0
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};
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static int __init crisv32_io_init(void)
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{
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int ret = 0;
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u32 i;
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/* Locks *should* be dynamically initialized. */
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for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
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spin_lock_init(&crisv32_ioports[i].lock);
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spin_lock_init(&dummy_port.lock);
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/* Initialize LEDs */
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#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
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ret += crisv32_io_get_name(&crisv32_led_net0_green,
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CONFIG_ETRAX_LED_G_NET0);
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crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
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if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
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ret += crisv32_io_get_name(&crisv32_led_net0_red,
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CONFIG_ETRAX_LED_R_NET0);
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crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
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} else
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crisv32_led_net0_red = dummy_led;
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#endif
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ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
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ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
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ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
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ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
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crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
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crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
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return ret;
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}
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__initcall(crisv32_io_init);
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int crisv32_io_get(struct crisv32_iopin *iopin,
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unsigned int port, unsigned int pin)
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{
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if (port > NBR_OF_PORTS)
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return -EINVAL;
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if (port > crisv32_ioports[port].pin_count)
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return -EINVAL;
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iopin->bit = 1 << pin;
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iopin->port = &crisv32_ioports[port];
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if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
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return -EIO;
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return 0;
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}
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int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
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{
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int port;
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int pin;
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if (toupper(*name) == 'P')
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name++;
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if (toupper(*name) < 'A' || toupper(*name) > 'E')
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return -EINVAL;
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port = toupper(*name) - 'A';
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name++;
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pin = simple_strtoul(name, NULL, 10);
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if (pin < 0 || pin > crisv32_ioports[port].pin_count)
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return -EINVAL;
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iopin->bit = 1 << pin;
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iopin->port = &crisv32_ioports[port];
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if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
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return -EIO;
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return 0;
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}
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#ifdef CONFIG_PCI
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/* PCI I/O access stuff */
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struct cris_io_operations *cris_iops = NULL;
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EXPORT_SYMBOL(cris_iops);
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#endif
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@@ -2,7 +2,7 @@
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := dma.o pinmux.o io.o arbiter.o
|
||||
obj-y := dma.o pinmux.o arbiter.o
|
||||
|
||||
clean:
|
||||
|
||||
|
||||
@@ -1,191 +0,0 @@
|
||||
/*
|
||||
* Helper functions for I/O pins.
|
||||
*
|
||||
* Copyright (c) 2004-2007 Axis Communications AB.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
|
||||
#ifndef DEBUG
|
||||
#define DEBUG(x)
|
||||
#endif
|
||||
|
||||
struct crisv32_ioport crisv32_ioports[] = {
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
|
||||
8
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
|
||||
18
|
||||
},
|
||||
{
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
|
||||
(unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
|
||||
18
|
||||
}
|
||||
};
|
||||
|
||||
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
|
||||
|
||||
struct crisv32_iopin crisv32_led_net0_green;
|
||||
struct crisv32_iopin crisv32_led_net0_red;
|
||||
struct crisv32_iopin crisv32_led_net1_green;
|
||||
struct crisv32_iopin crisv32_led_net1_red;
|
||||
struct crisv32_iopin crisv32_led2_green;
|
||||
struct crisv32_iopin crisv32_led2_red;
|
||||
struct crisv32_iopin crisv32_led3_green;
|
||||
struct crisv32_iopin crisv32_led3_red;
|
||||
|
||||
/* Dummy port used when green LED and red LED is on the same bit */
|
||||
static unsigned long io_dummy;
|
||||
static struct crisv32_ioport dummy_port = {
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
&io_dummy,
|
||||
18
|
||||
};
|
||||
static struct crisv32_iopin dummy_led = {
|
||||
&dummy_port,
|
||||
0
|
||||
};
|
||||
|
||||
static int __init crisv32_io_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
u32 i;
|
||||
|
||||
/* Locks *should* be dynamically initialized. */
|
||||
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
|
||||
spin_lock_init(&crisv32_ioports[i].lock);
|
||||
spin_lock_init(&dummy_port.lock);
|
||||
|
||||
/* Initialize LEDs */
|
||||
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net0_green,
|
||||
CONFIG_ETRAX_LED_G_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
|
||||
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net0_red,
|
||||
CONFIG_ETRAX_LED_R_NET0);
|
||||
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
|
||||
} else
|
||||
crisv32_led_net0_red = dummy_led;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
|
||||
ret +=
|
||||
crisv32_io_get_name(&crisv32_led_net1_green,
|
||||
CONFIG_ETRAX_LED_G_NET1);
|
||||
crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
|
||||
if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
|
||||
crisv32_io_get_name(&crisv32_led_net1_red,
|
||||
CONFIG_ETRAX_LED_R_NET1);
|
||||
crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
|
||||
} else
|
||||
crisv32_led_net1_red = dummy_led;
|
||||
#endif
|
||||
|
||||
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
|
||||
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
|
||||
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
|
||||
|
||||
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
|
||||
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
__initcall(crisv32_io_init);
|
||||
|
||||
int crisv32_io_get(struct crisv32_iopin *iopin,
|
||||
unsigned int port, unsigned int pin)
|
||||
{
|
||||
if (port > NBR_OF_PORTS)
|
||||
return -EINVAL;
|
||||
if (port > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
|
||||
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
|
||||
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
|
||||
pin, port));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
|
||||
{
|
||||
int port;
|
||||
int pin;
|
||||
|
||||
if (toupper(*name) == 'P')
|
||||
name++;
|
||||
|
||||
if (toupper(*name) < 'A' || toupper(*name) > 'E')
|
||||
return -EINVAL;
|
||||
|
||||
port = toupper(*name) - 'A';
|
||||
name++;
|
||||
pin = simple_strtoul(name, NULL, 10);
|
||||
|
||||
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
|
||||
return -EINVAL;
|
||||
|
||||
iopin->bit = 1 << pin;
|
||||
iopin->port = &crisv32_ioports[port];
|
||||
|
||||
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
|
||||
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
|
||||
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
|
||||
return -EIO;
|
||||
|
||||
DEBUG(printk(KERN_DEBUG
|
||||
"crisv32_io_get_name: Allocated pin %d on port %d\n",
|
||||
pin, port));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI I/O access stuff */
|
||||
struct cris_io_operations *cris_iops = NULL;
|
||||
EXPORT_SYMBOL(cris_iops);
|
||||
#endif
|
||||
@@ -1,140 +0,0 @@
|
||||
#ifndef _ASM_ARCH_CRIS_IO_H
|
||||
#define _ASM_ARCH_CRIS_IO_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <hwregs/reg_map.h>
|
||||
#include <hwregs/reg_rdwr.h>
|
||||
#include <hwregs/gio_defs.h>
|
||||
|
||||
enum crisv32_io_dir
|
||||
{
|
||||
crisv32_io_dir_in = 0,
|
||||
crisv32_io_dir_out = 1
|
||||
};
|
||||
|
||||
struct crisv32_ioport
|
||||
{
|
||||
volatile unsigned long *oe;
|
||||
volatile unsigned long *data;
|
||||
volatile unsigned long *data_in;
|
||||
unsigned int pin_count;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct crisv32_iopin
|
||||
{
|
||||
struct crisv32_ioport* port;
|
||||
int bit;
|
||||
};
|
||||
|
||||
extern struct crisv32_ioport crisv32_ioports[];
|
||||
|
||||
extern struct crisv32_iopin crisv32_led1_green;
|
||||
extern struct crisv32_iopin crisv32_led1_red;
|
||||
extern struct crisv32_iopin crisv32_led2_green;
|
||||
extern struct crisv32_iopin crisv32_led2_red;
|
||||
extern struct crisv32_iopin crisv32_led3_green;
|
||||
extern struct crisv32_iopin crisv32_led3_red;
|
||||
|
||||
extern struct crisv32_iopin crisv32_led_net0_green;
|
||||
extern struct crisv32_iopin crisv32_led_net0_red;
|
||||
extern struct crisv32_iopin crisv32_led_net1_green;
|
||||
extern struct crisv32_iopin crisv32_led_net1_red;
|
||||
|
||||
static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
|
||||
{
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&iopin->port->lock, flags);
|
||||
|
||||
if (iopin->port->data) {
|
||||
if (val)
|
||||
*iopin->port->data |= iopin->bit;
|
||||
else
|
||||
*iopin->port->data &= ~iopin->bit;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iopin->port->lock, flags);
|
||||
}
|
||||
|
||||
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
|
||||
enum crisv32_io_dir dir)
|
||||
{
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&iopin->port->lock, flags);
|
||||
|
||||
if (iopin->port->oe) {
|
||||
if (dir == crisv32_io_dir_in)
|
||||
*iopin->port->oe &= ~iopin->bit;
|
||||
else
|
||||
*iopin->port->oe |= iopin->bit;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iopin->port->lock, flags);
|
||||
}
|
||||
|
||||
static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
|
||||
{
|
||||
return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
|
||||
}
|
||||
|
||||
int crisv32_io_get(struct crisv32_iopin* iopin,
|
||||
unsigned int port, unsigned int pin);
|
||||
int crisv32_io_get_name(struct crisv32_iopin* iopin,
|
||||
const char *name);
|
||||
|
||||
#define CRIS_LED_OFF 0x00
|
||||
#define CRIS_LED_GREEN 0x01
|
||||
#define CRIS_LED_RED 0x02
|
||||
#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
|
||||
|
||||
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
|
||||
#define CRIS_LED_NETWORK_GRP0_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
#else
|
||||
#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
|
||||
#endif
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led_net0_green, !(x));
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led_net0_red, !(x));
|
||||
|
||||
#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
|
||||
#define CRIS_LED_NETWORK_GRP1_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
#else
|
||||
#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
|
||||
#endif
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led_net1_green, !(x));
|
||||
|
||||
#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led_net1_red, !(x));
|
||||
|
||||
#define CRIS_LED_ACTIVE_SET(x) \
|
||||
do { \
|
||||
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
|
||||
CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
|
||||
} while (0)
|
||||
|
||||
#define CRIS_LED_ACTIVE_SET_G(x) \
|
||||
crisv32_io_set(&crisv32_led2_green, !(x));
|
||||
#define CRIS_LED_ACTIVE_SET_R(x) \
|
||||
crisv32_io_set(&crisv32_led2_red, !(x));
|
||||
#define CRIS_LED_DISK_WRITE(x) \
|
||||
do{\
|
||||
crisv32_io_set(&crisv32_led3_green, !(x)); \
|
||||
crisv32_io_set(&crisv32_led3_red, !(x)); \
|
||||
}while(0)
|
||||
#define CRIS_LED_DISK_READ(x) \
|
||||
crisv32_io_set(&crisv32_led3_green, !(x));
|
||||
|
||||
#endif
|
||||
@@ -2,7 +2,9 @@
|
||||
#define _ASM_CRIS_IO_H
|
||||
|
||||
#include <asm/page.h> /* for __va, __pa */
|
||||
#ifdef CONFIG_ETRAX_ARCH_V10
|
||||
#include <arch/io.h>
|
||||
#endif
|
||||
#include <asm-generic/iomap.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user