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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless into for-davem
This commit is contained in:
John W. Linville
@@ -1351,6 +1351,14 @@ W: http://wireless.kernel.org/en/users/Drivers/ath9k
|
||||
S: Supported
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F: drivers/net/wireless/ath/ath9k/
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||||
|
||||
WILOCITY WIL6210 WIRELESS DRIVER
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||||
M: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
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||||
L: linux-wireless@vger.kernel.org
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L: wil6210@qca.qualcomm.com
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S: Supported
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||||
W: http://wireless.kernel.org/en/users/Drivers/wil6210
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F: drivers/net/wireless/ath/wil6210/
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CARL9170 LINUX COMMUNITY WIRELESS DRIVER
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M: Christian Lamparter <chunkeey@googlemail.com>
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L: linux-wireless@vger.kernel.org
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@@ -30,5 +30,6 @@ source "drivers/net/wireless/ath/ath9k/Kconfig"
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source "drivers/net/wireless/ath/carl9170/Kconfig"
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source "drivers/net/wireless/ath/ath6kl/Kconfig"
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source "drivers/net/wireless/ath/ar5523/Kconfig"
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source "drivers/net/wireless/ath/wil6210/Kconfig"
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endif
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@@ -3,6 +3,7 @@ obj-$(CONFIG_ATH9K_HW) += ath9k/
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obj-$(CONFIG_CARL9170) += carl9170/
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obj-$(CONFIG_ATH6KL) += ath6kl/
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obj-$(CONFIG_AR5523) += ar5523/
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obj-$(CONFIG_WIL6210) += wil6210/
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obj-$(CONFIG_ATH_COMMON) += ath.o
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@@ -0,0 +1,29 @@
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config WIL6210
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tristate "Wilocity 60g WiFi card wil6210 support"
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depends on CFG80211
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depends on PCI
|
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default n
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---help---
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This module adds support for wireless adapter based on
|
||||
wil6210 chip by Wilocity. It supports operation on the
|
||||
60 GHz band, covered by the IEEE802.11ad standard.
|
||||
|
||||
http://wireless.kernel.org/en/users/Drivers/wil6210
|
||||
|
||||
If you choose to build it as a module, it will be called
|
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wil6210
|
||||
|
||||
config WIL6210_ISR_COR
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bool "Use Clear-On-Read mode for ISR registers for wil6210"
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depends on WIL6210
|
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default y
|
||||
---help---
|
||||
ISR registers on wil6210 chip may operate in either
|
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COR (Clear-On-Read) or W1C (Write-1-to-Clear) mode.
|
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For production code, use COR (say y); is default since
|
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it saves extra target transaction;
|
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For ISR debug, use W1C (say n); is allows to monitor ISR
|
||||
registers with debugfs. If COR were used, ISR would
|
||||
self-clear when accessed for debug purposes, it makes
|
||||
such monitoring impossible.
|
||||
Say y unless you debug interrupts
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||||
@@ -0,0 +1,13 @@
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obj-$(CONFIG_WIL6210) += wil6210.o
|
||||
|
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wil6210-objs := main.o
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wil6210-objs += netdev.o
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wil6210-objs += cfg80211.o
|
||||
wil6210-objs += pcie_bus.o
|
||||
wil6210-objs += debugfs.o
|
||||
wil6210-objs += wmi.o
|
||||
wil6210-objs += interrupt.o
|
||||
wil6210-objs += txrx.o
|
||||
|
||||
subdir-ccflags-y += -Werror
|
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subdir-ccflags-y += -D__CHECK_ENDIAN__
|
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,30 @@
|
||||
#ifndef WIL_DBG_HEXDUMP_H_
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#define WIL_DBG_HEXDUMP_H_
|
||||
|
||||
#if defined(CONFIG_DYNAMIC_DEBUG)
|
||||
#define wil_dynamic_hex_dump(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii) \
|
||||
do { \
|
||||
DEFINE_DYNAMIC_DEBUG_METADATA(descriptor, \
|
||||
__builtin_constant_p(prefix_str) ? prefix_str : "hexdump");\
|
||||
if (unlikely(descriptor.flags & _DPRINTK_FLAGS_PRINT)) \
|
||||
print_hex_dump(KERN_DEBUG, prefix_str, \
|
||||
prefix_type, rowsize, groupsize, \
|
||||
buf, len, ascii); \
|
||||
} while (0)
|
||||
|
||||
#define wil_print_hex_dump_debug(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii) \
|
||||
wil_dynamic_hex_dump(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii)
|
||||
|
||||
#define print_hex_dump_bytes(prefix_str, prefix_type, buf, len) \
|
||||
wil_dynamic_hex_dump(prefix_str, prefix_type, 16, 1, buf, len, true)
|
||||
#else /* defined(CONFIG_DYNAMIC_DEBUG) */
|
||||
#define wil_print_hex_dump_debug(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii) \
|
||||
print_hex_dump(KERN_DEBUG, prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii)
|
||||
#endif /* defined(CONFIG_DYNAMIC_DEBUG) */
|
||||
|
||||
#endif /* WIL_DBG_HEXDUMP_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,471 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
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||||
|
||||
#include "wil6210.h"
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||||
|
||||
/**
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||||
* Theory of operation:
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*
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* There is ISR pseudo-cause register,
|
||||
* dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
|
||||
* Its bits represents OR'ed bits from 3 real ISR registers:
|
||||
* TX, RX, and MISC.
|
||||
*
|
||||
* Registers may be configured to either "write 1 to clear" or
|
||||
* "clear on read" mode
|
||||
*
|
||||
* When handling interrupt, one have to mask/unmask interrupts for the
|
||||
* real ISR registers, or hardware may malfunction.
|
||||
*
|
||||
*/
|
||||
|
||||
#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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||||
#define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
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||||
#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
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||||
BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
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||||
#define WIL6210_IMC_MISC (ISR_MISC_FW_READY | ISR_MISC_MBOX_EVT)
|
||||
|
||||
#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
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||||
BIT_DMA_PSEUDO_CAUSE_TX | \
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||||
BIT_DMA_PSEUDO_CAUSE_MISC))
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||||
|
||||
#if defined(CONFIG_WIL6210_ISR_COR)
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||||
/* configure to Clear-On-Read mode */
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||||
#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
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||||
|
||||
static inline void wil_icr_clear(u32 x, void __iomem *addr)
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||||
{
|
||||
|
||||
}
|
||||
#else /* defined(CONFIG_WIL6210_ISR_COR) */
|
||||
/* configure to Write-1-to-Clear mode */
|
||||
#define WIL_ICR_ICC_VALUE (0UL)
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||||
|
||||
static inline void wil_icr_clear(u32 x, void __iomem *addr)
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||||
{
|
||||
iowrite32(x, addr);
|
||||
}
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||||
#endif /* defined(CONFIG_WIL6210_ISR_COR) */
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||||
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static inline u32 wil_ioread32_and_clear(void __iomem *addr)
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||||
{
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u32 x = ioread32(addr);
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||||
|
||||
wil_icr_clear(x, addr);
|
||||
|
||||
return x;
|
||||
}
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||||
|
||||
static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
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offsetof(struct RGF_ICR, IMS));
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}
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|
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static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
|
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, IMS));
|
||||
}
|
||||
|
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static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, IMS));
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}
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static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
|
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{
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wil_dbg_IRQ(wil, "%s()\n", __func__);
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
|
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HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
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|
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clear_bit(wil_status_irqen, &wil->status);
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}
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||||
static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IMC_TX, wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, IMC));
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}
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static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
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{
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||||
iowrite32(WIL6210_IMC_RX, wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, IMC));
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||||
}
|
||||
|
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static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IMC_MISC, wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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||||
offsetof(struct RGF_ICR, IMC));
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||||
}
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||||
|
||||
static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
|
||||
{
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||||
wil_dbg_IRQ(wil, "%s()\n", __func__);
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||||
set_bit(wil_status_irqen, &wil->status);
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||||
|
||||
iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
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HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
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||||
}
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|
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void wil6210_disable_irq(struct wil6210_priv *wil)
|
||||
{
|
||||
wil_dbg_IRQ(wil, "%s()\n", __func__);
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||||
|
||||
wil6210_mask_irq_tx(wil);
|
||||
wil6210_mask_irq_rx(wil);
|
||||
wil6210_mask_irq_misc(wil);
|
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wil6210_mask_irq_pseudo(wil);
|
||||
}
|
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|
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void wil6210_enable_irq(struct wil6210_priv *wil)
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{
|
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wil_dbg_IRQ(wil, "%s()\n", __func__);
|
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||||
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICC));
|
||||
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
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offsetof(struct RGF_ICR, ICC));
|
||||
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
|
||||
offsetof(struct RGF_ICR, ICC));
|
||||
|
||||
wil6210_unmask_irq_pseudo(wil);
|
||||
wil6210_unmask_irq_tx(wil);
|
||||
wil6210_unmask_irq_rx(wil);
|
||||
wil6210_unmask_irq_misc(wil);
|
||||
}
|
||||
|
||||
static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
|
||||
{
|
||||
struct wil6210_priv *wil = cookie;
|
||||
u32 isr = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
|
||||
wil_dbg_IRQ(wil, "ISR RX 0x%08x\n", isr);
|
||||
|
||||
if (!isr) {
|
||||
wil_err(wil, "spurious IRQ: RX\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
wil6210_mask_irq_rx(wil);
|
||||
|
||||
if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
|
||||
wil_dbg_IRQ(wil, "RX done\n");
|
||||
isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
|
||||
wil_rx_handle(wil);
|
||||
}
|
||||
|
||||
if (isr)
|
||||
wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
|
||||
|
||||
wil6210_unmask_irq_rx(wil);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
|
||||
{
|
||||
struct wil6210_priv *wil = cookie;
|
||||
u32 isr = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
|
||||
wil_dbg_IRQ(wil, "ISR TX 0x%08x\n", isr);
|
||||
|
||||
if (!isr) {
|
||||
wil_err(wil, "spurious IRQ: TX\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
wil6210_mask_irq_tx(wil);
|
||||
|
||||
if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
|
||||
uint i;
|
||||
wil_dbg_IRQ(wil, "TX done\n");
|
||||
isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
|
||||
for (i = 0; i < 24; i++) {
|
||||
u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
|
||||
if (isr & mask) {
|
||||
isr &= ~mask;
|
||||
wil_dbg_IRQ(wil, "TX done(%i)\n", i);
|
||||
wil_tx_complete(wil, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (isr)
|
||||
wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
|
||||
|
||||
wil6210_unmask_irq_tx(wil);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
|
||||
{
|
||||
struct wil6210_priv *wil = cookie;
|
||||
u32 isr = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_MISC_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
|
||||
wil_dbg_IRQ(wil, "ISR MISC 0x%08x\n", isr);
|
||||
|
||||
if (!isr) {
|
||||
wil_err(wil, "spurious IRQ: MISC\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
wil6210_mask_irq_misc(wil);
|
||||
|
||||
if (isr & ISR_MISC_FW_READY) {
|
||||
wil_dbg_IRQ(wil, "IRQ: FW ready\n");
|
||||
/**
|
||||
* Actual FW ready indicated by the
|
||||
* WMI_FW_READY_EVENTID
|
||||
*/
|
||||
isr &= ~ISR_MISC_FW_READY;
|
||||
}
|
||||
|
||||
wil->isr_misc = isr;
|
||||
|
||||
if (isr) {
|
||||
return IRQ_WAKE_THREAD;
|
||||
} else {
|
||||
wil6210_unmask_irq_misc(wil);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
|
||||
{
|
||||
struct wil6210_priv *wil = cookie;
|
||||
u32 isr = wil->isr_misc;
|
||||
|
||||
wil_dbg_IRQ(wil, "Thread ISR MISC 0x%08x\n", isr);
|
||||
|
||||
if (isr & ISR_MISC_MBOX_EVT) {
|
||||
wil_dbg_IRQ(wil, "MBOX event\n");
|
||||
wmi_recv_cmd(wil);
|
||||
isr &= ~ISR_MISC_MBOX_EVT;
|
||||
}
|
||||
|
||||
if (isr)
|
||||
wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
|
||||
|
||||
wil->isr_misc = 0;
|
||||
|
||||
wil6210_unmask_irq_misc(wil);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* thread IRQ handler
|
||||
*/
|
||||
static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
|
||||
{
|
||||
struct wil6210_priv *wil = cookie;
|
||||
|
||||
wil_dbg_IRQ(wil, "Thread IRQ\n");
|
||||
/* Discover real IRQ cause */
|
||||
if (wil->isr_misc)
|
||||
wil6210_irq_misc_thread(irq, cookie);
|
||||
|
||||
wil6210_unmask_irq_pseudo(wil);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* DEBUG
|
||||
* There is subtle bug in hardware that causes IRQ to raise when it should be
|
||||
* masked. It is quite rare and hard to debug.
|
||||
*
|
||||
* Catch irq issue if it happens and print all I can.
|
||||
*/
|
||||
static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
|
||||
{
|
||||
if (!test_bit(wil_status_irqen, &wil->status)) {
|
||||
u32 icm_rx = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICM));
|
||||
u32 icr_rx = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
u32 imv_rx = ioread32(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_RX_ICR) +
|
||||
offsetof(struct RGF_ICR, IMV));
|
||||
u32 icm_tx = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICM));
|
||||
u32 icr_tx = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
u32 imv_tx = ioread32(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_TX_ICR) +
|
||||
offsetof(struct RGF_ICR, IMV));
|
||||
u32 icm_misc = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_MISC_ICR) +
|
||||
offsetof(struct RGF_ICR, ICM));
|
||||
u32 icr_misc = wil_ioread32_and_clear(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_MISC_ICR) +
|
||||
offsetof(struct RGF_ICR, ICR));
|
||||
u32 imv_misc = ioread32(wil->csr +
|
||||
HOSTADDR(RGF_DMA_EP_MISC_ICR) +
|
||||
offsetof(struct RGF_ICR, IMV));
|
||||
wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
|
||||
"Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
|
||||
"Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
|
||||
"Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
|
||||
pseudo_cause,
|
||||
icm_rx, icr_rx, imv_rx,
|
||||
icm_tx, icr_tx, imv_tx,
|
||||
icm_misc, icr_misc, imv_misc);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t wil6210_hardirq(int irq, void *cookie)
|
||||
{
|
||||
irqreturn_t rc = IRQ_HANDLED;
|
||||
struct wil6210_priv *wil = cookie;
|
||||
u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
|
||||
|
||||
/**
|
||||
* pseudo_cause is Clear-On-Read, no need to ACK
|
||||
*/
|
||||
if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
|
||||
return IRQ_NONE;
|
||||
|
||||
/* FIXME: IRQ mask debug */
|
||||
if (wil6210_debug_irq_mask(wil, pseudo_cause))
|
||||
return IRQ_NONE;
|
||||
|
||||
wil6210_mask_irq_pseudo(wil);
|
||||
|
||||
/* Discover real IRQ cause
|
||||
* There are 2 possible phases for every IRQ:
|
||||
* - hard IRQ handler called right here
|
||||
* - threaded handler called later
|
||||
*
|
||||
* Hard IRQ handler reads and clears ISR.
|
||||
*
|
||||
* If threaded handler requested, hard IRQ handler
|
||||
* returns IRQ_WAKE_THREAD and saves ISR register value
|
||||
* for the threaded handler use.
|
||||
*
|
||||
* voting for wake thread - need at least 1 vote
|
||||
*/
|
||||
if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
|
||||
(wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
|
||||
rc = IRQ_WAKE_THREAD;
|
||||
|
||||
if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
|
||||
(wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
|
||||
rc = IRQ_WAKE_THREAD;
|
||||
|
||||
if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
|
||||
(wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
|
||||
rc = IRQ_WAKE_THREAD;
|
||||
|
||||
/* if thread is requested, it will unmask IRQ */
|
||||
if (rc != IRQ_WAKE_THREAD)
|
||||
wil6210_unmask_irq_pseudo(wil);
|
||||
|
||||
wil_dbg_IRQ(wil, "Hard IRQ 0x%08x\n", pseudo_cause);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
|
||||
{
|
||||
int rc;
|
||||
/*
|
||||
* IRQ's are in the following order:
|
||||
* - Tx
|
||||
* - Rx
|
||||
* - Misc
|
||||
*/
|
||||
|
||||
rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
|
||||
WIL_NAME"_tx", wil);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
|
||||
WIL_NAME"_rx", wil);
|
||||
if (rc)
|
||||
goto free0;
|
||||
|
||||
rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
|
||||
wil6210_irq_misc_thread,
|
||||
IRQF_SHARED, WIL_NAME"_misc", wil);
|
||||
if (rc)
|
||||
goto free1;
|
||||
|
||||
return 0;
|
||||
/* error branch */
|
||||
free1:
|
||||
free_irq(irq + 1, wil);
|
||||
free0:
|
||||
free_irq(irq, wil);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
int wil6210_init_irq(struct wil6210_priv *wil, int irq)
|
||||
{
|
||||
int rc;
|
||||
if (wil->n_msi == 3)
|
||||
rc = wil6210_request_3msi(wil, irq);
|
||||
else
|
||||
rc = request_threaded_irq(irq, wil6210_hardirq,
|
||||
wil6210_thread_irq,
|
||||
wil->n_msi ? 0 : IRQF_SHARED,
|
||||
WIL_NAME, wil);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
wil6210_enable_irq(wil);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
|
||||
{
|
||||
wil6210_disable_irq(wil);
|
||||
free_irq(irq, wil);
|
||||
if (wil->n_msi == 3) {
|
||||
free_irq(irq + 1, wil);
|
||||
free_irq(irq + 2, wil);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,407 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ieee80211.h>
|
||||
#include <linux/wireless.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/if_arp.h>
|
||||
|
||||
#include "wil6210.h"
|
||||
|
||||
/*
|
||||
* Due to a hardware issue,
|
||||
* one has to read/write to/from NIC in 32-bit chunks;
|
||||
* regular memcpy_fromio and siblings will
|
||||
* not work on 64-bit platform - it uses 64-bit transactions
|
||||
*
|
||||
* Force 32-bit transactions to enable NIC on 64-bit platforms
|
||||
*
|
||||
* To avoid byte swap on big endian host, __raw_{read|write}l
|
||||
* should be used - {read|write}l would swap bytes to provide
|
||||
* little endian on PCI value in host endianness.
|
||||
*/
|
||||
void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
|
||||
size_t count)
|
||||
{
|
||||
u32 *d = dst;
|
||||
const volatile u32 __iomem *s = src;
|
||||
|
||||
/* size_t is unsigned, if (count%4 != 0) it will wrap */
|
||||
for (count += 4; count > 4; count -= 4)
|
||||
*d++ = __raw_readl(s++);
|
||||
}
|
||||
|
||||
void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
|
||||
size_t count)
|
||||
{
|
||||
volatile u32 __iomem *d = dst;
|
||||
const u32 *s = src;
|
||||
|
||||
for (count += 4; count > 4; count -= 4)
|
||||
__raw_writel(*s++, d++);
|
||||
}
|
||||
|
||||
static void _wil6210_disconnect(struct wil6210_priv *wil, void *bssid)
|
||||
{
|
||||
uint i;
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
struct wireless_dev *wdev = wil->wdev;
|
||||
|
||||
wil_dbg(wil, "%s()\n", __func__);
|
||||
|
||||
wil_link_off(wil);
|
||||
clear_bit(wil_status_fwconnected, &wil->status);
|
||||
|
||||
switch (wdev->sme_state) {
|
||||
case CFG80211_SME_CONNECTED:
|
||||
cfg80211_disconnected(ndev, WLAN_STATUS_UNSPECIFIED_FAILURE,
|
||||
NULL, 0, GFP_KERNEL);
|
||||
break;
|
||||
case CFG80211_SME_CONNECTING:
|
||||
cfg80211_connect_result(ndev, bssid, NULL, 0, NULL, 0,
|
||||
WLAN_STATUS_UNSPECIFIED_FAILURE,
|
||||
GFP_KERNEL);
|
||||
break;
|
||||
default:
|
||||
;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wil->vring_tx); i++)
|
||||
wil_vring_fini_tx(wil, i);
|
||||
}
|
||||
|
||||
static void wil_disconnect_worker(struct work_struct *work)
|
||||
{
|
||||
struct wil6210_priv *wil = container_of(work,
|
||||
struct wil6210_priv, disconnect_worker);
|
||||
|
||||
_wil6210_disconnect(wil, NULL);
|
||||
}
|
||||
|
||||
static void wil_connect_timer_fn(ulong x)
|
||||
{
|
||||
struct wil6210_priv *wil = (void *)x;
|
||||
|
||||
wil_dbg(wil, "Connect timeout\n");
|
||||
|
||||
/* reschedule to thread context - disconnect won't
|
||||
* run from atomic context
|
||||
*/
|
||||
schedule_work(&wil->disconnect_worker);
|
||||
}
|
||||
|
||||
int wil_priv_init(struct wil6210_priv *wil)
|
||||
{
|
||||
wil_dbg(wil, "%s()\n", __func__);
|
||||
|
||||
mutex_init(&wil->mutex);
|
||||
mutex_init(&wil->wmi_mutex);
|
||||
|
||||
init_completion(&wil->wmi_ready);
|
||||
|
||||
wil->pending_connect_cid = -1;
|
||||
setup_timer(&wil->connect_timer, wil_connect_timer_fn, (ulong)wil);
|
||||
|
||||
INIT_WORK(&wil->wmi_connect_worker, wmi_connect_worker);
|
||||
INIT_WORK(&wil->disconnect_worker, wil_disconnect_worker);
|
||||
INIT_WORK(&wil->wmi_event_worker, wmi_event_worker);
|
||||
|
||||
INIT_LIST_HEAD(&wil->pending_wmi_ev);
|
||||
spin_lock_init(&wil->wmi_ev_lock);
|
||||
|
||||
wil->wmi_wq = create_singlethread_workqueue(WIL_NAME"_wmi");
|
||||
if (!wil->wmi_wq)
|
||||
return -EAGAIN;
|
||||
|
||||
wil->wmi_wq_conn = create_singlethread_workqueue(WIL_NAME"_connect");
|
||||
if (!wil->wmi_wq_conn) {
|
||||
destroy_workqueue(wil->wmi_wq);
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* make shadow copy of registers that should not change on run time */
|
||||
wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
|
||||
sizeof(struct wil6210_mbox_ctl));
|
||||
wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
|
||||
wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wil6210_disconnect(struct wil6210_priv *wil, void *bssid)
|
||||
{
|
||||
del_timer_sync(&wil->connect_timer);
|
||||
_wil6210_disconnect(wil, bssid);
|
||||
}
|
||||
|
||||
void wil_priv_deinit(struct wil6210_priv *wil)
|
||||
{
|
||||
cancel_work_sync(&wil->disconnect_worker);
|
||||
wil6210_disconnect(wil, NULL);
|
||||
wmi_event_flush(wil);
|
||||
destroy_workqueue(wil->wmi_wq_conn);
|
||||
destroy_workqueue(wil->wmi_wq);
|
||||
}
|
||||
|
||||
static void wil_target_reset(struct wil6210_priv *wil)
|
||||
{
|
||||
wil_dbg(wil, "Resetting...\n");
|
||||
|
||||
/* register write */
|
||||
#define W(a, v) iowrite32(v, wil->csr + HOSTADDR(a))
|
||||
/* register set = read, OR, write */
|
||||
#define S(a, v) iowrite32(ioread32(wil->csr + HOSTADDR(a)) | v, \
|
||||
wil->csr + HOSTADDR(a))
|
||||
|
||||
/* hpal_perst_from_pad_src_n_mask */
|
||||
S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
|
||||
/* car_perst_rst_src_n_mask */
|
||||
S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(7));
|
||||
|
||||
W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
|
||||
W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
|
||||
|
||||
msleep(100);
|
||||
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000170);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FC00);
|
||||
|
||||
msleep(100);
|
||||
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
|
||||
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
|
||||
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
|
||||
|
||||
msleep(2000);
|
||||
|
||||
W(RGF_USER_USER_CPU_0, BIT(0)); /* user_cpu_man_de_rst */
|
||||
|
||||
msleep(2000);
|
||||
|
||||
wil_dbg(wil, "Reset completed\n");
|
||||
|
||||
#undef W
|
||||
#undef S
|
||||
}
|
||||
|
||||
void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r)
|
||||
{
|
||||
le32_to_cpus(&r->base);
|
||||
le16_to_cpus(&r->entry_size);
|
||||
le16_to_cpus(&r->size);
|
||||
le32_to_cpus(&r->tail);
|
||||
le32_to_cpus(&r->head);
|
||||
}
|
||||
|
||||
static int wil_wait_for_fw_ready(struct wil6210_priv *wil)
|
||||
{
|
||||
ulong to = msecs_to_jiffies(1000);
|
||||
ulong left = wait_for_completion_timeout(&wil->wmi_ready, to);
|
||||
if (0 == left) {
|
||||
wil_err(wil, "Firmware not ready\n");
|
||||
return -ETIME;
|
||||
} else {
|
||||
wil_dbg(wil, "FW ready after %d ms\n",
|
||||
jiffies_to_msecs(to-left));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We reset all the structures, and we reset the UMAC.
|
||||
* After calling this routine, you're expected to reload
|
||||
* the firmware.
|
||||
*/
|
||||
int wil_reset(struct wil6210_priv *wil)
|
||||
{
|
||||
int rc;
|
||||
|
||||
cancel_work_sync(&wil->disconnect_worker);
|
||||
wil6210_disconnect(wil, NULL);
|
||||
|
||||
wmi_event_flush(wil);
|
||||
|
||||
flush_workqueue(wil->wmi_wq);
|
||||
flush_workqueue(wil->wmi_wq_conn);
|
||||
|
||||
wil6210_disable_irq(wil);
|
||||
wil->status = 0;
|
||||
|
||||
/* TODO: put MAC in reset */
|
||||
wil_target_reset(wil);
|
||||
|
||||
/* init after reset */
|
||||
wil->pending_connect_cid = -1;
|
||||
INIT_COMPLETION(wil->wmi_ready);
|
||||
|
||||
/* make shadow copy of registers that should not change on run time */
|
||||
wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
|
||||
sizeof(struct wil6210_mbox_ctl));
|
||||
wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
|
||||
wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
|
||||
|
||||
/* TODO: release MAC reset */
|
||||
wil6210_enable_irq(wil);
|
||||
|
||||
/* we just started MAC, wait for FW ready */
|
||||
rc = wil_wait_for_fw_ready(wil);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
void wil_link_on(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
|
||||
wil_dbg(wil, "%s()\n", __func__);
|
||||
|
||||
netif_carrier_on(ndev);
|
||||
netif_tx_wake_all_queues(ndev);
|
||||
}
|
||||
|
||||
void wil_link_off(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
|
||||
wil_dbg(wil, "%s()\n", __func__);
|
||||
|
||||
netif_tx_stop_all_queues(ndev);
|
||||
netif_carrier_off(ndev);
|
||||
}
|
||||
|
||||
static int __wil_up(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
struct wireless_dev *wdev = wil->wdev;
|
||||
struct ieee80211_channel *channel = wdev->preset_chandef.chan;
|
||||
int rc;
|
||||
int bi;
|
||||
u16 wmi_nettype = wil_iftype_nl2wmi(wdev->iftype);
|
||||
|
||||
rc = wil_reset(wil);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* FIXME Firmware works now in PBSS mode(ToDS=0, FromDS=0) */
|
||||
wmi_nettype = wil_iftype_nl2wmi(NL80211_IFTYPE_ADHOC);
|
||||
switch (wdev->iftype) {
|
||||
case NL80211_IFTYPE_STATION:
|
||||
wil_dbg(wil, "type: STATION\n");
|
||||
bi = 0;
|
||||
ndev->type = ARPHRD_ETHER;
|
||||
break;
|
||||
case NL80211_IFTYPE_AP:
|
||||
wil_dbg(wil, "type: AP\n");
|
||||
bi = 100;
|
||||
ndev->type = ARPHRD_ETHER;
|
||||
break;
|
||||
case NL80211_IFTYPE_P2P_CLIENT:
|
||||
wil_dbg(wil, "type: P2P_CLIENT\n");
|
||||
bi = 0;
|
||||
ndev->type = ARPHRD_ETHER;
|
||||
break;
|
||||
case NL80211_IFTYPE_P2P_GO:
|
||||
wil_dbg(wil, "type: P2P_GO\n");
|
||||
bi = 100;
|
||||
ndev->type = ARPHRD_ETHER;
|
||||
break;
|
||||
case NL80211_IFTYPE_MONITOR:
|
||||
wil_dbg(wil, "type: Monitor\n");
|
||||
bi = 0;
|
||||
ndev->type = ARPHRD_IEEE80211_RADIOTAP;
|
||||
/* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_RADIOTAP ? */
|
||||
break;
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* Apply profile in the following order: */
|
||||
/* SSID and channel for the AP */
|
||||
switch (wdev->iftype) {
|
||||
case NL80211_IFTYPE_AP:
|
||||
case NL80211_IFTYPE_P2P_GO:
|
||||
if (wdev->ssid_len == 0) {
|
||||
wil_err(wil, "SSID not set\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
wmi_set_ssid(wil, wdev->ssid_len, wdev->ssid);
|
||||
if (channel)
|
||||
wmi_set_channel(wil, channel->hw_value);
|
||||
break;
|
||||
default:
|
||||
;
|
||||
}
|
||||
|
||||
/* MAC address - pre-requisite for other commands */
|
||||
wmi_set_mac_address(wil, ndev->dev_addr);
|
||||
|
||||
/* Set up beaconing if required. */
|
||||
rc = wmi_set_bcon(wil, bi, wmi_nettype);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Rx VRING. After MAC and beacon */
|
||||
wil_rx_init(wil);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wil_up(struct wil6210_priv *wil)
|
||||
{
|
||||
int rc;
|
||||
|
||||
mutex_lock(&wil->mutex);
|
||||
rc = __wil_up(wil);
|
||||
mutex_unlock(&wil->mutex);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __wil_down(struct wil6210_priv *wil)
|
||||
{
|
||||
if (wil->scan_request) {
|
||||
cfg80211_scan_done(wil->scan_request, true);
|
||||
wil->scan_request = NULL;
|
||||
}
|
||||
|
||||
wil6210_disconnect(wil, NULL);
|
||||
wil_rx_fini(wil);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wil_down(struct wil6210_priv *wil)
|
||||
{
|
||||
int rc;
|
||||
|
||||
mutex_lock(&wil->mutex);
|
||||
rc = __wil_down(wil);
|
||||
mutex_unlock(&wil->mutex);
|
||||
|
||||
return rc;
|
||||
}
|
||||
@@ -0,0 +1,157 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "wil6210.h"
|
||||
|
||||
static int wil_open(struct net_device *ndev)
|
||||
{
|
||||
struct wil6210_priv *wil = ndev_to_wil(ndev);
|
||||
|
||||
return wil_up(wil);
|
||||
}
|
||||
|
||||
static int wil_stop(struct net_device *ndev)
|
||||
{
|
||||
struct wil6210_priv *wil = ndev_to_wil(ndev);
|
||||
|
||||
return wil_down(wil);
|
||||
}
|
||||
|
||||
/*
|
||||
* AC to queue mapping
|
||||
*
|
||||
* AC_VO -> queue 3
|
||||
* AC_VI -> queue 2
|
||||
* AC_BE -> queue 1
|
||||
* AC_BK -> queue 0
|
||||
*/
|
||||
static u16 wil_select_queue(struct net_device *ndev, struct sk_buff *skb)
|
||||
{
|
||||
static const u16 wil_1d_to_queue[8] = { 1, 0, 0, 1, 2, 2, 3, 3 };
|
||||
struct wil6210_priv *wil = ndev_to_wil(ndev);
|
||||
u16 rc;
|
||||
|
||||
skb->priority = cfg80211_classify8021d(skb);
|
||||
|
||||
rc = wil_1d_to_queue[skb->priority];
|
||||
|
||||
wil_dbg_TXRX(wil, "%s() %d -> %d\n", __func__, (int)skb->priority,
|
||||
(int)rc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static const struct net_device_ops wil_netdev_ops = {
|
||||
.ndo_open = wil_open,
|
||||
.ndo_stop = wil_stop,
|
||||
.ndo_start_xmit = wil_start_xmit,
|
||||
.ndo_select_queue = wil_select_queue,
|
||||
.ndo_set_mac_address = eth_mac_addr,
|
||||
.ndo_validate_addr = eth_validate_addr,
|
||||
};
|
||||
|
||||
void *wil_if_alloc(struct device *dev, void __iomem *csr)
|
||||
{
|
||||
struct net_device *ndev;
|
||||
struct wireless_dev *wdev;
|
||||
struct wil6210_priv *wil;
|
||||
struct ieee80211_channel *ch;
|
||||
int rc = 0;
|
||||
|
||||
wdev = wil_cfg80211_init(dev);
|
||||
if (IS_ERR(wdev)) {
|
||||
dev_err(dev, "wil_cfg80211_init failed\n");
|
||||
return wdev;
|
||||
}
|
||||
|
||||
wil = wdev_to_wil(wdev);
|
||||
wil->csr = csr;
|
||||
wil->wdev = wdev;
|
||||
|
||||
rc = wil_priv_init(wil);
|
||||
if (rc) {
|
||||
dev_err(dev, "wil_priv_init failed\n");
|
||||
goto out_wdev;
|
||||
}
|
||||
|
||||
wdev->iftype = NL80211_IFTYPE_STATION; /* TODO */
|
||||
/* default monitor channel */
|
||||
ch = wdev->wiphy->bands[IEEE80211_BAND_60GHZ]->channels;
|
||||
cfg80211_chandef_create(&wdev->preset_chandef, ch, NL80211_CHAN_NO_HT);
|
||||
|
||||
ndev = alloc_netdev_mqs(0, "wlan%d", ether_setup, WIL6210_TX_QUEUES, 1);
|
||||
if (!ndev) {
|
||||
dev_err(dev, "alloc_netdev_mqs failed\n");
|
||||
rc = -ENOMEM;
|
||||
goto out_priv;
|
||||
}
|
||||
|
||||
ndev->netdev_ops = &wil_netdev_ops;
|
||||
ndev->ieee80211_ptr = wdev;
|
||||
SET_NETDEV_DEV(ndev, wiphy_dev(wdev->wiphy));
|
||||
wdev->netdev = ndev;
|
||||
|
||||
wil_link_off(wil);
|
||||
|
||||
return wil;
|
||||
|
||||
out_priv:
|
||||
wil_priv_deinit(wil);
|
||||
|
||||
out_wdev:
|
||||
wil_wdev_free(wil);
|
||||
|
||||
return ERR_PTR(rc);
|
||||
}
|
||||
|
||||
void wil_if_free(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
if (!ndev)
|
||||
return;
|
||||
|
||||
free_netdev(ndev);
|
||||
wil_priv_deinit(wil);
|
||||
wil_wdev_free(wil);
|
||||
}
|
||||
|
||||
int wil_if_add(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
int rc;
|
||||
|
||||
rc = register_netdev(ndev);
|
||||
if (rc < 0) {
|
||||
dev_err(&ndev->dev, "Failed to register netdev: %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
wil_link_off(wil);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wil_if_remove(struct wil6210_priv *wil)
|
||||
{
|
||||
struct net_device *ndev = wil_to_ndev(wil);
|
||||
|
||||
unregister_netdev(ndev);
|
||||
}
|
||||
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/moduleparam.h>
|
||||
|
||||
#include "wil6210.h"
|
||||
|
||||
static int use_msi = 1;
|
||||
module_param(use_msi, int, S_IRUGO);
|
||||
MODULE_PARM_DESC(use_msi,
|
||||
" Use MSI interrupt: "
|
||||
"0 - don't, 1 - (default) - single, or 3");
|
||||
|
||||
/* Bus ops */
|
||||
static int wil_if_pcie_enable(struct wil6210_priv *wil)
|
||||
{
|
||||
struct pci_dev *pdev = wil->pdev;
|
||||
int rc;
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
/*
|
||||
* how many MSI interrupts to request?
|
||||
*/
|
||||
switch (use_msi) {
|
||||
case 3:
|
||||
case 1:
|
||||
case 0:
|
||||
break;
|
||||
default:
|
||||
wil_err(wil, "Invalid use_msi=%d, default to 1\n",
|
||||
use_msi);
|
||||
use_msi = 1;
|
||||
}
|
||||
wil->n_msi = use_msi;
|
||||
if (wil->n_msi) {
|
||||
wil_dbg(wil, "Setup %d MSI interrupts\n", use_msi);
|
||||
rc = pci_enable_msi_block(pdev, wil->n_msi);
|
||||
if (rc && (wil->n_msi == 3)) {
|
||||
wil_err(wil, "3 MSI mode failed, try 1 MSI\n");
|
||||
wil->n_msi = 1;
|
||||
rc = pci_enable_msi_block(pdev, wil->n_msi);
|
||||
}
|
||||
if (rc) {
|
||||
wil_err(wil, "pci_enable_msi failed, use INTx\n");
|
||||
wil->n_msi = 0;
|
||||
}
|
||||
} else {
|
||||
wil_dbg(wil, "MSI interrupts disabled, use INTx\n");
|
||||
}
|
||||
|
||||
rc = wil6210_init_irq(wil, pdev->irq);
|
||||
if (rc)
|
||||
goto stop_master;
|
||||
|
||||
/* need reset here to obtain MAC */
|
||||
rc = wil_reset(wil);
|
||||
if (rc)
|
||||
goto release_irq;
|
||||
|
||||
return 0;
|
||||
|
||||
release_irq:
|
||||
wil6210_fini_irq(wil, pdev->irq);
|
||||
/* safe to call if no MSI */
|
||||
pci_disable_msi(pdev);
|
||||
stop_master:
|
||||
pci_clear_master(pdev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int wil_if_pcie_disable(struct wil6210_priv *wil)
|
||||
{
|
||||
struct pci_dev *pdev = wil->pdev;
|
||||
|
||||
pci_clear_master(pdev);
|
||||
/* disable and release IRQ */
|
||||
wil6210_fini_irq(wil, pdev->irq);
|
||||
/* safe to call if no MSI */
|
||||
pci_disable_msi(pdev);
|
||||
/* TODO: disable HW */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wil_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
struct wil6210_priv *wil;
|
||||
struct device *dev = &pdev->dev;
|
||||
void __iomem *csr;
|
||||
int rc;
|
||||
|
||||
/* check HW */
|
||||
dev_info(&pdev->dev, WIL_NAME " device found [%04x:%04x] (rev %x)\n",
|
||||
(int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
|
||||
|
||||
if (pci_resource_len(pdev, 0) != WIL6210_MEM_SIZE) {
|
||||
dev_err(&pdev->dev, "Not " WIL_NAME "? "
|
||||
"BAR0 size is %lu while expecting %lu\n",
|
||||
(ulong)pci_resource_len(pdev, 0), WIL6210_MEM_SIZE);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "pci_enable_device failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
/* rollback to err_disable_pdev */
|
||||
|
||||
rc = pci_request_region(pdev, 0, WIL_NAME);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "pci_request_region failed\n");
|
||||
goto err_disable_pdev;
|
||||
}
|
||||
/* rollback to err_release_reg */
|
||||
|
||||
csr = pci_ioremap_bar(pdev, 0);
|
||||
if (!csr) {
|
||||
dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
|
||||
rc = -ENODEV;
|
||||
goto err_release_reg;
|
||||
}
|
||||
/* rollback to err_iounmap */
|
||||
dev_info(&pdev->dev, "CSR at %pR -> %p\n", &pdev->resource[0], csr);
|
||||
|
||||
wil = wil_if_alloc(dev, csr);
|
||||
if (IS_ERR(wil)) {
|
||||
rc = (int)PTR_ERR(wil);
|
||||
dev_err(dev, "wil_if_alloc failed: %d\n", rc);
|
||||
goto err_iounmap;
|
||||
}
|
||||
/* rollback to if_free */
|
||||
|
||||
pci_set_drvdata(pdev, wil);
|
||||
wil->pdev = pdev;
|
||||
|
||||
/* FW should raise IRQ when ready */
|
||||
rc = wil_if_pcie_enable(wil);
|
||||
if (rc) {
|
||||
wil_err(wil, "Enable device failed\n");
|
||||
goto if_free;
|
||||
}
|
||||
/* rollback to bus_disable */
|
||||
|
||||
rc = wil_if_add(wil);
|
||||
if (rc) {
|
||||
wil_err(wil, "wil_if_add failed: %d\n", rc);
|
||||
goto bus_disable;
|
||||
}
|
||||
|
||||
wil6210_debugfs_init(wil);
|
||||
|
||||
/* check FW is alive */
|
||||
wmi_echo(wil);
|
||||
|
||||
return 0;
|
||||
|
||||
bus_disable:
|
||||
wil_if_pcie_disable(wil);
|
||||
if_free:
|
||||
wil_if_free(wil);
|
||||
err_iounmap:
|
||||
pci_iounmap(pdev, csr);
|
||||
err_release_reg:
|
||||
pci_release_region(pdev, 0);
|
||||
err_disable_pdev:
|
||||
pci_disable_device(pdev);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void wil_pcie_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct wil6210_priv *wil = pci_get_drvdata(pdev);
|
||||
|
||||
wil6210_debugfs_remove(wil);
|
||||
wil_if_pcie_disable(wil);
|
||||
wil_if_remove(wil);
|
||||
wil_if_free(wil);
|
||||
pci_iounmap(pdev, wil->csr);
|
||||
pci_release_region(pdev, 0);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
}
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(wil6210_pcie_ids) = {
|
||||
{ PCI_DEVICE(0x1ae9, 0x0301) },
|
||||
{ /* end: all zeroes */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, wil6210_pcie_ids);
|
||||
|
||||
static struct pci_driver wil6210_driver = {
|
||||
.probe = wil_pcie_probe,
|
||||
.remove = wil_pcie_remove,
|
||||
.id_table = wil6210_pcie_ids,
|
||||
.name = WIL_NAME,
|
||||
};
|
||||
|
||||
module_pci_driver(wil6210_driver);
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_AUTHOR("Qualcomm Atheros <wil6210@qca.qualcomm.com>");
|
||||
MODULE_DESCRIPTION("Driver for 60g WiFi WIL6210 card");
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,362 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef WIL6210_TXRX_H
|
||||
#define WIL6210_TXRX_H
|
||||
|
||||
#define BUF_SW_OWNED (1)
|
||||
#define BUF_HW_OWNED (0)
|
||||
|
||||
/* size of max. Rx packet */
|
||||
#define RX_BUF_LEN (2048)
|
||||
#define TX_BUF_LEN (2048)
|
||||
/* how many bytes to reserve for rtap header? */
|
||||
#define WIL6210_RTAP_SIZE (128)
|
||||
|
||||
/* Tx/Rx path */
|
||||
/*
|
||||
* Tx descriptor - MAC part
|
||||
* [dword 0]
|
||||
* bit 0.. 9 : lifetime_expiry_value:10
|
||||
* bit 10 : interrup_en:1
|
||||
* bit 11 : status_en:1
|
||||
* bit 12..13 : txss_override:2
|
||||
* bit 14 : timestamp_insertion:1
|
||||
* bit 15 : duration_preserve:1
|
||||
* bit 16..21 : reserved0:6
|
||||
* bit 22..26 : mcs_index:5
|
||||
* bit 27 : mcs_en:1
|
||||
* bit 28..29 : reserved1:2
|
||||
* bit 30 : reserved2:1
|
||||
* bit 31 : sn_preserved:1
|
||||
* [dword 1]
|
||||
* bit 0.. 3 : pkt_mode:4
|
||||
* bit 4 : pkt_mode_en:1
|
||||
* bit 5.. 7 : reserved0:3
|
||||
* bit 8..13 : reserved1:6
|
||||
* bit 14 : reserved2:1
|
||||
* bit 15 : ack_policy_en:1
|
||||
* bit 16..19 : dst_index:4
|
||||
* bit 20 : dst_index_en:1
|
||||
* bit 21..22 : ack_policy:2
|
||||
* bit 23 : lifetime_en:1
|
||||
* bit 24..30 : max_retry:7
|
||||
* bit 31 : max_retry_en:1
|
||||
* [dword 2]
|
||||
* bit 0.. 7 : num_of_descriptors:8
|
||||
* bit 8..17 : reserved:10
|
||||
* bit 18..19 : l2_translation_type:2
|
||||
* bit 20 : snap_hdr_insertion_en:1
|
||||
* bit 21 : vlan_removal_en:1
|
||||
* bit 22..31 : reserved0:10
|
||||
* [dword 3]
|
||||
* bit 0.. 31: ucode_cmd:32
|
||||
*/
|
||||
struct vring_tx_mac {
|
||||
u32 d[3];
|
||||
u32 ucode_cmd;
|
||||
} __packed;
|
||||
|
||||
/* TX MAC Dword 0 */
|
||||
#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
|
||||
#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
|
||||
#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
|
||||
#define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
|
||||
#define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
|
||||
#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
|
||||
#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
|
||||
#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
|
||||
#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
|
||||
#define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
|
||||
#define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
|
||||
#define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
|
||||
|
||||
#define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
|
||||
#define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
|
||||
#define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
|
||||
|
||||
/* TX MAC Dword 1 */
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
|
||||
#define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
|
||||
#define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
|
||||
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
|
||||
|
||||
/* TX MAC Dword 2 */
|
||||
#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
|
||||
#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
|
||||
#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
|
||||
|
||||
#define MAC_CFG_DESC_TX_2_RESERVED_POS 8
|
||||
#define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
|
||||
#define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
|
||||
|
||||
#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
|
||||
#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
|
||||
#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
|
||||
|
||||
#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
|
||||
#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
|
||||
|
||||
#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
|
||||
#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
|
||||
#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
|
||||
|
||||
/* TX MAC Dword 3 */
|
||||
#define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
|
||||
#define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
|
||||
#define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
|
||||
|
||||
/* TX DMA Dword 0 */
|
||||
#define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
|
||||
#define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
|
||||
#define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
|
||||
#define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
|
||||
#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
|
||||
#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
|
||||
#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
|
||||
#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
|
||||
#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
|
||||
#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_QID_POS 16
|
||||
#define DMA_CFG_DESC_TX_0_QID_LEN 5
|
||||
#define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
|
||||
#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
|
||||
#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
|
||||
|
||||
#define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
|
||||
#define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
|
||||
#define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000
|
||||
|
||||
|
||||
#define TX_DMA_STATUS_DU BIT(0)
|
||||
|
||||
struct vring_tx_dma {
|
||||
u32 d0;
|
||||
u32 addr_low;
|
||||
u16 addr_high;
|
||||
u8 ip_length;
|
||||
u8 b11; /* 0..6: mac_length; 7:ip_version */
|
||||
u8 error; /* 0..2: err; 3..7: reserved; */
|
||||
u8 status; /* 0: used; 1..7; reserved */
|
||||
u16 length;
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Rx descriptor - MAC part
|
||||
* [dword 0]
|
||||
* bit 0.. 3 : tid:4 The QoS (b3-0) TID Field
|
||||
* bit 4.. 6 : connection_id:3 :The Source index that was found during
|
||||
* Parsing the TA. This field is used to define the source of the packet
|
||||
* bit 7 : reserved:1
|
||||
* bit 8.. 9 : mac_id:2 : The MAC virtual Ring number (always zero)
|
||||
* bit 10..11 : frame_type:2 : The FC Control (b3-2) - MPDU Type
|
||||
* (management, data, control and extension)
|
||||
* bit 12..15 : frame_subtype:4 : The FC Control (b7-4) - Frame Subtype
|
||||
* bit 16..27 : seq_number:12 The received Sequence number field
|
||||
* bit 28..31 : extended:4 extended subtype
|
||||
* [dword 1]
|
||||
* bit 0.. 3 : reserved
|
||||
* bit 4.. 5 : key_id:2
|
||||
* bit 6 : decrypt_bypass:1
|
||||
* bit 7 : security:1
|
||||
* bit 8.. 9 : ds_bits:2
|
||||
* bit 10 : a_msdu_present:1 from qos header
|
||||
* bit 11 : a_msdu_type:1 from qos header
|
||||
* bit 12 : a_mpdu:1 part of AMPDU aggregation
|
||||
* bit 13 : broadcast:1
|
||||
* bit 14 : mutlicast:1
|
||||
* bit 15 : reserved:1
|
||||
* bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
|
||||
* is received from
|
||||
* bit 21..24 : mcs:4
|
||||
* bit 25..28 : mic_icr:4
|
||||
* bit 29..31 : reserved:3
|
||||
* [dword 2]
|
||||
* bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received
|
||||
* bit 3 : fc_protocol_ver:1 The FC Control (b0) - Protocol Version
|
||||
* bit 4 : fc_order:1 The FC Control (b15) -Order
|
||||
* bit 5.. 7 : qos_ack_policy:3 The QoS (b6-5) ack policy Field
|
||||
* bit 8 : esop:1 The QoS (b4) ESOP field
|
||||
* bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
|
||||
* bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
|
||||
* bit 15 : qos_ac_constraint:1
|
||||
* bit 16..31 : pn_15_0:16 low 2 bytes of PN
|
||||
* [dword 3]
|
||||
* bit 0..31 : pn_47_16:32 high 4 bytes of PN
|
||||
*/
|
||||
struct vring_rx_mac {
|
||||
u32 d0;
|
||||
u32 d1;
|
||||
u16 w4;
|
||||
u16 pn_15_0;
|
||||
u32 pn_47_16;
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Rx descriptor - DMA part
|
||||
* [dword 0]
|
||||
* bit 0.. 7 : l4_length:8 layer 4 length
|
||||
* bit 8.. 9 : reserved:2
|
||||
* bit 10 : cmd_dma_it:1
|
||||
* bit 11..15 : reserved:5
|
||||
* bit 16..29 : phy_info_length:14
|
||||
* bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
|
||||
* [dword 1]
|
||||
* bit 0..31 : addr_low:32 The payload buffer low address
|
||||
* [dword 2]
|
||||
* bit 0..15 : addr_high:16 The payload buffer high address
|
||||
* bit 16..23 : ip_length:8
|
||||
* bit 24..30 : mac_length:7
|
||||
* bit 31 : ip_version:1
|
||||
* [dword 3]
|
||||
* [byte 12] error
|
||||
* [byte 13] status
|
||||
* bit 0 : du:1
|
||||
* bit 1 : eop:1
|
||||
* bit 2 : error:1
|
||||
* bit 3 : mi:1
|
||||
* bit 4 : l3_identified:1
|
||||
* bit 5 : l4_identified:1
|
||||
* bit 6 : phy_info_included:1
|
||||
* bit 7 : reserved:1
|
||||
* [word 7] length
|
||||
*
|
||||
*/
|
||||
|
||||
#define RX_DMA_D0_CMD_DMA_IT BIT(10)
|
||||
|
||||
#define RX_DMA_STATUS_DU BIT(0)
|
||||
#define RX_DMA_STATUS_ERROR BIT(2)
|
||||
#define RX_DMA_STATUS_PHY_INFO BIT(6)
|
||||
|
||||
struct vring_rx_dma {
|
||||
u32 d0;
|
||||
u32 addr_low;
|
||||
u16 addr_high;
|
||||
u8 ip_length;
|
||||
u8 b11;
|
||||
u8 error;
|
||||
u8 status;
|
||||
u16 length;
|
||||
} __packed;
|
||||
|
||||
struct vring_tx_desc {
|
||||
struct vring_tx_mac mac;
|
||||
struct vring_tx_dma dma;
|
||||
} __packed;
|
||||
|
||||
struct vring_rx_desc {
|
||||
struct vring_rx_mac mac;
|
||||
struct vring_rx_dma dma;
|
||||
} __packed;
|
||||
|
||||
union vring_desc {
|
||||
struct vring_tx_desc tx;
|
||||
struct vring_rx_desc rx;
|
||||
} __packed;
|
||||
|
||||
static inline int wil_rxdesc_phy_length(volatile struct vring_rx_desc *d)
|
||||
{
|
||||
return WIL_GET_BITS(d->dma.d0, 16, 29);
|
||||
}
|
||||
|
||||
static inline int wil_rxdesc_mcs(volatile struct vring_rx_desc *d)
|
||||
{
|
||||
return WIL_GET_BITS(d->mac.d1, 21, 24);
|
||||
}
|
||||
|
||||
static inline int wil_rxdesc_ds_bits(volatile struct vring_rx_desc *d)
|
||||
{
|
||||
return WIL_GET_BITS(d->mac.d1, 8, 9);
|
||||
}
|
||||
|
||||
static inline int wil_rxdesc_ftype(volatile struct vring_rx_desc *d)
|
||||
{
|
||||
return WIL_GET_BITS(d->mac.d0, 10, 11);
|
||||
}
|
||||
|
||||
#endif /* WIL6210_TXRX_H */
|
||||
@@ -0,0 +1,363 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Qualcomm Atheros, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __WIL6210_H__
|
||||
#define __WIL6210_H__
|
||||
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/wireless.h>
|
||||
#include <net/cfg80211.h>
|
||||
|
||||
#include "dbg_hexdump.h"
|
||||
|
||||
#define WIL_NAME "wil6210"
|
||||
|
||||
/**
|
||||
* extract bits [@b0:@b1] (inclusive) from the value @x
|
||||
* it should be @b0 <= @b1, or result is incorrect
|
||||
*/
|
||||
static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
|
||||
{
|
||||
return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
|
||||
}
|
||||
|
||||
#define WIL6210_MEM_SIZE (2*1024*1024UL)
|
||||
|
||||
#define WIL6210_TX_QUEUES (4)
|
||||
|
||||
#define WIL6210_RX_RING_SIZE (128)
|
||||
#define WIL6210_TX_RING_SIZE (128)
|
||||
#define WIL6210_MAX_TX_RINGS (24)
|
||||
|
||||
/* Hardware definitions begin */
|
||||
|
||||
/*
|
||||
* Mapping
|
||||
* RGF File | Host addr | FW addr
|
||||
* | |
|
||||
* user_rgf | 0x000000 | 0x880000
|
||||
* dma_rgf | 0x001000 | 0x881000
|
||||
* pcie_rgf | 0x002000 | 0x882000
|
||||
* | |
|
||||
*/
|
||||
|
||||
/* Where various structures placed in host address space */
|
||||
#define WIL6210_FW_HOST_OFF (0x880000UL)
|
||||
|
||||
#define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF)
|
||||
|
||||
/*
|
||||
* Interrupt control registers block
|
||||
*
|
||||
* each interrupt controlled by the same bit in all registers
|
||||
*/
|
||||
struct RGF_ICR {
|
||||
u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
|
||||
u32 ICR; /* Cause, W1C/COR depending on ICC */
|
||||
u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
|
||||
u32 ICS; /* Cause Set, WO */
|
||||
u32 IMV; /* Mask, RW+S/C */
|
||||
u32 IMS; /* Mask Set, write 1 to set */
|
||||
u32 IMC; /* Mask Clear, write 1 to clear */
|
||||
} __packed;
|
||||
|
||||
/* registers - FW addresses */
|
||||
#define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
|
||||
#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
|
||||
#define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
|
||||
#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
|
||||
#define RGF_USER_MAC_CPU_0 (0x8801fc)
|
||||
#define RGF_USER_USER_CPU_0 (0x8801e0)
|
||||
#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
|
||||
#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
|
||||
#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
|
||||
#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
|
||||
|
||||
#define RGF_DMA_PSEUDO_CAUSE (0x881c68)
|
||||
#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
|
||||
#define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70)
|
||||
#define BIT_DMA_PSEUDO_CAUSE_RX BIT(0)
|
||||
#define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
|
||||
#define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
|
||||
|
||||
#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
|
||||
#define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
|
||||
#define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */
|
||||
#define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */
|
||||
#define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0)
|
||||
#define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
|
||||
#define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
|
||||
#define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
|
||||
#define BIT_DMA_EP_MISC_ICR_FW_INT0 BIT(28)
|
||||
#define BIT_DMA_EP_MISC_ICR_FW_INT1 BIT(29)
|
||||
|
||||
/* Interrupt moderation control */
|
||||
#define RGF_DMA_ITR_CNT_TRSH (0x881c5c)
|
||||
#define RGF_DMA_ITR_CNT_DATA (0x881c60)
|
||||
#define RGF_DMA_ITR_CNT_CRL (0x881C64)
|
||||
#define BIT_DMA_ITR_CNT_CRL_EN BIT(0)
|
||||
#define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1)
|
||||
#define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2)
|
||||
#define BIT_DMA_ITR_CNT_CRL_CLR BIT(3)
|
||||
#define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4)
|
||||
|
||||
/* popular locations */
|
||||
#define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
|
||||
#define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
|
||||
offsetof(struct RGF_ICR, ICS))
|
||||
#define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
|
||||
|
||||
/* ISR register bits */
|
||||
#define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT0
|
||||
#define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT1
|
||||
|
||||
/* Hardware definitions end */
|
||||
|
||||
struct wil6210_mbox_ring {
|
||||
u32 base;
|
||||
u16 entry_size; /* max. size of mbox entry, incl. all headers */
|
||||
u16 size;
|
||||
u32 tail;
|
||||
u32 head;
|
||||
} __packed;
|
||||
|
||||
struct wil6210_mbox_ring_desc {
|
||||
__le32 sync;
|
||||
__le32 addr;
|
||||
} __packed;
|
||||
|
||||
/* at HOST_OFF_WIL6210_MBOX_CTL */
|
||||
struct wil6210_mbox_ctl {
|
||||
struct wil6210_mbox_ring tx;
|
||||
struct wil6210_mbox_ring rx;
|
||||
} __packed;
|
||||
|
||||
struct wil6210_mbox_hdr {
|
||||
__le16 seq;
|
||||
__le16 len; /* payload, bytes after this header */
|
||||
__le16 type;
|
||||
u8 flags;
|
||||
u8 reserved;
|
||||
} __packed;
|
||||
|
||||
#define WIL_MBOX_HDR_TYPE_WMI (0)
|
||||
|
||||
/* max. value for wil6210_mbox_hdr.len */
|
||||
#define MAX_MBOXITEM_SIZE (240)
|
||||
|
||||
struct wil6210_mbox_hdr_wmi {
|
||||
u8 reserved0[2];
|
||||
__le16 id;
|
||||
__le16 info1; /* bits [0..3] - device_id, rest - unused */
|
||||
u8 reserved1[2];
|
||||
} __packed;
|
||||
|
||||
struct pending_wmi_event {
|
||||
struct list_head list;
|
||||
struct {
|
||||
struct wil6210_mbox_hdr hdr;
|
||||
struct wil6210_mbox_hdr_wmi wmi;
|
||||
u8 data[0];
|
||||
} __packed event;
|
||||
};
|
||||
|
||||
union vring_desc;
|
||||
|
||||
struct vring {
|
||||
dma_addr_t pa;
|
||||
volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
|
||||
u16 size; /* number of vring_desc elements */
|
||||
u32 swtail;
|
||||
u32 swhead;
|
||||
u32 hwtail; /* write here to inform hw */
|
||||
void **ctx; /* void *ctx[size] - software context */
|
||||
};
|
||||
|
||||
enum { /* for wil6210_priv.status */
|
||||
wil_status_fwready = 0,
|
||||
wil_status_fwconnected,
|
||||
wil_status_dontscan,
|
||||
wil_status_irqen, /* FIXME: interrupts enabled - for debug */
|
||||
};
|
||||
|
||||
struct pci_dev;
|
||||
|
||||
struct wil6210_stats {
|
||||
u64 tsf;
|
||||
u32 snr;
|
||||
u16 last_mcs_rx;
|
||||
u16 bf_mcs; /* last BF, used for Tx */
|
||||
u16 my_rx_sector;
|
||||
u16 my_tx_sector;
|
||||
u16 peer_rx_sector;
|
||||
u16 peer_tx_sector;
|
||||
};
|
||||
|
||||
struct wil6210_priv {
|
||||
struct pci_dev *pdev;
|
||||
int n_msi;
|
||||
struct wireless_dev *wdev;
|
||||
void __iomem *csr;
|
||||
ulong status;
|
||||
/* profile */
|
||||
u32 monitor_flags;
|
||||
u32 secure_pcp; /* create secure PCP? */
|
||||
int sinfo_gen;
|
||||
/* cached ISR registers */
|
||||
u32 isr_misc;
|
||||
/* mailbox related */
|
||||
struct mutex wmi_mutex;
|
||||
struct wil6210_mbox_ctl mbox_ctl;
|
||||
struct completion wmi_ready;
|
||||
u16 wmi_seq;
|
||||
u16 reply_id; /**< wait for this WMI event */
|
||||
void *reply_buf;
|
||||
u16 reply_size;
|
||||
struct workqueue_struct *wmi_wq; /* for deferred calls */
|
||||
struct work_struct wmi_event_worker;
|
||||
struct workqueue_struct *wmi_wq_conn; /* for connect worker */
|
||||
struct work_struct wmi_connect_worker;
|
||||
struct work_struct disconnect_worker;
|
||||
struct timer_list connect_timer;
|
||||
int pending_connect_cid;
|
||||
struct list_head pending_wmi_ev;
|
||||
/*
|
||||
* protect pending_wmi_ev
|
||||
* - fill in IRQ from wil6210_irq_misc,
|
||||
* - consumed in thread by wmi_event_worker
|
||||
*/
|
||||
spinlock_t wmi_ev_lock;
|
||||
/* DMA related */
|
||||
struct vring vring_rx;
|
||||
struct vring vring_tx[WIL6210_MAX_TX_RINGS];
|
||||
u8 dst_addr[WIL6210_MAX_TX_RINGS][ETH_ALEN];
|
||||
/* scan */
|
||||
struct cfg80211_scan_request *scan_request;
|
||||
|
||||
struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
|
||||
/* statistics */
|
||||
struct wil6210_stats stats;
|
||||
/* debugfs */
|
||||
struct dentry *debug;
|
||||
struct debugfs_blob_wrapper fw_code_blob;
|
||||
struct debugfs_blob_wrapper fw_data_blob;
|
||||
struct debugfs_blob_wrapper fw_peri_blob;
|
||||
struct debugfs_blob_wrapper uc_code_blob;
|
||||
struct debugfs_blob_wrapper uc_data_blob;
|
||||
struct debugfs_blob_wrapper rgf_blob;
|
||||
};
|
||||
|
||||
#define wil_to_wiphy(i) (i->wdev->wiphy)
|
||||
#define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
|
||||
#define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
|
||||
#define wil_to_wdev(i) (i->wdev)
|
||||
#define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
|
||||
#define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
|
||||
#define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
|
||||
|
||||
#define wil_dbg(wil, fmt, arg...) netdev_dbg(wil_to_ndev(wil), fmt, ##arg)
|
||||
#define wil_info(wil, fmt, arg...) netdev_info(wil_to_ndev(wil), fmt, ##arg)
|
||||
#define wil_err(wil, fmt, arg...) netdev_err(wil_to_ndev(wil), fmt, ##arg)
|
||||
|
||||
#define wil_dbg_IRQ(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
|
||||
#define wil_dbg_TXRX(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
|
||||
#define wil_dbg_WMI(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
|
||||
|
||||
#define wil_hex_dump_TXRX(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii) \
|
||||
wil_print_hex_dump_debug("DBG[TXRX]" prefix_str,\
|
||||
prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii)
|
||||
|
||||
#define wil_hex_dump_WMI(prefix_str, prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii) \
|
||||
wil_print_hex_dump_debug("DBG[ WMI]" prefix_str,\
|
||||
prefix_type, rowsize, \
|
||||
groupsize, buf, len, ascii)
|
||||
|
||||
void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
|
||||
size_t count);
|
||||
void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
|
||||
size_t count);
|
||||
|
||||
void *wil_if_alloc(struct device *dev, void __iomem *csr);
|
||||
void wil_if_free(struct wil6210_priv *wil);
|
||||
int wil_if_add(struct wil6210_priv *wil);
|
||||
void wil_if_remove(struct wil6210_priv *wil);
|
||||
int wil_priv_init(struct wil6210_priv *wil);
|
||||
void wil_priv_deinit(struct wil6210_priv *wil);
|
||||
int wil_reset(struct wil6210_priv *wil);
|
||||
void wil_link_on(struct wil6210_priv *wil);
|
||||
void wil_link_off(struct wil6210_priv *wil);
|
||||
int wil_up(struct wil6210_priv *wil);
|
||||
int wil_down(struct wil6210_priv *wil);
|
||||
void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
|
||||
|
||||
void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
|
||||
void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
|
||||
int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
|
||||
struct wil6210_mbox_hdr *hdr);
|
||||
int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
|
||||
void wmi_recv_cmd(struct wil6210_priv *wil);
|
||||
int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
|
||||
u16 reply_id, void *reply, u8 reply_size, int to_msec);
|
||||
void wmi_connect_worker(struct work_struct *work);
|
||||
void wmi_event_worker(struct work_struct *work);
|
||||
void wmi_event_flush(struct wil6210_priv *wil);
|
||||
int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
|
||||
int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
|
||||
int wmi_set_channel(struct wil6210_priv *wil, int channel);
|
||||
int wmi_get_channel(struct wil6210_priv *wil, int *channel);
|
||||
int wmi_tx_eapol(struct wil6210_priv *wil, struct sk_buff *skb);
|
||||
int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
|
||||
const void *mac_addr);
|
||||
int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
|
||||
const void *mac_addr, int key_len, const void *key);
|
||||
int wmi_echo(struct wil6210_priv *wil);
|
||||
int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
|
||||
|
||||
int wil6210_init_irq(struct wil6210_priv *wil, int irq);
|
||||
void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
|
||||
void wil6210_disable_irq(struct wil6210_priv *wil);
|
||||
void wil6210_enable_irq(struct wil6210_priv *wil);
|
||||
|
||||
int wil6210_debugfs_init(struct wil6210_priv *wil);
|
||||
void wil6210_debugfs_remove(struct wil6210_priv *wil);
|
||||
|
||||
struct wireless_dev *wil_cfg80211_init(struct device *dev);
|
||||
void wil_wdev_free(struct wil6210_priv *wil);
|
||||
|
||||
int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
|
||||
int wmi_set_bcon(struct wil6210_priv *wil, int bi, u8 wmi_nettype);
|
||||
void wil6210_disconnect(struct wil6210_priv *wil, void *bssid);
|
||||
|
||||
int wil_rx_init(struct wil6210_priv *wil);
|
||||
void wil_rx_fini(struct wil6210_priv *wil);
|
||||
|
||||
/* TX API */
|
||||
int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
|
||||
int cid, int tid);
|
||||
void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
|
||||
|
||||
netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
|
||||
void wil_tx_complete(struct wil6210_priv *wil, int ringid);
|
||||
|
||||
/* RX API */
|
||||
void wil_rx_handle(struct wil6210_priv *wil);
|
||||
|
||||
int wil_iftype_nl2wmi(enum nl80211_iftype type);
|
||||
|
||||
#endif /* __WIL6210_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -7,6 +7,7 @@
|
||||
#include <linux/hw_random.h>
|
||||
#include <linux/bcma/bcma.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/completion.h>
|
||||
#include <net/mac80211.h>
|
||||
|
||||
#include "debugfs.h"
|
||||
@@ -722,6 +723,10 @@ enum b43_firmware_file_type {
|
||||
struct b43_request_fw_context {
|
||||
/* The device we are requesting the fw for. */
|
||||
struct b43_wldev *dev;
|
||||
/* a completion event structure needed if this call is asynchronous */
|
||||
struct completion fw_load_complete;
|
||||
/* a pointer to the firmware object */
|
||||
const struct firmware *blob;
|
||||
/* The type of firmware to request. */
|
||||
enum b43_firmware_file_type req_type;
|
||||
/* Error messages for each firmware type. */
|
||||
|
||||
@@ -2088,11 +2088,18 @@ static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
|
||||
b43warn(wl, text);
|
||||
}
|
||||
|
||||
static void b43_fw_cb(const struct firmware *firmware, void *context)
|
||||
{
|
||||
struct b43_request_fw_context *ctx = context;
|
||||
|
||||
ctx->blob = firmware;
|
||||
complete(&ctx->fw_load_complete);
|
||||
}
|
||||
|
||||
int b43_do_request_fw(struct b43_request_fw_context *ctx,
|
||||
const char *name,
|
||||
struct b43_firmware_file *fw)
|
||||
struct b43_firmware_file *fw, bool async)
|
||||
{
|
||||
const struct firmware *blob;
|
||||
struct b43_fw_header *hdr;
|
||||
u32 size;
|
||||
int err;
|
||||
@@ -2131,11 +2138,31 @@ int b43_do_request_fw(struct b43_request_fw_context *ctx,
|
||||
B43_WARN_ON(1);
|
||||
return -ENOSYS;
|
||||
}
|
||||
err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
|
||||
if (async) {
|
||||
/* do this part asynchronously */
|
||||
init_completion(&ctx->fw_load_complete);
|
||||
err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
|
||||
ctx->dev->dev->dev, GFP_KERNEL,
|
||||
ctx, b43_fw_cb);
|
||||
if (err < 0) {
|
||||
pr_err("Unable to load firmware\n");
|
||||
return err;
|
||||
}
|
||||
/* stall here until fw ready */
|
||||
wait_for_completion(&ctx->fw_load_complete);
|
||||
if (ctx->blob)
|
||||
goto fw_ready;
|
||||
/* On some ARM systems, the async request will fail, but the next sync
|
||||
* request works. For this reason, we dall through here
|
||||
*/
|
||||
}
|
||||
err = request_firmware(&ctx->blob, ctx->fwname,
|
||||
ctx->dev->dev->dev);
|
||||
if (err == -ENOENT) {
|
||||
snprintf(ctx->errors[ctx->req_type],
|
||||
sizeof(ctx->errors[ctx->req_type]),
|
||||
"Firmware file \"%s\" not found\n", ctx->fwname);
|
||||
"Firmware file \"%s\" not found\n",
|
||||
ctx->fwname);
|
||||
return err;
|
||||
} else if (err) {
|
||||
snprintf(ctx->errors[ctx->req_type],
|
||||
@@ -2144,14 +2171,15 @@ int b43_do_request_fw(struct b43_request_fw_context *ctx,
|
||||
ctx->fwname, err);
|
||||
return err;
|
||||
}
|
||||
if (blob->size < sizeof(struct b43_fw_header))
|
||||
fw_ready:
|
||||
if (ctx->blob->size < sizeof(struct b43_fw_header))
|
||||
goto err_format;
|
||||
hdr = (struct b43_fw_header *)(blob->data);
|
||||
hdr = (struct b43_fw_header *)(ctx->blob->data);
|
||||
switch (hdr->type) {
|
||||
case B43_FW_TYPE_UCODE:
|
||||
case B43_FW_TYPE_PCM:
|
||||
size = be32_to_cpu(hdr->size);
|
||||
if (size != blob->size - sizeof(struct b43_fw_header))
|
||||
if (size != ctx->blob->size - sizeof(struct b43_fw_header))
|
||||
goto err_format;
|
||||
/* fallthrough */
|
||||
case B43_FW_TYPE_IV:
|
||||
@@ -2162,7 +2190,7 @@ int b43_do_request_fw(struct b43_request_fw_context *ctx,
|
||||
goto err_format;
|
||||
}
|
||||
|
||||
fw->data = blob;
|
||||
fw->data = ctx->blob;
|
||||
fw->filename = name;
|
||||
fw->type = ctx->req_type;
|
||||
|
||||
@@ -2172,7 +2200,7 @@ err_format:
|
||||
snprintf(ctx->errors[ctx->req_type],
|
||||
sizeof(ctx->errors[ctx->req_type]),
|
||||
"Firmware file \"%s\" format error.\n", ctx->fwname);
|
||||
release_firmware(blob);
|
||||
release_firmware(ctx->blob);
|
||||
|
||||
return -EPROTO;
|
||||
}
|
||||
@@ -2223,7 +2251,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
|
||||
goto err_no_ucode;
|
||||
}
|
||||
}
|
||||
err = b43_do_request_fw(ctx, filename, &fw->ucode);
|
||||
err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
|
||||
if (err)
|
||||
goto err_load;
|
||||
|
||||
@@ -2235,7 +2263,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
|
||||
else
|
||||
goto err_no_pcm;
|
||||
fw->pcm_request_failed = false;
|
||||
err = b43_do_request_fw(ctx, filename, &fw->pcm);
|
||||
err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
|
||||
if (err == -ENOENT) {
|
||||
/* We did not find a PCM file? Not fatal, but
|
||||
* core rev <= 10 must do without hwcrypto then. */
|
||||
@@ -2296,7 +2324,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
|
||||
default:
|
||||
goto err_no_initvals;
|
||||
}
|
||||
err = b43_do_request_fw(ctx, filename, &fw->initvals);
|
||||
err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
|
||||
if (err)
|
||||
goto err_load;
|
||||
|
||||
@@ -2355,7 +2383,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
|
||||
default:
|
||||
goto err_no_initvals;
|
||||
}
|
||||
err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
|
||||
err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
|
||||
if (err)
|
||||
goto err_load;
|
||||
|
||||
|
||||
@@ -137,9 +137,8 @@ void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on);
|
||||
|
||||
|
||||
struct b43_request_fw_context;
|
||||
int b43_do_request_fw(struct b43_request_fw_context *ctx,
|
||||
const char *name,
|
||||
struct b43_firmware_file *fw);
|
||||
int b43_do_request_fw(struct b43_request_fw_context *ctx, const char *name,
|
||||
struct b43_firmware_file *fw, bool async);
|
||||
void b43_do_release_fw(struct b43_firmware_file *fw);
|
||||
|
||||
#endif /* B43_MAIN_H_ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user