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Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc power management changes from Arnd Bergmann:
"These are various power management related changes, mainly concerning
cpuidle on i.MX and OMAP, as well as a the move of the omap
smartreflex driver to live in the power subsystem."
Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}
* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
ARM: OMAP2+: do not allow SmartReflex to be built as a module
ARM: OMAP2: Use hwmod to initialize mmc for 2420
ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
ARM: OMAP3: PM: call pre/post transition per powerdomain
ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
ARM: OMAP3+: PRM: Enable IO wake up
ARM: OMAP4: PRM: Add IO Daisychain support
ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3: PM: correct enable/disable of daisy io chain
ARM: OMAP2+: PRM: fix compile for OMAP4-only build
W1: OMAP HDQ1W: use runtime PM
ARM: OMAP2+: HDQ1W: use omap_device
W1: OMAP HDQ1W: use 32-bit register accesses
W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
...
This commit is contained in:
Linus Torvalds
@@ -279,6 +279,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
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clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
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clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
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clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
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/* Set SDHC parents to be PLL2 */
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clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
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@@ -336,7 +337,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
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clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
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clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
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clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
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clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
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clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
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clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
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clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
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@@ -120,6 +120,7 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
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.handle_irq = imx53_handle_irq,
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.timer = &imx53_timer,
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.init_machine = imx53_dt_init,
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.init_late = imx53_init_late,
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.dt_compat = imx53_dt_board_compat,
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.restart = mxc_restart,
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MACHINE_END
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@@ -12,7 +12,9 @@
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/cpuidle.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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@@ -24,6 +26,7 @@
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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#include <linux/mfd/anatop.h>
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#include <asm/cpuidle.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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@@ -31,8 +34,10 @@
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/common.h>
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#include <mach/cpuidle.h>
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#include <mach/hardware.h>
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void imx6q_restart(char mode, const char *cmd)
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{
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struct device_node *np;
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@@ -169,6 +174,19 @@ static void __init imx6q_init_machine(void)
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imx6q_usb_init();
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}
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static struct cpuidle_driver imx6q_cpuidle_driver = {
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.name = "imx6q_cpuidle",
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.owner = THIS_MODULE,
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.en_core_tk_irqen = 1,
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.states[0] = ARM_CPUIDLE_WFI_STATE,
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.state_count = 1,
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};
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static void __init imx6q_init_late(void)
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{
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imx_cpuidle_init(&imx6q_cpuidle_driver);
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}
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static void __init imx6q_map_io(void)
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{
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imx_lluart_map_io();
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@@ -213,6 +231,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
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.handle_irq = imx6q_handle_irq,
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.timer = &imx6q_timer,
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.init_machine = imx6q_init_machine,
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.init_late = imx6q_init_late,
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.dt_compat = imx6q_dt_compat,
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.restart = imx6q_restart,
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MACHINE_END
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@@ -267,5 +267,6 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
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.handle_irq = imx53_handle_irq,
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.timer = &mx53_ard_timer,
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.init_machine = mx53_ard_board_init,
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.init_late = imx53_init_late,
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.restart = mxc_restart,
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MACHINE_END
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@@ -174,5 +174,6 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
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.handle_irq = imx53_handle_irq,
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.timer = &mx53_evk_timer,
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.init_machine = mx53_evk_board_init,
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.init_late = imx53_init_late,
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.restart = mxc_restart,
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MACHINE_END
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@@ -316,5 +316,6 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
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.handle_irq = imx53_handle_irq,
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.timer = &mx53_loco_timer,
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.init_machine = mx53_loco_board_init,
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.init_late = imx53_init_late,
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.restart = mxc_restart,
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MACHINE_END
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@@ -163,5 +163,6 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
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.handle_irq = imx53_handle_irq,
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.timer = &mx53_smd_timer,
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.init_machine = mx53_smd_board_init,
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.init_late = imx53_init_late,
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.restart = mxc_restart,
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MACHINE_END
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@@ -16,7 +16,6 @@
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#include <linux/clk.h>
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#include <linux/pinctrl/machine.h>
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#include <asm/system_misc.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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@@ -24,24 +23,6 @@
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#include <mach/devices-common.h>
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#include <mach/iomux-v3.h>
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static struct clk *gpc_dvfs_clk;
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static void imx5_idle(void)
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{
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/* gpc clock is needed for SRPG */
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if (gpc_dvfs_clk == NULL) {
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (IS_ERR(gpc_dvfs_clk))
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return;
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clk_prepare(gpc_dvfs_clk);
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}
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clk_enable(gpc_dvfs_clk);
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (!tzic_enable_wake())
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cpu_do_idle();
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clk_disable(gpc_dvfs_clk);
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}
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/*
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* Define the MX50 memory map.
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*/
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@@ -105,7 +86,6 @@ void __init imx51_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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arm_pm_idle = imx5_idle;
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}
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void __init imx53_init_early(void)
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@@ -243,4 +223,10 @@ void __init imx53_soc_init(void)
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void __init imx51_init_late(void)
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{
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mx51_neon_fixup();
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imx51_pm_init();
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}
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void __init imx53_init_late(void)
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{
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imx53_pm_init();
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}
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+85
-26
@@ -12,19 +12,30 @@
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <asm/cacheflush.h>
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#include <asm/system_misc.h>
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#include <asm/tlbflush.h>
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#include <mach/common.h>
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#include <mach/cpuidle.h>
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#include <mach/hardware.h>
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#include "crm-regs-imx5.h"
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static struct clk *gpc_dvfs_clk;
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/*
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* The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
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* This is also the lowest power state possible without affecting
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* non-cpu parts of the system. For these reasons, imx5 should default
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* to always using this state for cpu idling. The PM_SUSPEND_STANDBY also
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* uses this state and needs to take no action when registers remain confgiured
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* for this state.
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*/
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#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
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/*
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* set cpu low power mode before WFI instruction. This function is called
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* mx5 because it can be used for mx50, mx51, and mx53.
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*/
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void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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{
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u32 plat_lpc, arm_srpgcr, ccm_clpcr;
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u32 empgc0, empgc1;
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@@ -87,11 +98,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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}
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}
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static int mx5_suspend_prepare(void)
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{
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return clk_prepare_enable(gpc_dvfs_clk);
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}
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static int mx5_suspend_enter(suspend_state_t state)
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{
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switch (state) {
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@@ -99,7 +105,7 @@ static int mx5_suspend_enter(suspend_state_t state)
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mx5_cpu_lp_set(STOP_POWER_OFF);
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break;
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case PM_SUSPEND_STANDBY:
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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/* DEFAULT_IDLE_STATE already configured */
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break;
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default:
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return -EINVAL;
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@@ -114,12 +120,10 @@ static int mx5_suspend_enter(suspend_state_t state)
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__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
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}
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cpu_do_idle();
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return 0;
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}
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static void mx5_suspend_finish(void)
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{
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clk_disable_unprepare(gpc_dvfs_clk);
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/* return registers to default idle state */
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mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
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return 0;
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}
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static int mx5_pm_valid(suspend_state_t state)
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@@ -129,25 +133,80 @@ static int mx5_pm_valid(suspend_state_t state)
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static const struct platform_suspend_ops mx5_suspend_ops = {
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.valid = mx5_pm_valid,
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.prepare = mx5_suspend_prepare,
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.enter = mx5_suspend_enter,
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.finish = mx5_suspend_finish,
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};
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static int __init mx5_pm_init(void)
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static inline int imx5_cpu_do_idle(void)
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{
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if (!cpu_is_mx51() && !cpu_is_mx53())
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return 0;
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int ret = tzic_enable_wake();
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if (gpc_dvfs_clk == NULL)
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (likely(!ret))
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cpu_do_idle();
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if (!IS_ERR(gpc_dvfs_clk)) {
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if (cpu_is_mx51())
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suspend_set_ops(&mx5_suspend_ops);
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} else
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return -EPERM;
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return ret;
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}
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static void imx5_pm_idle(void)
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{
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imx5_cpu_do_idle();
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}
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static int imx5_cpuidle_enter(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int idx)
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{
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int ret;
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ret = imx5_cpu_do_idle();
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if (ret < 0)
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return ret;
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return idx;
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}
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static struct cpuidle_driver imx5_cpuidle_driver = {
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.name = "imx5_cpuidle",
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.owner = THIS_MODULE,
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.en_core_tk_irqen = 1,
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.states[0] = {
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.enter = imx5_cpuidle_enter,
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.exit_latency = 2,
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.target_residency = 1,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "IMX5 SRPG",
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.desc = "CPU state retained,powered off",
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},
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.state_count = 1,
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};
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|
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static int __init imx5_pm_common_init(void)
|
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{
|
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int ret;
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struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
|
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|
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if (IS_ERR(gpc_dvfs_clk))
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return PTR_ERR(gpc_dvfs_clk);
|
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|
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ret = clk_prepare_enable(gpc_dvfs_clk);
|
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if (ret)
|
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return ret;
|
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|
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arm_pm_idle = imx5_pm_idle;
|
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|
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/* Set the registers to the default cpu idle state. */
|
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mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
|
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|
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imx_cpuidle_init(&imx5_cpuidle_driver);
|
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return 0;
|
||||
}
|
||||
device_initcall(mx5_pm_init);
|
||||
|
||||
void __init imx51_pm_init(void)
|
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{
|
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int ret = imx5_pm_common_init();
|
||||
if (!ret)
|
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suspend_set_ops(&mx5_suspend_ops);
|
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}
|
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|
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void __init imx53_pm_init(void)
|
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{
|
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imx5_pm_common_init();
|
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}
|
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|
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@@ -74,8 +74,9 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
|
||||
obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
|
||||
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
|
||||
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
|
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obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
|
||||
|
||||
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
|
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obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
|
||||
|
||||
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
|
||||
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
@@ -75,20 +75,6 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
|
||||
|
||||
static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
|
||||
|
||||
static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
|
||||
struct clockdomain *clkdm)
|
||||
{
|
||||
clkdm_allow_idle(clkdm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
|
||||
struct clockdomain *clkdm)
|
||||
{
|
||||
clkdm_deny_idle(clkdm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
@@ -106,8 +92,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||
|
||||
/* Deny idle for C1 */
|
||||
if (index == 0) {
|
||||
pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
|
||||
pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
|
||||
clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
|
||||
clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -129,8 +115,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
|
||||
|
||||
/* Re-allow idle for C1 */
|
||||
if (index == 0) {
|
||||
pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
|
||||
pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
|
||||
clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
|
||||
clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
|
||||
}
|
||||
|
||||
return_sleep_time:
|
||||
@@ -176,7 +162,7 @@ static int next_valid_state(struct cpuidle_device *dev,
|
||||
u32 mpu_deepest_state = PWRDM_POWER_RET;
|
||||
u32 core_deepest_state = PWRDM_POWER_RET;
|
||||
int idx;
|
||||
int next_index = -1;
|
||||
int next_index = 0; /* C1 is the default value */
|
||||
|
||||
if (enable_off_mode) {
|
||||
mpu_deepest_state = PWRDM_POWER_OFF;
|
||||
@@ -207,12 +193,6 @@ static int next_valid_state(struct cpuidle_device *dev,
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* C1 is always valid.
|
||||
* So, no need to check for 'next_index == -1' outside
|
||||
* this loop.
|
||||
*/
|
||||
|
||||
return next_index;
|
||||
}
|
||||
|
||||
@@ -226,23 +206,22 @@ static int next_valid_state(struct cpuidle_device *dev,
|
||||
* the device to the specified or a safer state.
|
||||
*/
|
||||
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
int new_state_idx;
|
||||
u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
|
||||
u32 core_next_state, per_next_state = 0, per_saved_state = 0;
|
||||
struct omap3_idle_statedata *cx;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Prevent idle completely if CAM is active.
|
||||
* Use only C1 if CAM is active.
|
||||
* CAM does not have wakeup capability in OMAP3.
|
||||
*/
|
||||
cam_state = pwrdm_read_pwrst(cam_pd);
|
||||
if (cam_state == PWRDM_POWER_ON) {
|
||||
if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
|
||||
new_state_idx = drv->safe_state_index;
|
||||
goto select_state;
|
||||
}
|
||||
else
|
||||
new_state_idx = next_valid_state(dev, drv, index);
|
||||
|
||||
/*
|
||||
* FIXME: we currently manage device-specific idle states
|
||||
@@ -252,24 +231,28 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
|
||||
* its own code.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Prevent PER off if CORE is not in retention or off as this
|
||||
* would disable PER wakeups completely.
|
||||
*/
|
||||
cx = &omap3_idle_data[index];
|
||||
/* Program PER state */
|
||||
cx = &omap3_idle_data[new_state_idx];
|
||||
core_next_state = cx->core_state;
|
||||
per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
|
||||
if ((per_next_state == PWRDM_POWER_OFF) &&
|
||||
(core_next_state > PWRDM_POWER_RET))
|
||||
per_next_state = PWRDM_POWER_RET;
|
||||
if (new_state_idx == 0) {
|
||||
/* In C1 do not allow PER state lower than CORE state */
|
||||
if (per_next_state < core_next_state)
|
||||
per_next_state = core_next_state;
|
||||
} else {
|
||||
/*
|
||||
* Prevent PER OFF if CORE is not in RETention or OFF as this
|
||||
* would disable PER wakeups completely.
|
||||
*/
|
||||
if ((per_next_state == PWRDM_POWER_OFF) &&
|
||||
(core_next_state > PWRDM_POWER_RET))
|
||||
per_next_state = PWRDM_POWER_RET;
|
||||
}
|
||||
|
||||
/* Are we changing PER target state? */
|
||||
if (per_next_state != per_saved_state)
|
||||
pwrdm_set_next_pwrst(per_pd, per_next_state);
|
||||
|
||||
new_state_idx = next_valid_state(dev, drv, index);
|
||||
|
||||
select_state:
|
||||
ret = omap3_enter_idle(dev, drv, new_state_idx);
|
||||
|
||||
/* Restore original PER state if it was modified */
|
||||
@@ -286,7 +269,7 @@ struct cpuidle_driver omap3_idle_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.states = {
|
||||
{
|
||||
.enter = omap3_enter_idle,
|
||||
.enter = omap3_enter_idle_bm,
|
||||
.exit_latency = 2 + 2,
|
||||
.target_residency = 5,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
|
||||
@@ -27,7 +27,6 @@
|
||||
|
||||
#include "iomap.h"
|
||||
#include <plat/board.h>
|
||||
#include <plat/mmc.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
@@ -603,112 +602,6 @@ static inline void omap_init_aes(void) { }
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
|
||||
|
||||
static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
|
||||
*mmc_controller)
|
||||
{
|
||||
if ((mmc_controller->slots[0].switch_pin > 0) && \
|
||||
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
|
||||
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
if ((mmc_controller->slots[0].gpio_wp > 0) && \
|
||||
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
|
||||
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
|
||||
omap_mux_init_signal("sdmmc_cmd", 0);
|
||||
omap_mux_init_signal("sdmmc_clki", 0);
|
||||
omap_mux_init_signal("sdmmc_clko", 0);
|
||||
omap_mux_init_signal("sdmmc_dat0", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir0", 0);
|
||||
omap_mux_init_signal("sdmmc_cmd_dir", 0);
|
||||
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
|
||||
omap_mux_init_signal("sdmmc_dat1", 0);
|
||||
omap_mux_init_signal("sdmmc_dat2", 0);
|
||||
omap_mux_init_signal("sdmmc_dat3", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir1", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir2", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir3", 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use internal loop-back in MMC/SDIO Module Input Clock
|
||||
* selection
|
||||
*/
|
||||
if (mmc_controller->slots[0].internal_clock) {
|
||||
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
||||
v |= (1 << 24);
|
||||
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
}
|
||||
|
||||
void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct omap_hwmod *oh;
|
||||
int id = 0;
|
||||
char *oh_name = "msdi1";
|
||||
char *dev_name = "mmci-omap";
|
||||
|
||||
if (!mmc_data[0]) {
|
||||
pr_err("%s fails: Incomplete platform data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
omap242x_mmc_mux(mmc_data[0]);
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
if (!oh) {
|
||||
pr_err("Could not look up %s\n", oh_name);
|
||||
return;
|
||||
}
|
||||
pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
|
||||
sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
|
||||
if (IS_ERR(pdev))
|
||||
WARN(1, "Can'd build omap_device for %s:%s.\n",
|
||||
dev_name, oh->name);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
|
||||
#define OMAP_HDQ_BASE 0x480B2000
|
||||
static struct resource omap_hdq_resources[] = {
|
||||
{
|
||||
.start = OMAP_HDQ_BASE,
|
||||
.end = OMAP_HDQ_BASE + 0x1C,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_24XX_HDQ_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
static struct platform_device omap_hdq_dev = {
|
||||
.name = "omap_hdq",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(omap_hdq_resources),
|
||||
.resource = omap_hdq_resources,
|
||||
};
|
||||
static inline void omap_hdq_init(void)
|
||||
{
|
||||
if (cpu_is_omap2420())
|
||||
return;
|
||||
|
||||
platform_device_register(&omap_hdq_dev);
|
||||
}
|
||||
#else
|
||||
static inline void omap_hdq_init(void) {}
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
|
||||
defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
|
||||
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
|
||||
@@ -753,7 +646,6 @@ static int __init omap2_init_devices(void)
|
||||
omap_init_mcspi();
|
||||
}
|
||||
omap_init_pmu();
|
||||
omap_hdq_init();
|
||||
omap_init_sti();
|
||||
omap_init_sham();
|
||||
omap_init_aes();
|
||||
|
||||
@@ -22,7 +22,13 @@
|
||||
* 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
#include <plat/hdq1w.h>
|
||||
|
||||
#include "common.h"
|
||||
@@ -70,3 +76,23 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init omap_init_hdq(void)
|
||||
{
|
||||
int id = -1;
|
||||
struct platform_device *pdev;
|
||||
struct omap_hwmod *oh;
|
||||
char *oh_name = "hdq1w";
|
||||
char *devname = "omap_hdq";
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
if (!oh)
|
||||
return 0;
|
||||
|
||||
pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0);
|
||||
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
|
||||
devname, oh->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_hdq);
|
||||
|
||||
@@ -22,11 +22,15 @@
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
#include <plat/mmc.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "control.h"
|
||||
#include "mux.h"
|
||||
|
||||
/*
|
||||
* MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
|
||||
@@ -86,3 +90,72 @@ int omap_msdi_reset(struct omap_hwmod *oh)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
|
||||
|
||||
static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
|
||||
*mmc_controller)
|
||||
{
|
||||
if ((mmc_controller->slots[0].switch_pin > 0) && \
|
||||
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
|
||||
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
if ((mmc_controller->slots[0].gpio_wp > 0) && \
|
||||
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
|
||||
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
|
||||
omap_mux_init_signal("sdmmc_cmd", 0);
|
||||
omap_mux_init_signal("sdmmc_clki", 0);
|
||||
omap_mux_init_signal("sdmmc_clko", 0);
|
||||
omap_mux_init_signal("sdmmc_dat0", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir0", 0);
|
||||
omap_mux_init_signal("sdmmc_cmd_dir", 0);
|
||||
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
|
||||
omap_mux_init_signal("sdmmc_dat1", 0);
|
||||
omap_mux_init_signal("sdmmc_dat2", 0);
|
||||
omap_mux_init_signal("sdmmc_dat3", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir1", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir2", 0);
|
||||
omap_mux_init_signal("sdmmc_dat_dir3", 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use internal loop-back in MMC/SDIO Module Input Clock
|
||||
* selection
|
||||
*/
|
||||
if (mmc_controller->slots[0].internal_clock) {
|
||||
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
||||
v |= (1 << 24);
|
||||
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
}
|
||||
|
||||
void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct omap_hwmod *oh;
|
||||
int id = 0;
|
||||
char *oh_name = "msdi1";
|
||||
char *dev_name = "mmci-omap";
|
||||
|
||||
if (!mmc_data[0]) {
|
||||
pr_err("%s fails: Incomplete platform data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
omap242x_mmc_mux(mmc_data[0]);
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
if (!oh) {
|
||||
pr_err("Could not look up %s\n", oh_name);
|
||||
return;
|
||||
}
|
||||
pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
|
||||
sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
|
||||
if (IS_ERR(pdev))
|
||||
WARN(1, "Can'd build omap_device for %s:%s.\n",
|
||||
dev_name, oh->name);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -255,7 +255,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
pwrdm_pre_transition();
|
||||
pwrdm_pre_transition(NULL);
|
||||
|
||||
/*
|
||||
* Check MPUSS next state and save interrupt controller if needed.
|
||||
@@ -287,7 +287,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
|
||||
wakeup_cpu = smp_processor_id();
|
||||
set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
|
||||
|
||||
pwrdm_post_transition();
|
||||
pwrdm_post_transition(NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -153,6 +153,7 @@
|
||||
#include "prm44xx.h"
|
||||
#include "prminst44xx.h"
|
||||
#include "mux.h"
|
||||
#include "pm.h"
|
||||
|
||||
/* Maximum microseconds to wait for OMAP module to softreset */
|
||||
#define MAX_MODULE_SOFTRESET_WAIT 10000
|
||||
@@ -197,6 +198,9 @@ static LIST_HEAD(omap_hwmod_list);
|
||||
/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
|
||||
static struct omap_hwmod *mpu_oh;
|
||||
|
||||
/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
|
||||
static DEFINE_SPINLOCK(io_chain_lock);
|
||||
|
||||
/*
|
||||
* linkspace: ptr to a buffer that struct omap_hwmod_link records are
|
||||
* allocated from - used to reduce the number of small memory
|
||||
@@ -1758,6 +1762,32 @@ static int _reset(struct omap_hwmod *oh)
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
|
||||
*
|
||||
* Call the appropriate PRM function to clear any logged I/O chain
|
||||
* wakeups and to reconfigure the chain. This apparently needs to be
|
||||
* done upon every mux change. Since hwmods can be concurrently
|
||||
* enabled and idled, hold a spinlock around the I/O chain
|
||||
* reconfiguration sequence. No return value.
|
||||
*
|
||||
* XXX When the PRM code is moved to drivers, this function can be removed,
|
||||
* as the PRM infrastructure should abstract this.
|
||||
*/
|
||||
static void _reconfigure_io_chain(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&io_chain_lock, flags);
|
||||
|
||||
if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
|
||||
omap3xxx_prm_reconfigure_io_chain();
|
||||
else if (cpu_is_omap44xx())
|
||||
omap44xx_prm_reconfigure_io_chain();
|
||||
|
||||
spin_unlock_irqrestore(&io_chain_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* _enable - enable an omap_hwmod
|
||||
* @oh: struct omap_hwmod *
|
||||
@@ -1814,8 +1844,10 @@ static int _enable(struct omap_hwmod *oh)
|
||||
/* Mux pins for device runtime if populated */
|
||||
if (oh->mux && (!oh->mux->enabled ||
|
||||
((oh->_state == _HWMOD_STATE_IDLE) &&
|
||||
oh->mux->pads_dynamic)))
|
||||
oh->mux->pads_dynamic))) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
_add_initiator_dep(oh, mpu_oh);
|
||||
|
||||
@@ -1907,8 +1939,10 @@ static int _idle(struct omap_hwmod *oh)
|
||||
clkdm_hwmod_disable(oh->clkdm, oh);
|
||||
|
||||
/* Mux pins for device idle if populated */
|
||||
if (oh->mux && oh->mux->pads_dynamic)
|
||||
if (oh->mux && oh->mux->pads_dynamic) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
oh->_state = _HWMOD_STATE_IDLE;
|
||||
|
||||
|
||||
@@ -14,6 +14,8 @@
|
||||
*
|
||||
* XXX these should be marked initdata for multi-OMAP kernels
|
||||
*/
|
||||
#include <linux/power/smartreflex.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <plat/cpu.h>
|
||||
@@ -29,8 +31,6 @@
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
#include "smartreflex.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
#include "wd_timer.h"
|
||||
@@ -1357,7 +1357,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap34xx_sr1_hwmod = {
|
||||
.name = "sr1",
|
||||
.name = "smartreflex_mpu_iva",
|
||||
.class = &omap34xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr1_fck",
|
||||
.prcm = {
|
||||
@@ -1375,7 +1375,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap36xx_sr1_hwmod = {
|
||||
.name = "sr1",
|
||||
.name = "smartreflex_mpu_iva",
|
||||
.class = &omap36xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr1_fck",
|
||||
.prcm = {
|
||||
@@ -1402,7 +1402,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap34xx_sr2_hwmod = {
|
||||
.name = "sr2",
|
||||
.name = "smartreflex_core",
|
||||
.class = &omap34xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr2_fck",
|
||||
.prcm = {
|
||||
@@ -1420,7 +1420,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap36xx_sr2_hwmod = {
|
||||
.name = "sr2",
|
||||
.name = "smartreflex_core",
|
||||
.class = &omap36xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr2_fck",
|
||||
.prcm = {
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/power/smartreflex.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/cpu.h>
|
||||
@@ -32,8 +33,6 @@
|
||||
#include <plat/common.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
#include "smartreflex.h"
|
||||
#include "cm1_44xx.h"
|
||||
#include "cm2_44xx.h"
|
||||
#include "prm44xx.h"
|
||||
|
||||
@@ -101,7 +101,7 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
|
||||
static inline void enable_omap3630_toggle_l2_on_restore(void) { }
|
||||
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
|
||||
|
||||
#ifdef CONFIG_OMAP_SMARTREFLEX
|
||||
#ifdef CONFIG_POWER_AVS_OMAP
|
||||
extern int omap_devinit_smartreflex(void);
|
||||
extern void omap_enable_smartreflex_on_init(void);
|
||||
#else
|
||||
|
||||
@@ -70,34 +70,6 @@ void (*omap3_do_wfi_sram)(void);
|
||||
|
||||
static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
|
||||
static struct powerdomain *core_pwrdm, *per_pwrdm;
|
||||
static struct powerdomain *cam_pwrdm;
|
||||
|
||||
static void omap3_enable_io_chain(void)
|
||||
{
|
||||
int timeout = 0;
|
||||
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
|
||||
PM_WKEN);
|
||||
/* Do a readback to assure write has been done */
|
||||
omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
|
||||
|
||||
while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
|
||||
OMAP3430_ST_IO_CHAIN_MASK)) {
|
||||
timeout++;
|
||||
if (timeout > 1000) {
|
||||
pr_err("Wake up daisy chain activation failed.\n");
|
||||
return;
|
||||
}
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
|
||||
WKUP_MOD, PM_WKEN);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap3_disable_io_chain(void)
|
||||
{
|
||||
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
|
||||
PM_WKEN);
|
||||
}
|
||||
|
||||
static void omap3_core_save_context(void)
|
||||
{
|
||||
@@ -299,24 +271,22 @@ void omap_sram_idle(void)
|
||||
/* Enable IO-PAD and IO-CHAIN wakeups */
|
||||
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
|
||||
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
|
||||
if (omap3_has_io_wakeup() &&
|
||||
(per_next_state < PWRDM_POWER_ON ||
|
||||
core_next_state < PWRDM_POWER_ON)) {
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
|
||||
if (omap3_has_io_chain_ctrl())
|
||||
omap3_enable_io_chain();
|
||||
}
|
||||
|
||||
pwrdm_pre_transition();
|
||||
if (mpu_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(mpu_pwrdm);
|
||||
pwrdm_pre_transition(neon_pwrdm);
|
||||
}
|
||||
|
||||
/* PER */
|
||||
if (per_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(per_pwrdm);
|
||||
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
|
||||
omap2_gpio_prepare_for_idle(per_going_off);
|
||||
}
|
||||
|
||||
/* CORE */
|
||||
if (core_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(core_pwrdm);
|
||||
if (core_next_state == PWRDM_POWER_OFF) {
|
||||
omap3_core_save_context();
|
||||
omap3_cm_save_context();
|
||||
@@ -369,26 +339,20 @@ void omap_sram_idle(void)
|
||||
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_VOLTCTRL_OFFSET);
|
||||
pwrdm_post_transition(core_pwrdm);
|
||||
}
|
||||
omap3_intc_resume_idle();
|
||||
|
||||
pwrdm_post_transition();
|
||||
|
||||
/* PER */
|
||||
if (per_next_state < PWRDM_POWER_ON)
|
||||
if (per_next_state < PWRDM_POWER_ON) {
|
||||
omap2_gpio_resume_after_idle();
|
||||
|
||||
/* Disable IO-PAD and IO-CHAIN wakeup */
|
||||
if (omap3_has_io_wakeup() &&
|
||||
(per_next_state < PWRDM_POWER_ON ||
|
||||
core_next_state < PWRDM_POWER_ON)) {
|
||||
omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
|
||||
PM_WKEN);
|
||||
if (omap3_has_io_chain_ctrl())
|
||||
omap3_disable_io_chain();
|
||||
pwrdm_post_transition(per_pwrdm);
|
||||
}
|
||||
|
||||
clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
|
||||
if (mpu_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_post_transition(mpu_pwrdm);
|
||||
pwrdm_post_transition(neon_pwrdm);
|
||||
}
|
||||
}
|
||||
|
||||
static void omap3_pm_idle(void)
|
||||
@@ -754,7 +718,6 @@ int __init omap3_pm_init(void)
|
||||
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
|
||||
per_pwrdm = pwrdm_lookup("per_pwrdm");
|
||||
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
||||
cam_pwrdm = pwrdm_lookup("cam_pwrdm");
|
||||
|
||||
neon_clkdm = clkdm_lookup("neon_clkdm");
|
||||
mpu_clkdm = clkdm_lookup("mpu_clkdm");
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user