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[MIPS] Wind River 4KC PPMC Eval Board Support
Support for the GT-64120-based Wind River 4KC PPMC Evaluation board. Signed-off-by: Rongkai.Zhan <Rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Mark.Zhan
Ralf Baechle
@@ -327,6 +327,27 @@ config MIPS_SEAD
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This enables support for the MIPS Technologies SEAD evaluation
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board.
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config WR_PPMC
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bool "Support for Wind River PPMC board"
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select IRQ_CPU
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select MIPS_GT64120
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_NEVADA
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select SYS_HAS_CPU_RM7000
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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This enables support for the Wind River MIPS32 4KC PPMC evaluation
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board, which is based on GT64120 bridge chip.
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config MIPS_SIM
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bool 'MIPS simulator (MIPSsim)'
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select DMA_NONCOHERENT
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@@ -286,6 +286,13 @@ core-$(CONFIG_MIPS_EV96100) += arch/mips/galileo-boards/ev96100/
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cflags-$(CONFIG_MIPS_EV96100) += -Iinclude/asm-mips/mach-ev96100
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load-$(CONFIG_MIPS_EV96100) += 0xffffffff80100000
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#
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# Wind River PPMC Board (4KC + GT64120)
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#
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core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
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cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
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load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
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#
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# Globespan IVR eval board with QED 5231 CPU
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#
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,14 @@
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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# Copyright 2006 Wind River System, Inc.
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# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
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#
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# Makefile for the Wind River MIPS 4KC PPMC Eval Board
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#
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obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o
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EXTRA_AFLAGS := $(CFLAGS)
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@@ -0,0 +1,59 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
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* Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/mach-wrppmc/mach-gt64120.h>
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.align 5
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.set noat
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NESTED(handle_IRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI # Important: mark KERNEL mode !
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.set at
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mfc0 t0, CP0_CAUSE # get pending interrupts
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mfc0 t1, CP0_STATUS # get enabled interrupts
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and t0, t0, t1 # get allowed interrupts
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andi t0, t0, 0xFF00
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beqz t0, 1f
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move a1, sp # Prepare 'struct pt_regs *regs' pointer
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andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer
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bnez t1, handle_cputimer_irq
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andi t1, t0, CAUSEF_IP6 # UART 16550 port
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bnez t1, handle_uart_irq
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andi t1, t0, CAUSEF_IP3 # PCI INT_A
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bnez t1, handle_pci_intA_irq
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/* wrong alarm or masked ... */
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1: j spurious_interrupt
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nop
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END(handle_IRQ)
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.align 5
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handle_cputimer_irq:
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li a0, WRPPMC_MIPS_TIMER_IRQ
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jal do_IRQ
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j ret_from_irq
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.align 5
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handle_uart_irq:
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li a0, WRPPMC_UART16550_IRQ
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jal do_IRQ
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j ret_from_irq
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.align 5
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handle_pci_intA_irq:
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li a0, WRPPMC_PCI_INTA_IRQ
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jal do_IRQ
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j ret_from_irq
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@@ -0,0 +1,63 @@
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/*
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* irq.c: GT64120 Interrupt Controller
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*
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* Copyright (C) 2006, Wind River System Inc.
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* Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/irq_cpu.h>
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#include <asm/gt64120.h>
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extern asmlinkage void handle_IRQ(void);
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/**
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* Initialize GT64120 Interrupt Controller
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*/
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void gt64120_init_pic(void)
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{
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/* clear CPU Interrupt Cause Registers */
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GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
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GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
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/* Disable all interrupts from GT64120 bridge chip */
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GT_WRITE(GT_INTRMASK_OFS, 0x00);
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GT_WRITE(GT_HINTRMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
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}
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void __init arch_init_irq(void)
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{
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/* enable all CPU interrupt bits. */
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set_c0_status(ST0_IM); /* IE bit is still 0 */
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/* Install MIPS Interrupt Trap Vector */
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set_except_vector(0, handle_IRQ);
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/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
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mips_cpu_irq_init(0);
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gt64120_init_pic();
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}
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@@ -0,0 +1,53 @@
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/*
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* pci.c: GT64120 PCI support.
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*
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* Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/gt64120.h>
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extern struct pci_ops gt64120_pci_ops;
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static struct resource pci0_io_resource = {
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.name = "pci_0 io",
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.start = GT_PCI_IO_BASE,
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.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci0_mem_resource = {
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.name = "pci_0 memory",
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.start = GT_PCI_MEM_BASE,
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.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller hose_0 = {
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.pci_ops = >64120_pci_ops,
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.io_resource = &pci0_io_resource,
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.mem_resource = &pci0_mem_resource,
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};
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static int __init gt64120_pci_init(void)
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{
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u32 tmp;
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tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
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tmp = GT_READ(GT_PCI0_BARE_OFS);
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/* reset the whole PCI I/O space range */
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ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
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register_pci_controller(&hose_0);
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return 0;
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}
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arch_initcall(gt64120_pci_init);
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@@ -0,0 +1,50 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997 Ralf Baechle
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*/
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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void wrppmc_machine_restart(char *command)
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{
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/*
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* Ouch, we're still alive ... This time we take the silver bullet ...
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* ... and find that we leave the hardware in a state in which the
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* kernel in the flush locks up somewhen during of after the PCI
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* detection stuff.
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*/
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local_irq_disable();
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set_c0_status(ST0_BEV | ST0_ERL);
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change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
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flush_cache_all();
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write_c0_wired(0);
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__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
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}
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void wrppmc_machine_halt(void)
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{
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local_irq_disable();
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printk(KERN_NOTICE "You can safely turn off the power\n");
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while (1) {
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__asm__(
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".set\tmips3\n\t"
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"wait\n\t"
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".set\tmips0"
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);
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}
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}
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void wrppmc_machine_power_off(void)
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{
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wrppmc_machine_halt();
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}
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@@ -0,0 +1,173 @@
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/*
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* setup.c: Setup pointers to hardware dependent routines.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/gt64120.h>
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unsigned long gt64120_base = KSEG1ADDR(0x14000000);
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#ifdef WRPPMC_EARLY_DEBUG
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static volatile unsigned char * wrppmc_led = \
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(volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
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/*
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* PPMC LED control register:
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* -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
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* -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
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* -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
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*/
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void wrppmc_led_on(int mask)
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{
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unsigned char value = *wrppmc_led;
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value &= (0xF8 | mask);
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*wrppmc_led = value;
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}
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/* If mask = 0, turn off all LEDs */
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void wrppmc_led_off(int mask)
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{
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unsigned char value = *wrppmc_led;
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value |= (0x7 & mask);
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*wrppmc_led = value;
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}
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/*
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* We assume that bootloader has initialized UART16550 correctly
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*/
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void __init wrppmc_early_putc(char ch)
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{
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static volatile unsigned char *wrppmc_uart = \
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(volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
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unsigned char value;
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/* Wait until Transmit-Holding-Register is empty */
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while (1) {
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value = *(wrppmc_uart + 5);
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if (value & 0x20)
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break;
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}
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*wrppmc_uart = ch;
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}
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void __init wrppmc_early_printk(const char *fmt, ...)
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{
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static char pbuf[256] = {'\0', };
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char *ch = pbuf;
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va_list args;
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unsigned int i;
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memset(pbuf, 0, 256);
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va_start(args, fmt);
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i = vsprintf(pbuf, fmt, args);
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va_end(args);
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/* Print the string */
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while (*ch != '\0') {
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wrppmc_early_putc(*ch);
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/* if print '\n', also print '\r' */
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if (*ch++ == '\n')
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wrppmc_early_putc('\r');
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}
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}
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#endif /* WRPPMC_EARLY_DEBUG */
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unsigned long __init prom_free_prom_memory(void)
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{
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return 0;
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}
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#ifdef CONFIG_SERIAL_8250
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static void wrppmc_setup_serial(void)
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{
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struct uart_port up;
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memset(&up, 0x00, sizeof(struct uart_port));
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/*
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* A note about mapbase/membase
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* -) mapbase is the physical address of the IO port.
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* -) membase is an 'ioremapped' cookie.
|
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*/
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up.line = 0;
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up.type = PORT_16550;
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up.iotype = UPIO_MEM;
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up.mapbase = WRPPMC_UART16550_BASE;
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up.membase = ioremap(up.mapbase, 8);
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up.irq = WRPPMC_UART16550_IRQ;
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up.uartclk = WRPPMC_UART16550_CLOCK;
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up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
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up.regshift = 0;
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early_serial_setup(&up);
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}
|
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#endif
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void __init plat_setup(void)
|
||||
{
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||||
extern void wrppmc_time_init(void);
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extern void wrppmc_timer_setup(struct irqaction *);
|
||||
extern void wrppmc_machine_restart(char *command);
|
||||
extern void wrppmc_machine_halt(void);
|
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extern void wrppmc_machine_power_off(void);
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||||
|
||||
_machine_restart = wrppmc_machine_restart;
|
||||
_machine_halt = wrppmc_machine_halt;
|
||||
pm_power_off = wrppmc_machine_power_off;
|
||||
|
||||
/* Use MIPS Count/Compare Timer */
|
||||
board_time_init = wrppmc_time_init;
|
||||
board_timer_setup = wrppmc_timer_setup;
|
||||
|
||||
/* This makes the operations of 'in/out[bwl]' to the
|
||||
* physical address ( < KSEG0) can work via KSEG1
|
||||
*/
|
||||
set_io_port_base(KSEG1);
|
||||
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
wrppmc_setup_serial();
|
||||
#endif
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
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return "Wind River PPMC (GT64120)";
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes basic routines and structures pointers, memory size (as
|
||||
* given by the bios and saves the command line.
|
||||
*/
|
||||
void __init prom_init(void)
|
||||
{
|
||||
mips_machgroup = MACH_GROUP_GALILEO;
|
||||
mips_machtype = MACH_EV64120A;
|
||||
|
||||
add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
|
||||
add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
|
||||
|
||||
wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
|
||||
WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
|
||||
}
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* time.c: MIPS CPU Count/Compare timer hookup
|
||||
*
|
||||
* Author: Mark.Zhan, <rongkai.zhan@windriver.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2006, Wind River System Inc.
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/param.h> /* for HZ */
|
||||
#include <linux/irq.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
|
||||
|
||||
void __init wrppmc_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
/* Install ISR for timer interrupt */
|
||||
setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
|
||||
|
||||
/* to generate the first timer interrupt */
|
||||
write_c0_compare(mips_hpt_frequency/HZ);
|
||||
write_c0_count(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
|
||||
*
|
||||
* NOTE: We disable all GT64120 timers, and use MIPS processor internal
|
||||
* timer as the source of kernel clock tick.
|
||||
*/
|
||||
void __init wrppmc_time_init(void)
|
||||
{
|
||||
/* Disable GT64120 timers */
|
||||
GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
|
||||
GT_WRITE(GT_TC0_OFS, 0x00);
|
||||
GT_WRITE(GT_TC1_OFS, 0x00);
|
||||
GT_WRITE(GT_TC2_OFS, 0x00);
|
||||
GT_WRITE(GT_TC3_OFS, 0x00);
|
||||
|
||||
/* Use MIPS compare/count internal timer */
|
||||
mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
|
||||
}
|
||||
@@ -57,3 +57,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
|
||||
obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
|
||||
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
|
||||
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
|
||||
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* fixup-wrppmc.c: PPMC board specific PCI fixup
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
/* PCI interrupt pins */
|
||||
#define PCI_INTA 1
|
||||
#define PCI_INTB 2
|
||||
#define PCI_INTC 3
|
||||
#define PCI_INTD 4
|
||||
|
||||
#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
|
||||
|
||||
static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
|
||||
/* 0 INTA INTB INTC INTD */
|
||||
[0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
|
||||
[6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
|
||||
};
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
return pci_irq_tab[slot][pin];
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* This is a direct copy of the ev96100.h file, with a global
|
||||
* search and replace. The numbers are the same.
|
||||
*
|
||||
* The reason I'm duplicating this is so that the 64120/96100
|
||||
* defines won't be confusing in the source code.
|
||||
*/
|
||||
#ifndef __ASM_MIPS_GT64120_H
|
||||
#define __ASM_MIPS_GT64120_H
|
||||
|
||||
/*
|
||||
* This is the CPU physical memory map of PPMC Board:
|
||||
*
|
||||
* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
|
||||
* 0x1C000000-0x1C000000 - LED (CS0)
|
||||
* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
|
||||
* 0x1F000000-0x1F000000 - MailBox (CS3)
|
||||
* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
|
||||
*/
|
||||
|
||||
#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
|
||||
#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
|
||||
|
||||
#define WRPPMC_UART16550_BASE 0x1C800000
|
||||
#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
|
||||
|
||||
#define WRPPMC_LED_BASE 0x1C000000
|
||||
#define WRPPMC_MBOX_BASE 0x1F000000
|
||||
|
||||
#define WRPPMC_BOOTROM_BASE 0x1FC00000
|
||||
#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
|
||||
|
||||
#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
|
||||
#define WRPPMC_UART16550_IRQ 6
|
||||
#define WRPPMC_PCI_INTA_IRQ 3
|
||||
|
||||
/*
|
||||
* PCI Bus I/O and Memory resources allocation
|
||||
*
|
||||
* NOTE: We only have PCI_0 hose interface
|
||||
*/
|
||||
#define GT_PCI_MEM_BASE 0x13000000UL
|
||||
#define GT_PCI_MEM_SIZE 0x02000000UL
|
||||
#define GT_PCI_IO_BASE 0x11000000UL
|
||||
#define GT_PCI_IO_SIZE 0x02000000UL
|
||||
#define GT_ISA_IO_BASE PCI_IO_BASE
|
||||
|
||||
/*
|
||||
* PCI interrupts will come in on either the INTA or INTD interrups lines,
|
||||
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
|
||||
* boards, they all either come in on IntD or they all come in on IntA, they
|
||||
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
|
||||
* "requested" interrupt numbers and go through the list whenever we get an
|
||||
* IntA/D.
|
||||
*
|
||||
* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
|
||||
* INTD is 11.
|
||||
*/
|
||||
#define GT_TIMER 4
|
||||
#define GT_INTA 2
|
||||
#define GT_INTD 5
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* GT64120 internal register space base address
|
||||
*/
|
||||
extern unsigned long gt64120_base;
|
||||
|
||||
#define GT64120_BASE (gt64120_base)
|
||||
|
||||
/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
|
||||
#undef WRPPMC_EARLY_DEBUG
|
||||
|
||||
#ifdef WRPPMC_EARLY_DEBUG
|
||||
extern void wrppmc_led_on(int mask);
|
||||
extern void wrppmc_led_off(int mask);
|
||||
extern void wrppmc_early_printk(const char *fmt, ...);
|
||||
#else
|
||||
#define wrppmc_early_printk(fmt, ...) do {} while (0)
|
||||
#endif /* WRPPMC_EARLY_DEBUG */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_MIPS_GT64120_H */
|
||||
Reference in New Issue
Block a user