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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
This commit is contained in:
+8
-1
@@ -1120,6 +1120,13 @@ W: http://wireless.kernel.org/en/users/Drivers/ar9170
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||||
S: Maintained
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||||
F: drivers/net/wireless/ath/ar9170/
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CARL9170 LINUX COMMUNITY WIRELESS DRIVER
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M: Christian Lamparter <chunkeey@googlemail.com>
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L: linux-wireless@vger.kernel.org
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W: http://wireless.kernel.org/en/users/Drivers/carl9170
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S: Maintained
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F: drivers/net/wireless/ath/carl9170/
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ATK0110 HWMON DRIVER
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M: Luca Tettamanti <kronos.it@gmail.com>
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L: lm-sensors@lm-sensors.org
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@@ -6427,7 +6434,7 @@ W: http://wireless.kernel.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
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S: Maintained
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F: drivers/net/wireless/wl12xx/wl1271*
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F: include/linux/spi/wl12xx.h
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F: include/linux/wl12xx.h
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WL3501 WIRELESS PCMCIA CARD DRIVER
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M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
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@@ -25,7 +25,7 @@
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#include <linux/spi/ads7846.h>
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#include <linux/regulator/machine.h>
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#include <linux/i2c/twl.h>
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#include <linux/spi/wl12xx.h>
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#include <linux/wl12xx.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <linux/leds.h>
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@@ -14,7 +14,7 @@
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#include <linux/input.h>
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#include <linux/input/matrix_keypad.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/wl12xx.h>
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#include <linux/wl12xx.h>
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#include <linux/i2c.h>
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#include <linux/i2c/twl.h>
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#include <linux/clk.h>
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@@ -16,6 +16,8 @@
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#include <linux/gpio.h>
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#include <linux/i2c/twl.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/fixed.h>
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#include <linux/wl12xx.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@@ -27,6 +29,9 @@
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#include "mux.h"
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#include "hsmmc.h"
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#define OMAP_ZOOM_WLAN_PMENA_GPIO (101)
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#define OMAP_ZOOM_WLAN_IRQ_GPIO (162)
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/* Zoom2 has Qwerty keyboard*/
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static int board_keymap[] = {
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KEY(0, 0, KEY_E),
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@@ -106,6 +111,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
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.supply = "vmmc",
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};
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static struct regulator_consumer_supply zoom_vmmc3_supply = {
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.supply = "vmmc",
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.dev_name = "mmci-omap-hs.2",
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};
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/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
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static struct regulator_init_data zoom_vmmc1 = {
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.constraints = {
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@@ -151,6 +161,38 @@ static struct regulator_init_data zoom_vsim = {
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.consumer_supplies = &zoom_vsim_supply,
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};
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static struct regulator_init_data zoom_vmmc3 = {
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.constraints = {
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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},
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.num_consumer_supplies = 1,
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.consumer_supplies = &zoom_vmmc3_supply,
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};
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static struct fixed_voltage_config zoom_vwlan = {
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.supply_name = "vwl1271",
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.microvolts = 1800000, /* 1.8V */
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.gpio = OMAP_ZOOM_WLAN_PMENA_GPIO,
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.startup_delay = 70000, /* 70msec */
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.enable_high = 1,
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.enabled_at_boot = 0,
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.init_data = &zoom_vmmc3,
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};
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static struct platform_device omap_vwlan_device = {
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.name = "reg-fixed-voltage",
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.id = 1,
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.dev = {
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.platform_data = &zoom_vwlan,
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},
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};
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struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
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.irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
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/* ZOOM ref clock is 26 MHz */
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.board_ref_clock = 1,
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};
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static struct omap2_hsmmc_info mmc[] __initdata = {
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{
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.name = "external",
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@@ -168,6 +210,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
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.nonremovable = true,
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.power_saving = true,
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},
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{
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.name = "wl1271",
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.mmc = 3,
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.wires = 4,
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.gpio_wp = -EINVAL,
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.gpio_cd = -EINVAL,
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.nonremovable = true,
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},
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{} /* Terminator */
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};
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@@ -279,7 +329,11 @@ static void enable_board_wakeup_source(void)
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void __init zoom_peripherals_init(void)
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{
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if (wl12xx_set_platform_data(&omap_zoom_wlan_data))
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pr_err("error setting wl12xx data\n");
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omap_i2c_init();
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platform_device_register(&omap_vwlan_device);
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usb_musb_init(&musb_board_data);
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enable_board_wakeup_source();
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}
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@@ -50,5 +50,7 @@ obj-$(CONFIG_ATH_COMMON) += ath/
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obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o
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obj-$(CONFIG_WL12XX) += wl12xx/
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# small builtin driver bit
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obj-$(CONFIG_WL12XX_PLATFORM_DATA) += wl12xx/wl12xx_platform_data.o
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obj-$(CONFIG_IWM) += iwmc3200wifi/
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@@ -105,7 +105,7 @@ static struct pci_driver airo_driver = {
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of statistics in the /proc filesystem */
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#define IGNLABEL(comment) NULL
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static char *statsLabels[] = {
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static const char *statsLabels[] = {
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"RxOverrun",
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IGNLABEL("RxPlcpCrcErr"),
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IGNLABEL("RxPlcpFormatErr"),
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@@ -932,7 +932,7 @@ typedef struct aironet_ioctl {
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unsigned char __user *data; // d-data
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} aironet_ioctl;
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static char swversion[] = "2.1";
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static const char swversion[] = "2.1";
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#endif /* CISCO_EXT */
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#define NUM_MODULES 2
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@@ -1374,7 +1374,7 @@ static int micsetup(struct airo_info *ai) {
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return SUCCESS;
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}
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static char micsnap[] = {0xAA,0xAA,0x03,0x00,0x40,0x96,0x00,0x02};
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static const u8 micsnap[] = {0xAA,0xAA,0x03,0x00,0x40,0x96,0x00,0x02};
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/*===========================================================================
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* Description: Mic a packet
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@@ -5023,7 +5023,7 @@ static void proc_config_on_close(struct inode *inode, struct file *file)
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airo_config_commit(dev, NULL, NULL, NULL);
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}
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static char *get_rmode(__le16 mode)
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static const char *get_rmode(__le16 mode)
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{
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switch(mode & RXMODE_MASK) {
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case RXMODE_RFMON: return "rfmon";
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@@ -25,5 +25,6 @@ config ATH_DEBUG
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source "drivers/net/wireless/ath/ath5k/Kconfig"
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source "drivers/net/wireless/ath/ath9k/Kconfig"
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source "drivers/net/wireless/ath/ar9170/Kconfig"
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source "drivers/net/wireless/ath/carl9170/Kconfig"
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endif
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@@ -1,11 +1,13 @@
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obj-$(CONFIG_ATH5K) += ath5k/
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obj-$(CONFIG_ATH9K_HW) += ath9k/
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obj-$(CONFIG_AR9170_USB) += ar9170/
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obj-$(CONFIG_CARL9170) += carl9170/
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obj-$(CONFIG_ATH_COMMON) += ath.o
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ath-objs := main.o \
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regd.o \
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hw.o
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hw.o \
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key.o
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ath-$(CONFIG_ATH_DEBUG) += debug.o
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@@ -71,6 +71,32 @@ struct ath_regulatory {
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struct reg_dmn_pair_mapping *regpair;
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};
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enum ath_crypt_caps {
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ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
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ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
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};
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struct ath_keyval {
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u8 kv_type;
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u8 kv_pad;
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u16 kv_len;
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u8 kv_val[16]; /* TK */
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u8 kv_mic[8]; /* Michael MIC key */
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u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
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* supports both MIC keys in the same key cache entry;
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* in that case, kv_mic is the RX key) */
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};
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enum ath_cipher {
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ATH_CIPHER_WEP = 0,
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ATH_CIPHER_AES_OCB = 1,
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ATH_CIPHER_AES_CCM = 2,
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ATH_CIPHER_CKIP = 3,
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ATH_CIPHER_TKIP = 4,
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ATH_CIPHER_CLR = 5,
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ATH_CIPHER_MIC = 127
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};
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/**
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* struct ath_ops - Register read/write operations
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*
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@@ -120,7 +146,7 @@ struct ath_common {
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u32 keymax;
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DECLARE_BITMAP(keymap, ATH_KEYMAX);
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DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
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u8 splitmic;
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enum ath_crypt_caps crypt_caps;
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struct ath_regulatory regulatory;
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const struct ath_ops *ops;
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@@ -132,5 +158,11 @@ struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
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gfp_t gfp_mask);
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void ath_hw_setbssidmask(struct ath_common *common);
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void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
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int ath_key_config(struct ath_common *common,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key);
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bool ath_hw_keyreset(struct ath_common *common, u16 entry);
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#endif /* ATH_H */
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@@ -206,6 +206,8 @@
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#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
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#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
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#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
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#define AR5K_INIT_CARR_SENSE_EN 1
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/*Swap RX/TX Descriptor for big endian archs*/
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@@ -256,8 +258,6 @@
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(AR5K_INIT_PROG_IFS_TURBO) \
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)
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/* token to use for aifs, cwmin, cwmax in MadWiFi */
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#define AR5K_TXQ_USEDEFAULT ((u32) -1)
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/* GENERIC CHIPSET DEFINITIONS */
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@@ -528,9 +528,9 @@ struct ath5k_txq_info {
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enum ath5k_tx_queue tqi_type;
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enum ath5k_tx_queue_subtype tqi_subtype;
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u16 tqi_flags; /* Tx queue flags (see above) */
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u32 tqi_aifs; /* Arbitrated Interframe Space */
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s32 tqi_cw_min; /* Minimum Contention Window */
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s32 tqi_cw_max; /* Maximum Contention Window */
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u8 tqi_aifs; /* Arbitrated Interframe Space */
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u16 tqi_cw_min; /* Minimum Contention Window */
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u16 tqi_cw_max; /* Maximum Contention Window */
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u32 tqi_cbr_period; /* Constant bit rate period */
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u32 tqi_cbr_overflow_limit;
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u32 tqi_burst_time;
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@@ -1028,8 +1028,6 @@ struct ath5k_hw {
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bool ah_turbo;
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bool ah_calibration;
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bool ah_single_chip;
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bool ah_aes_support;
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bool ah_combined_mic;
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enum ath5k_version ah_version;
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enum ath5k_radio ah_radio;
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@@ -1044,9 +1042,6 @@ struct ath5k_hw {
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#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
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u32 ah_atim_window;
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u32 ah_aifs;
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u32 ah_cw_min;
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u32 ah_cw_max;
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u32 ah_limit_tx_retries;
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u8 ah_coverage_class;
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@@ -1207,11 +1202,6 @@ void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
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unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
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unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
|
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unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
|
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/* Key table (WEP) functions */
|
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int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
|
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int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
|
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const struct ieee80211_key_conf *key, const u8 *mac);
|
||||
int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
|
||||
|
||||
/* Queue Control Unit, DFS Control Unit Functions */
|
||||
int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
|
||||
|
||||
@@ -119,8 +119,6 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
|
||||
ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
|
||||
ah->ah_imr = 0;
|
||||
ah->ah_atim_window = 0;
|
||||
ah->ah_aifs = AR5K_TUNE_AIFS;
|
||||
ah->ah_cw_min = AR5K_TUNE_CWMIN;
|
||||
ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
|
||||
ah->ah_software_retry = false;
|
||||
ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
|
||||
@@ -314,12 +312,16 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
|
||||
}
|
||||
|
||||
/* Crypto settings */
|
||||
ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
|
||||
(ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
|
||||
!AR5K_EEPROM_AES_DIS(ee->ee_misc5));
|
||||
common->keymax = (sc->ah->ah_version == AR5K_AR5210 ?
|
||||
AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
|
||||
|
||||
if (srev >= AR5K_SREV_AR5212_V4 &&
|
||||
(ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
|
||||
!AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
|
||||
common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
|
||||
|
||||
if (srev >= AR5K_SREV_AR2414) {
|
||||
ah->ah_combined_mic = true;
|
||||
common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
|
||||
AR5K_MISC_MODE_COMBINED_MIC);
|
||||
}
|
||||
|
||||
+1004
-1007
File diff suppressed because it is too large
Load Diff
@@ -60,6 +60,9 @@
|
||||
#define ATH_TXBUF 200 /* number of TX buffers */
|
||||
#define ATH_BCBUF 1 /* number of beacon buffers */
|
||||
|
||||
#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
|
||||
#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
|
||||
|
||||
struct ath5k_buf {
|
||||
struct list_head list;
|
||||
struct ath5k_desc *desc; /* virtual addr of desc */
|
||||
@@ -83,6 +86,9 @@ struct ath5k_txq {
|
||||
struct list_head q; /* transmit queue */
|
||||
spinlock_t lock; /* lock on q and link */
|
||||
bool setup;
|
||||
int txq_len; /* number of queued buffers */
|
||||
bool txq_poll_mark;
|
||||
unsigned int txq_stuck; /* informational counter */
|
||||
};
|
||||
|
||||
#define ATH5K_LED_MAX_NAME_LEN 31
|
||||
@@ -204,7 +210,6 @@ struct ath5k_softc {
|
||||
spinlock_t txbuflock;
|
||||
unsigned int txbuf_len; /* buf count in txbuf list */
|
||||
struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
|
||||
struct ath5k_txq *txq; /* main tx queue */
|
||||
struct tasklet_struct txtq; /* tx intr tasklet */
|
||||
struct ath5k_led tx_led; /* tx led */
|
||||
|
||||
@@ -230,6 +235,8 @@ struct ath5k_softc {
|
||||
|
||||
struct ath5k_ani_state ani_state;
|
||||
struct tasklet_struct ani_tasklet; /* ANI calibration */
|
||||
|
||||
struct delayed_work tx_complete_work;
|
||||
};
|
||||
|
||||
#define ath5k_hw_hasbssidmask(_ah) \
|
||||
|
||||
@@ -763,7 +763,7 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
|
||||
|
||||
struct ath5k_txq *txq;
|
||||
struct ath5k_buf *bf, *bf0;
|
||||
int i, n = 0;
|
||||
int i, n;
|
||||
|
||||
len += snprintf(buf+len, sizeof(buf)-len,
|
||||
"available txbuffers: %d\n", sc->txbuf_len);
|
||||
@@ -777,9 +777,16 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
|
||||
if (!txq->setup)
|
||||
continue;
|
||||
|
||||
n = 0;
|
||||
spin_lock_bh(&txq->lock);
|
||||
list_for_each_entry_safe(bf, bf0, &txq->q, list)
|
||||
n++;
|
||||
len += snprintf(buf+len, sizeof(buf)-len, " len: %d\n", n);
|
||||
spin_unlock_bh(&txq->lock);
|
||||
|
||||
len += snprintf(buf+len, sizeof(buf)-len,
|
||||
" len: %d bufs: %d\n", txq->txq_len, n);
|
||||
len += snprintf(buf+len, sizeof(buf)-len,
|
||||
" stuck: %d\n", txq->txq_stuck);
|
||||
}
|
||||
|
||||
if (len > sizeof(buf))
|
||||
|
||||
@@ -640,197 +640,6 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*********************\
|
||||
* Key table functions *
|
||||
\*********************/
|
||||
|
||||
/*
|
||||
* Reset a key entry on the table
|
||||
*/
|
||||
int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
|
||||
{
|
||||
unsigned int i, type;
|
||||
u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
|
||||
|
||||
AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
|
||||
|
||||
type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
|
||||
|
||||
for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
|
||||
|
||||
/* Reset associated MIC entry if TKIP
|
||||
* is enabled located at offset (entry + 64) */
|
||||
if (type == AR5K_KEYTABLE_TYPE_TKIP) {
|
||||
AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE);
|
||||
for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
|
||||
ath5k_hw_reg_write(ah, 0,
|
||||
AR5K_KEYTABLE_OFF(micentry, i));
|
||||
}
|
||||
|
||||
/*
|
||||
* Set NULL encryption on AR5212+
|
||||
*
|
||||
* Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
|
||||
* AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
|
||||
*
|
||||
* Note2: Windows driver (ndiswrapper) sets this to
|
||||
* 0x00000714 instead of 0x00000007
|
||||
*/
|
||||
if (ah->ah_version >= AR5K_AR5211) {
|
||||
ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
|
||||
AR5K_KEYTABLE_TYPE(entry));
|
||||
|
||||
if (type == AR5K_KEYTABLE_TYPE_TKIP) {
|
||||
ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
|
||||
AR5K_KEYTABLE_TYPE(micentry));
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static
|
||||
int ath5k_keycache_type(const struct ieee80211_key_conf *key)
|
||||
{
|
||||
switch (key->cipher) {
|
||||
case WLAN_CIPHER_SUITE_TKIP:
|
||||
return AR5K_KEYTABLE_TYPE_TKIP;
|
||||
case WLAN_CIPHER_SUITE_CCMP:
|
||||
return AR5K_KEYTABLE_TYPE_CCM;
|
||||
case WLAN_CIPHER_SUITE_WEP40:
|
||||
return AR5K_KEYTABLE_TYPE_40;
|
||||
case WLAN_CIPHER_SUITE_WEP104:
|
||||
return AR5K_KEYTABLE_TYPE_104;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set a key entry on the table
|
||||
*/
|
||||
int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
|
||||
const struct ieee80211_key_conf *key, const u8 *mac)
|
||||
{
|
||||
unsigned int i;
|
||||
int keylen;
|
||||
__le32 key_v[5] = {};
|
||||
__le32 key0 = 0, key1 = 0;
|
||||
__le32 *rxmic, *txmic;
|
||||
int keytype;
|
||||
u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
|
||||
bool is_tkip;
|
||||
const u8 *key_ptr;
|
||||
|
||||
is_tkip = (key->cipher == WLAN_CIPHER_SUITE_TKIP);
|
||||
|
||||
/*
|
||||
* key->keylen comes in from mac80211 in bytes.
|
||||
* TKIP is 128 bit + 128 bit mic
|
||||
*/
|
||||
keylen = (is_tkip) ? (128 / 8) : key->keylen;
|
||||
|
||||
if (entry > AR5K_KEYTABLE_SIZE ||
|
||||
(is_tkip && micentry > AR5K_KEYTABLE_SIZE))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (unlikely(keylen > 16))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
keytype = ath5k_keycache_type(key);
|
||||
if (keytype < 0)
|
||||
return keytype;
|
||||
|
||||
/*
|
||||
* each key block is 6 bytes wide, written as pairs of
|
||||
* alternating 32 and 16 bit le values.
|
||||
*/
|
||||
key_ptr = key->key;
|
||||
for (i = 0; keylen >= 6; keylen -= 6) {
|
||||
memcpy(&key_v[i], key_ptr, 6);
|
||||
i += 2;
|
||||
key_ptr += 6;
|
||||
}
|
||||
if (keylen)
|
||||
memcpy(&key_v[i], key_ptr, keylen);
|
||||
|
||||
/* intentionally corrupt key until mic is installed */
|
||||
if (is_tkip) {
|
||||
key0 = key_v[0] = ~key_v[0];
|
||||
key1 = key_v[1] = ~key_v[1];
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(key_v); i++)
|
||||
ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
|
||||
AR5K_KEYTABLE_OFF(entry, i));
|
||||
|
||||
ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
|
||||
|
||||
if (is_tkip) {
|
||||
/* Install rx/tx MIC */
|
||||
rxmic = (__le32 *) &key->key[16];
|
||||
txmic = (__le32 *) &key->key[24];
|
||||
|
||||
if (ah->ah_combined_mic) {
|
||||
key_v[0] = rxmic[0];
|
||||
key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16);
|
||||
key_v[2] = rxmic[1];
|
||||
key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff);
|
||||
key_v[4] = txmic[1];
|
||||
} else {
|
||||
key_v[0] = rxmic[0];
|
||||
key_v[1] = 0;
|
||||
key_v[2] = rxmic[1];
|
||||
key_v[3] = 0;
|
||||
key_v[4] = 0;
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(key_v); i++)
|
||||
ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
|
||||
AR5K_KEYTABLE_OFF(micentry, i));
|
||||
|
||||
ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
|
||||
AR5K_KEYTABLE_TYPE(micentry));
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
|
||||
|
||||
/* restore first 2 words of key */
|
||||
ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
|
||||
AR5K_KEYTABLE_OFF(entry, 0));
|
||||
ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
|
||||
AR5K_KEYTABLE_OFF(entry, 1));
|
||||
}
|
||||
|
||||
return ath5k_hw_set_key_lladdr(ah, entry, mac);
|
||||
}
|
||||
|
||||
int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
|
||||
{
|
||||
u32 low_id, high_id;
|
||||
|
||||
/* Invalid entry (key table overflow) */
|
||||
AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
|
||||
|
||||
/*
|
||||
* MAC may be NULL if it's a broadcast key. In this case no need to
|
||||
* to compute get_unaligned_le32 and get_unaligned_le16 as we
|
||||
* already know it.
|
||||
*/
|
||||
if (!mac) {
|
||||
low_id = 0xffffffff;
|
||||
high_id = 0xffff | AR5K_KEYTABLE_VALID;
|
||||
} else {
|
||||
low_id = get_unaligned_le32(mac);
|
||||
high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID;
|
||||
}
|
||||
|
||||
ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
|
||||
ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
|
||||
*
|
||||
|
||||
@@ -1377,7 +1377,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
|
||||
|
||||
/* protect against divide by 0 and loss of sign bits */
|
||||
if (i_coffd == 0 || q_coffd < 2)
|
||||
return -1;
|
||||
return 0;
|
||||
|
||||
i_coff = (-iq_corr) / i_coffd;
|
||||
i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
|
||||
|
||||
@@ -35,25 +35,59 @@ int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure cw is a power of 2 minus 1 and smaller than 1024
|
||||
*/
|
||||
static u16 ath5k_cw_validate(u16 cw_req)
|
||||
{
|
||||
u32 cw = 1;
|
||||
cw_req = min(cw_req, (u16)1023);
|
||||
|
||||
while (cw < cw_req)
|
||||
cw = (cw << 1) | 1;
|
||||
|
||||
return cw;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set properties for a transmit queue
|
||||
*/
|
||||
int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
|
||||
const struct ath5k_txq_info *queue_info)
|
||||
const struct ath5k_txq_info *qinfo)
|
||||
{
|
||||
struct ath5k_txq_info *qi;
|
||||
|
||||
AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
|
||||
|
||||
if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
|
||||
qi = &ah->ah_txq[queue];
|
||||
|
||||
if (qi->tqi_type == AR5K_TX_QUEUE_INACTIVE)
|
||||
return -EIO;
|
||||
|
||||
memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
|
||||
/* copy and validate values */
|
||||
qi->tqi_type = qinfo->tqi_type;
|
||||
qi->tqi_subtype = qinfo->tqi_subtype;
|
||||
qi->tqi_flags = qinfo->tqi_flags;
|
||||
/*
|
||||
* According to the docs: Although the AIFS field is 8 bit wide,
|
||||
* the maximum supported value is 0xFC. Setting it higher than that
|
||||
* will cause the DCU to hang.
|
||||
*/
|
||||
qi->tqi_aifs = min(qinfo->tqi_aifs, (u8)0xFC);
|
||||
qi->tqi_cw_min = ath5k_cw_validate(qinfo->tqi_cw_min);
|
||||
qi->tqi_cw_max = ath5k_cw_validate(qinfo->tqi_cw_max);
|
||||
qi->tqi_cbr_period = qinfo->tqi_cbr_period;
|
||||
qi->tqi_cbr_overflow_limit = qinfo->tqi_cbr_overflow_limit;
|
||||
qi->tqi_burst_time = qinfo->tqi_burst_time;
|
||||
qi->tqi_ready_time = qinfo->tqi_ready_time;
|
||||
|
||||
/*XXX: Is this supported on 5210 ?*/
|
||||
if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
|
||||
((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
|
||||
(queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
|
||||
queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
|
||||
ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
|
||||
/*XXX: Is this correct for AR5K_WME_AC_VI,VO ???*/
|
||||
if ((qinfo->tqi_type == AR5K_TX_QUEUE_DATA &&
|
||||
((qinfo->tqi_subtype == AR5K_WME_AC_VI) ||
|
||||
(qinfo->tqi_subtype == AR5K_WME_AC_VO))) ||
|
||||
qinfo->tqi_type == AR5K_TX_QUEUE_UAPSD)
|
||||
qi->tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -186,7 +220,7 @@ void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
*/
|
||||
int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
{
|
||||
u32 cw_min, cw_max, retry_lg, retry_sh;
|
||||
u32 retry_lg, retry_sh;
|
||||
struct ath5k_txq_info *tq = &ah->ah_txq[queue];
|
||||
|
||||
AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
|
||||
@@ -217,14 +251,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
/* Set IFS0 */
|
||||
if (ah->ah_turbo) {
|
||||
ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
|
||||
(ah->ah_aifs + tq->tqi_aifs) *
|
||||
AR5K_INIT_SLOT_TIME_TURBO) <<
|
||||
tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) <<
|
||||
AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
|
||||
AR5K_IFS0);
|
||||
} else {
|
||||
ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
|
||||
(ah->ah_aifs + tq->tqi_aifs) *
|
||||
AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
|
||||
tq->tqi_aifs * AR5K_INIT_SLOT_TIME) <<
|
||||
AR5K_IFS0_DIFS_S) |
|
||||
AR5K_INIT_SIFS, AR5K_IFS0);
|
||||
}
|
||||
|
||||
@@ -247,35 +280,6 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
AR5K_PHY_FRAME_CTL_5210);
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate cwmin/max by channel mode
|
||||
*/
|
||||
cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
|
||||
cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
|
||||
ah->ah_aifs = AR5K_TUNE_AIFS;
|
||||
/*XR is only supported on 5212*/
|
||||
if (IS_CHAN_XR(ah->ah_current_channel) &&
|
||||
ah->ah_version == AR5K_AR5212) {
|
||||
cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
|
||||
cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
|
||||
ah->ah_aifs = AR5K_TUNE_AIFS_XR;
|
||||
/*B mode is not supported on 5210*/
|
||||
} else if (IS_CHAN_B(ah->ah_current_channel) &&
|
||||
ah->ah_version != AR5K_AR5210) {
|
||||
cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
|
||||
cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
|
||||
ah->ah_aifs = AR5K_TUNE_AIFS_11B;
|
||||
}
|
||||
|
||||
cw_min = 1;
|
||||
while (cw_min < ah->ah_cw_min)
|
||||
cw_min = (cw_min << 1) | 1;
|
||||
|
||||
cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
|
||||
((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
|
||||
cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
|
||||
((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
|
||||
|
||||
/*
|
||||
* Calculate and set retry limits
|
||||
*/
|
||||
@@ -292,7 +296,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
/*No QCU/DCU [5210]*/
|
||||
if (ah->ah_version == AR5K_AR5210) {
|
||||
ath5k_hw_reg_write(ah,
|
||||
(cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
|
||||
(tq->tqi_cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
|
||||
| AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
|
||||
AR5K_NODCU_RETRY_LMT_SLG_RETRY)
|
||||
| AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
|
||||
@@ -314,14 +318,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
/*===Rest is also for QCU/DCU only [5211+]===*/
|
||||
|
||||
/*
|
||||
* Set initial content window (cw_min/cw_max)
|
||||
* Set contention window (cw_min/cw_max)
|
||||
* and arbitrated interframe space (aifs)...
|
||||
*/
|
||||
ath5k_hw_reg_write(ah,
|
||||
AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
|
||||
AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
|
||||
AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
|
||||
AR5K_DCU_LCL_IFS_AIFS),
|
||||
AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
|
||||
AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
|
||||
AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
|
||||
AR5K_QUEUE_DFS_LOCAL_IFS(queue));
|
||||
|
||||
/*
|
||||
|
||||
@@ -1822,50 +1822,8 @@
|
||||
|
||||
/*===5212 end===*/
|
||||
|
||||
/*
|
||||
* Key table (WEP) register
|
||||
*/
|
||||
#define AR5K_KEYTABLE_0_5210 0x9000
|
||||
#define AR5K_KEYTABLE_0_5211 0x8800
|
||||
#define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5))
|
||||
#define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5))
|
||||
#define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \
|
||||
AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))
|
||||
#define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2))
|
||||
#define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5)
|
||||
#define AR5K_KEYTABLE_TYPE_40 0x00000000
|
||||
#define AR5K_KEYTABLE_TYPE_104 0x00000001
|
||||
#define AR5K_KEYTABLE_TYPE_128 0x00000003
|
||||
#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */
|
||||
#define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */
|
||||
#define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */
|
||||
#define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */
|
||||
#define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */
|
||||
#define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6)
|
||||
#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7)
|
||||
#define AR5K_KEYTABLE_VALID 0x00008000
|
||||
|
||||
/* If key type is TKIP and MIC is enabled
|
||||
* MIC key goes in offset entry + 64 */
|
||||
#define AR5K_KEYTABLE_MIC_OFFSET 64
|
||||
|
||||
/* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit
|
||||
* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit
|
||||
* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit
|
||||
*
|
||||
* Some vendors have introduced bigger WEP keys to address
|
||||
* security vulnerabilities in WEP. This includes:
|
||||
*
|
||||
* WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit
|
||||
*
|
||||
* We can expand this if we find ar5k Atheros cards with a larger
|
||||
* key table size.
|
||||
*/
|
||||
#define AR5K_KEYTABLE_SIZE_5210 64
|
||||
#define AR5K_KEYTABLE_SIZE_5211 128
|
||||
#define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \
|
||||
AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)
|
||||
|
||||
|
||||
/*===PHY REGISTERS===*/
|
||||
|
||||
|
||||
@@ -32,6 +32,14 @@ config ATH9K_DEBUGFS
|
||||
|
||||
Also required for changing debug message flags at run time.
|
||||
|
||||
config ATH9K_RATE_CONTROL
|
||||
bool "Atheros ath9k rate control"
|
||||
depends on ATH9K
|
||||
default y
|
||||
---help---
|
||||
Say Y, if you want to use the ath9k specific rate control
|
||||
module instead of minstrel_ht.
|
||||
|
||||
config ATH9K_HTC
|
||||
tristate "Atheros HTC based wireless cards support"
|
||||
depends on USB && MAC80211
|
||||
|
||||
@@ -5,8 +5,8 @@ ath9k-y += beacon.o \
|
||||
recv.o \
|
||||
xmit.o \
|
||||
virtual.o \
|
||||
rc.o
|
||||
|
||||
ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
|
||||
ath9k-$(CONFIG_PCI) += pci.o
|
||||
ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
|
||||
ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user