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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for new arm SoCs from Olof Johansson: "Three new system-on-chip models are supported: the st-ericsson u9540 in ux500, the sam9n12 in at91 and the emma ev2 in shmobile. Emma is a little bit special because it is completely unrelated to the classic shmobile models, but the new Renesas rmobile SoCs are a combination of things from both Emma and shmobile, so it was decided to have them all live in one directory. This also contains updates to existing shmobile soc code as well as some related board changes due to dependencies." * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits) mach-shmobile: Use DT_MACHINE for KZM9D V3 mach-shmobile: Emma Mobile EV2 DT support V3 mach-shmobile: KZM9D board Ethernet support V3 mach-shmobile: Emma Mobile EV2 GPIO support V3 mach-shmobile: Emma Mobile EV2 SMP support V3 mach-shmobile: KZM9D board support V3 mach-shmobile: Emma Mobile EV2 SoC base support V3 gpio: Emma Mobile GPIO driver V2 ARM: mach-shmobile: sh73a0: fixup PINT/IRQ16-IRQ31 irq number conflict ARM: mach-shmobile: clock-r8a7740: use followparent_recalc on usb24s ARM: mach-shmobile: clock-r8a7740: add MMCIF clock ARM: mach-shmobile: clock-r8a7740: add SDHI clock ARM: mach-shmobile: clock-r8a7740: add USB clock ARM: mach-shmobile: clock-r8a7740: add FSI clock ARM: mach-shmobile: r8a7740: cleanup I2C workaround method ARM: mach-shmobile: r8a7740: add gpio_irq support ARM: mach-shmobile: sh7372: Add FSI DMAEngine support ARM / mach-shmobile: Use preset_lpj with calibrate_delay() ARM: ux500: ioremap differences for DB9540 ARM: ux500: core U9540 support ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Hong Xu <hong.xu@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9N12 SoC";
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||||
compatible = "atmel,at91sam9n12";
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||||
interrupt-parent = <&aic>;
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||||
|
||||
aliases {
|
||||
serial0 = &dbgu;
|
||||
serial1 = &usart0;
|
||||
serial2 = &usart1;
|
||||
serial3 = &usart2;
|
||||
serial4 = &usart3;
|
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gpio0 = &pioA;
|
||||
gpio1 = &pioB;
|
||||
gpio2 = &pioC;
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||||
gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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||||
cpus {
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||||
cpu@0 {
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||||
compatible = "arm,arm926ejs";
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};
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};
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||||
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memory {
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reg = <0x20000000 0x10000000>;
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||||
};
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||||
|
||||
ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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|
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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||||
|
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <2>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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};
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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};
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91rm9200-pmc";
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reg = <0xfffffc00 0x100>;
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};
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rstc@fffffe00 {
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compatible = "atmel,at91sam9g45-rstc";
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reg = <0xfffffe00 0x10>;
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};
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|
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 4>;
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};
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shdwc@fffffe10 {
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compatible = "atmel,at91sam9x5-shdwc";
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reg = <0xfffffe10 0x10>;
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf8008000 0x100>;
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interrupts = <17 4>;
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||||
};
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||||
|
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf800c000 0x100>;
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||||
interrupts = <17 4>;
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||||
};
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||||
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dma: dma-controller@ffffec00 {
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||||
compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 4>;
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};
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||||
|
||||
pioA: gpio@fffff400 {
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||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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||||
reg = <0xfffff400 0x100>;
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||||
interrupts = <2 4>;
|
||||
#gpio-cells = <2>;
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||||
gpio-controller;
|
||||
interrupt-controller;
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||||
};
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||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <2 4>;
|
||||
#gpio-cells = <2>;
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||||
gpio-controller;
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||||
interrupt-controller;
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||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <3 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
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||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
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reg = <0xfffffa00 0x100>;
|
||||
interrupts = <3 4>;
|
||||
#gpio-cells = <2>;
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||||
gpio-controller;
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||||
interrupt-controller;
|
||||
};
|
||||
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||||
dbgu: serial@fffff200 {
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||||
compatible = "atmel,at91sam9260-usart";
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||||
reg = <0xfffff200 0x200>;
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||||
interrupts = <1 4>;
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status = "disabled";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
compatible = "atmel,at91sam9260-usart";
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reg = <0xf801c000 0x4000>;
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||||
interrupts = <5 4>;
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||||
atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@f8020000 {
|
||||
compatible = "atmel,at91sam9260-usart";
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||||
reg = <0xf8020000 0x4000>;
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||||
interrupts = <6 4>;
|
||||
atmel,use-dma-rx;
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||||
atmel,use-dma-tx;
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||||
status = "disabled";
|
||||
};
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||||
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||||
usart2: serial@f8024000 {
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||||
compatible = "atmel,at91sam9260-usart";
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||||
reg = <0xf8024000 0x4000>;
|
||||
interrupts = <7 4>;
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||||
atmel,use-dma-rx;
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||||
atmel,use-dma-tx;
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status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@f8028000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8028000 0x4000>;
|
||||
interrupts = <8 4>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
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||||
status = "disabled";
|
||||
};
|
||||
};
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||||
|
||||
nand0: nand@40000000 {
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||||
compatible = "atmel,at91rm9200-nand";
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||||
#address-cells = <1>;
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||||
#size-cells = <1>;
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||||
reg = < 0x40000000 0x10000000
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||||
0xffffe000 0x00000600
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||||
0xffffe600 0x00000200
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||||
0x00100000 0x00100000
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||||
>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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gpios = <&pioD 5 0
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&pioD 4 0
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||||
0
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||||
>;
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status = "disabled";
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||||
};
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||||
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||||
usb0: ohci@00500000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00500000 0x00100000>;
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||||
interrupts = <22 4>;
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status = "disabled";
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||||
};
|
||||
};
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||||
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i2c@0 {
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compatible = "i2c-gpio";
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||||
gpios = <&pioA 30 0 /* sda */
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&pioA 31 0 /* scl */
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||||
>;
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||||
i2c-gpio,sda-open-drain;
|
||||
i2c-gpio,scl-open-drain;
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||||
i2c-gpio,delay-us = <2>; /* ~100 kHz */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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||||
};
|
||||
};
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@@ -0,0 +1,84 @@
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/*
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||||
* at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
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||||
*
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||||
* Copyright (C) 2012 Atmel,
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||||
* 2012 Hong Xu <hong.xu@atmel.com>
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||||
*
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||||
* Licensed under GPLv2 or later.
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||||
*/
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||||
/dts-v1/;
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/include/ "at91sam9n12.dtsi"
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/ {
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||||
model = "Atmel AT91SAM9N12-EK";
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compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
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||||
chosen {
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bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
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||||
};
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memory {
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reg = <0x20000000 0x10000000>;
|
||||
};
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||||
|
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clocks {
|
||||
#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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||||
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main_clock: clock@0 {
|
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compatible = "atmel,osc", "fixed-clock";
|
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clock-frequency = <16000000>;
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};
|
||||
};
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||||
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ahb {
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apb {
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dbgu: serial@fffff200 {
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status = "okay";
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||||
};
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||||
};
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||||
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nand0: nand@40000000 {
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nand-bus-width = <8>;
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nand-ecc-mode = "soft";
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nand-on-flash-bbt;
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status = "okay";
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};
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||||
};
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||||
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leds {
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compatible = "gpio-leds";
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||||
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d8 {
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label = "d8";
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gpios = <&pioB 4 1>;
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||||
linux,default-trigger = "mmc0";
|
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};
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||||
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||||
d9 {
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label = "d6";
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||||
gpios = <&pioB 5 1>;
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||||
linux,default-trigger = "nand-disk";
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||||
};
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||||
|
||||
d10 {
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||||
label = "d7";
|
||||
gpios = <&pioB 6 0>;
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||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
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||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
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enter {
|
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label = "Enter";
|
||||
gpios = <&pioB 4 1>;
|
||||
linux,code = <28>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Device Tree Source for the KZM9D board
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
/dts-v1/;
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||||
|
||||
/include/ "emev2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EMEV2 KZM9D Board";
|
||||
compatible = "renesas,kzm9d", "renesas,emev2";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x8000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS1,115200n81";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Device Tree Source for the EMEV2 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,emev2";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e0020000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xe0028000 0x1000>,
|
||||
<0xe0020000 0x0100>;
|
||||
};
|
||||
|
||||
sti@e0180000 {
|
||||
compatible = "renesas,em-sti";
|
||||
reg = <0xe0180000 0x54>;
|
||||
interrupts = <0 125 0>;
|
||||
};
|
||||
|
||||
uart@e1020000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1020000 0x38>;
|
||||
interrupts = <0 8 0>;
|
||||
};
|
||||
|
||||
uart@e1030000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1030000 0x38>;
|
||||
interrupts = <0 9 0>;
|
||||
};
|
||||
|
||||
uart@e1040000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1040000 0x38>;
|
||||
interrupts = <0 10 0>;
|
||||
};
|
||||
|
||||
uart@e1050000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1050000 0x38>;
|
||||
interrupts = <0 11 0>;
|
||||
};
|
||||
};
|
||||
@@ -91,6 +91,14 @@ config SOC_AT91SAM9X5
|
||||
This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
|
||||
and AT91SAM9X35.
|
||||
|
||||
config SOC_AT91SAM9N12
|
||||
bool "AT91SAM9N12 family"
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
help
|
||||
Select this if you are using Atmel's AT91SAM9N12 SoC.
|
||||
|
||||
choice
|
||||
prompt "Atmel AT91 Processor Devices for non DT boards"
|
||||
|
||||
|
||||
@@ -18,6 +18,7 @@ obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
|
||||
|
||||
|
||||
@@ -30,5 +30,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
|
||||
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
|
||||
# sam9g45
|
||||
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
|
||||
# sam9n12
|
||||
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
|
||||
# sam9x5
|
||||
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
|
||||
|
||||
@@ -0,0 +1,233 @@
|
||||
/*
|
||||
* SoC specific setup code for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/at91sam9n12.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
#include "sam9_smc.h"
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioAB_clk = {
|
||||
.name = "pioAB_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioCD_clk = {
|
||||
.name = "pioCD_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart3_clk = {
|
||||
.name = "usart3_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_USART3,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi0_clk = {
|
||||
.name = "twi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc_clk = {
|
||||
.name = "mci_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_MCI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart0_clk = {
|
||||
.name = "uart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UART0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uart1_clk = {
|
||||
.name = "uart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UART1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tcb_clk = {
|
||||
.name = "tcb_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_TCB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pwm_clk = {
|
||||
.name = "pwm_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_PWM,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk adc_clk = {
|
||||
.name = "adc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_ADC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk dma_clk = {
|
||||
.name = "dma_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_DMA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk uhp_clk = {
|
||||
.name = "uhp",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UHP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udp_clk = {
|
||||
.name = "udp_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_UDP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc_clk = {
|
||||
.name = "ssc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9N12_ID_SSC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] __initdata = {
|
||||
&pioAB_clk,
|
||||
&pioCD_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&usart3_clk,
|
||||
&twi0_clk,
|
||||
&twi1_clk,
|
||||
&mmc_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&lcdc_clk,
|
||||
&uart0_clk,
|
||||
&uart1_clk,
|
||||
&tcb_clk,
|
||||
&pwm_clk,
|
||||
&adc_clk,
|
||||
&dma_clk,
|
||||
&uhp_clk,
|
||||
&udp_clk,
|
||||
&ssc_clk,
|
||||
};
|
||||
|
||||
static struct clk_lookup periph_clocks_lookups[] = {
|
||||
/* lookup table for DT entries */
|
||||
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
|
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
|
||||
CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
|
||||
};
|
||||
|
||||
/*
|
||||
* The two programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void __init at91sam9n12_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
|
||||
clkdev_add_table(periph_clocks_lookups,
|
||||
ARRAY_SIZE(periph_clocks_lookups));
|
||||
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9N12 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9n12_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
|
||||
}
|
||||
|
||||
void __init at91sam9n12_initialize(void)
|
||||
{
|
||||
at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
|
||||
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
struct at91_init_soc __initdata at91sam9n12_soc = {
|
||||
.map_io = at91sam9n12_map_io,
|
||||
.register_clocks = at91sam9n12_register_clocks,
|
||||
.init = at91sam9n12_initialize,
|
||||
};
|
||||
@@ -58,13 +58,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
||||
|
||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12()))
|
||||
|
||||
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
@@ -78,12 +80,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
||||
|| cpu_is_at91sam9x5()))
|
||||
|
||||
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5())
|
||||
|| cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
|
||||
|| cpu_is_at91sam9n12())
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_SPINLOCK(clk_lock);
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* SoC specific header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation
|
||||
*
|
||||
* Common definitions, based on AT91SAM9N12 SoC datasheet
|
||||
*
|
||||
* Licensed under GPLv2 or later
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_H_
|
||||
#define _AT91SAM9N12_H_
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||
#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
|
||||
#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
|
||||
#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
|
||||
#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
|
||||
#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
|
||||
#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||
#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||
#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
|
||||
#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
|
||||
#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
|
||||
#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
|
||||
#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
|
||||
#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
|
||||
#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
|
||||
#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
|
||||
#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
|
||||
#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
|
||||
#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9N12_BASE_USART0 0xf801c000
|
||||
#define AT91SAM9N12_BASE_USART1 0xf8020000
|
||||
#define AT91SAM9N12_BASE_USART2 0xf8024000
|
||||
#define AT91SAM9N12_BASE_USART3 0xf8028000
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
|
||||
#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Matrix-centric header file for the AT91SAM9N12
|
||||
*
|
||||
* Copyright (C) 2012 Atmel Corporation.
|
||||
*
|
||||
* Only EBI related registers.
|
||||
* Write Protect register definitions may be useful.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _AT91SAM9N12_MATRIX_H_
|
||||
#define _AT91SAM9N12_MATRIX_H_
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||
|
||||
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||
|
||||
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||
|
||||
#endif
|
||||
@@ -25,6 +25,7 @@
|
||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||
#define ARCH_ID_AT91SAM9N12 0x819a07a0
|
||||
|
||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
@@ -71,6 +72,9 @@ enum at91_soc_type {
|
||||
/* SAM9X5 */
|
||||
AT91_SOC_SAM9X5,
|
||||
|
||||
/* SAM9N12 */
|
||||
AT91_SOC_SAM9N12,
|
||||
|
||||
/* Unknown type */
|
||||
AT91_SOC_NONE
|
||||
};
|
||||
@@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void)
|
||||
#define cpu_is_at91sam9x25() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AT91SAM9N12
|
||||
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
|
||||
#else
|
||||
#define cpu_is_at91sam9n12() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
#include <mach/at91sam9rl.h>
|
||||
#include <mach/at91sam9g45.h>
|
||||
#include <mach/at91sam9x5.h>
|
||||
#include <mach/at91sam9n12.h>
|
||||
|
||||
/*
|
||||
* On all at91 except rm9200 and x40 have the System Controller starts
|
||||
|
||||
@@ -143,6 +143,11 @@ static void __init soc_detect(u32 dbgu_base)
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9X5;
|
||||
at91_boot_soc = at91sam9x5_soc;
|
||||
break;
|
||||
|
||||
case ARCH_ID_AT91SAM9N12:
|
||||
at91_soc_initdata.type = AT91_SOC_SAM9N12;
|
||||
at91_boot_soc = at91sam9n12_soc;
|
||||
break;
|
||||
}
|
||||
|
||||
/* at91sam9g10 */
|
||||
@@ -210,6 +215,7 @@ static const char *soc_name[] = {
|
||||
[AT91_SOC_SAM9G45] = "at91sam9g45",
|
||||
[AT91_SOC_SAM9RL] = "at91sam9rl",
|
||||
[AT91_SOC_SAM9X5] = "at91sam9x5",
|
||||
[AT91_SOC_SAM9N12] = "at91sam9n12",
|
||||
[AT91_SOC_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
||||
@@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;
|
||||
extern struct at91_init_soc at91sam9g45_soc;
|
||||
extern struct at91_init_soc at91sam9rl_soc;
|
||||
extern struct at91_init_soc at91sam9x5_soc;
|
||||
extern struct at91_init_soc at91sam9n12_soc;
|
||||
|
||||
static inline int at91_soc_is_enabled(void)
|
||||
{
|
||||
@@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)
|
||||
#if !defined(CONFIG_SOC_AT91SAM9X5)
|
||||
#define at91sam9x5_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SOC_AT91SAM9N12)
|
||||
#define at91sam9n12_soc at91_boot_soc
|
||||
#endif
|
||||
|
||||
@@ -41,6 +41,12 @@ config ARCH_R8A7779
|
||||
select ARM_GIC
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
config ARCH_EMEV2
|
||||
bool "Emma Mobile EV2"
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
comment "SH-Mobile Board Type"
|
||||
|
||||
config MACH_G3EVM
|
||||
@@ -98,6 +104,11 @@ config MACH_MARZEN
|
||||
depends on ARCH_R8A7779
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
config MACH_KZM9D
|
||||
bool "KZM9D board"
|
||||
depends on ARCH_EMEV2
|
||||
select USE_OF
|
||||
|
||||
comment "SH-Mobile System Configuration"
|
||||
|
||||
config CPU_HAS_INTEVT
|
||||
|
||||
@@ -12,12 +12,14 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
|
||||
obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
|
||||
|
||||
# SMP objects
|
||||
smp-y := platsmp.o headsmp.o
|
||||
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
|
||||
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
|
||||
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
|
||||
|
||||
# Pinmux setup
|
||||
pfc-y :=
|
||||
@@ -49,6 +51,7 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
|
||||
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
|
||||
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
|
||||
obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
|
||||
|
||||
# Framework support
|
||||
obj-$(CONFIG_SMP) += $(smp-y)
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* kzm9d board support
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
* Copyright (C) 2012 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/emev2.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
/* Ether */
|
||||
static struct resource smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x20000000,
|
||||
.end = 0x2000ffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = EMEV2_GPIO_IRQ(1),
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_platdata = {
|
||||
.flags = SMSC911X_USE_32BIT,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
};
|
||||
|
||||
static struct platform_device smsc91x_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_platdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
.resource = smsc911x_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *kzm9d_devices[] __initdata = {
|
||||
&smsc91x_device,
|
||||
};
|
||||
|
||||
void __init kzm9d_add_standard_devices(void)
|
||||
{
|
||||
emev2_add_standard_devices();
|
||||
|
||||
platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
|
||||
}
|
||||
|
||||
static const char *kzm9d_boards_compat_dt[] __initdata = {
|
||||
"renesas,kzm9d",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(KZM9D_DT, "kzm9d")
|
||||
.map_io = emev2_map_io,
|
||||
.init_early = emev2_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = emev2_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = kzm9d_add_standard_devices,
|
||||
.timer = &shmobile_timer,
|
||||
.dt_compat = kzm9d_boards_compat_dt,
|
||||
MACHINE_END
|
||||
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Emma Mobile EV2 clock framework support
|
||||
*
|
||||
* Copyright (C) 2012 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define EMEV2_SMU_BASE 0xe0110000
|
||||
|
||||
/* EMEV2 SMU registers */
|
||||
#define USIAU0_RSTCTRL 0x094
|
||||
#define USIBU1_RSTCTRL 0x0ac
|
||||
#define USIBU2_RSTCTRL 0x0b0
|
||||
#define USIBU3_RSTCTRL 0x0b4
|
||||
#define STI_RSTCTRL 0x124
|
||||
#define USIAU0GCLKCTRL 0x4a0
|
||||
#define USIBU1GCLKCTRL 0x4b8
|
||||
#define USIBU2GCLKCTRL 0x4bc
|
||||
#define USIBU3GCLKCTRL 0x04c0
|
||||
#define STIGCLKCTRL 0x528
|
||||
#define USIAU0SCLKDIV 0x61c
|
||||
#define USIB2SCLKDIV 0x65c
|
||||
#define USIB3SCLKDIV 0x660
|
||||
#define STI_CLKSEL 0x688
|
||||
#define SMU_GENERAL_REG0 0x7c0
|
||||
|
||||
/* not pretty, but hey */
|
||||
static void __iomem *smu_base;
|
||||
|
||||
static void emev2_smu_write(unsigned long value, int offs)
|
||||
{
|
||||
BUG_ON(!smu_base || (offs >= PAGE_SIZE));
|
||||
iowrite32(value, smu_base + offs);
|
||||
}
|
||||
|
||||
void emev2_set_boot_vector(unsigned long value)
|
||||
{
|
||||
emev2_smu_write(value, SMU_GENERAL_REG0);
|
||||
}
|
||||
|
||||
static struct clk_mapping smu_mapping = {
|
||||
.phys = EMEV2_SMU_BASE,
|
||||
.len = PAGE_SIZE,
|
||||
};
|
||||
|
||||
/* Fixed 32 KHz root clock from C32K pin */
|
||||
static struct clk c32k_clk = {
|
||||
.rate = 32768,
|
||||
.mapping = &smu_mapping,
|
||||
};
|
||||
|
||||
/* PLL3 multiplies C32K with 7000 */
|
||||
static unsigned long pll3_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * 7000;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll3_clk_ops = {
|
||||
.recalc = pll3_recalc,
|
||||
};
|
||||
|
||||
static struct clk pll3_clk = {
|
||||
.ops = &pll3_clk_ops,
|
||||
.parent = &c32k_clk,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&c32k_clk,
|
||||
&pll3_clk,
|
||||
};
|
||||
|
||||
enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3,
|
||||
SCLKDIV_NR };
|
||||
|
||||
#define SCLKDIV(_reg, _shift) \
|
||||
{ \
|
||||
.parent = &pll3_clk, \
|
||||
.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
|
||||
.enable_bit = _shift, \
|
||||
}
|
||||
|
||||
static struct clk sclkdiv_clks[SCLKDIV_NR] = {
|
||||
[SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0),
|
||||
[SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16),
|
||||
[SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0),
|
||||
[SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0),
|
||||
};
|
||||
|
||||
enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
|
||||
GCLK_STI_SCLK,
|
||||
GCLK_NR };
|
||||
|
||||
#define GCLK_SCLK(_parent, _reg) \
|
||||
{ \
|
||||
.parent = _parent, \
|
||||
.enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \
|
||||
.enable_bit = 1, /* SCLK_GCC */ \
|
||||
}
|
||||
|
||||
static struct clk gclk_clks[GCLK_NR] = {
|
||||
[GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0],
|
||||
USIAU0GCLKCTRL),
|
||||
[GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1],
|
||||
USIBU1GCLKCTRL),
|
||||
[GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2],
|
||||
USIBU2GCLKCTRL),
|
||||
[GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
|
||||
USIBU3GCLKCTRL),
|
||||
[GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
|
||||
};
|
||||
|
||||
static int emev2_gclk_enable(struct clk *clk)
|
||||
{
|
||||
iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
|
||||
clk->mapped_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void emev2_gclk_disable(struct clk *clk)
|
||||
{
|
||||
iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
|
||||
clk->mapped_reg);
|
||||
}
|
||||
|
||||
static struct sh_clk_ops emev2_gclk_clk_ops = {
|
||||
.enable = emev2_gclk_enable,
|
||||
.disable = emev2_gclk_disable,
|
||||
.recalc = followparent_recalc,
|
||||
};
|
||||
|
||||
static int __init emev2_gclk_register(struct clk *clks, int nr)
|
||||
{
|
||||
struct clk *clkp;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
for (k = 0; !ret && (k < nr); k++) {
|
||||
clkp = clks + k;
|
||||
clkp->ops = &emev2_gclk_clk_ops;
|
||||
ret |= clk_register(clkp);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long emev2_sclkdiv_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned int sclk_div;
|
||||
|
||||
sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff;
|
||||
|
||||
return clk->parent->rate / (sclk_div + 1);
|
||||
}
|
||||
|
||||
static struct sh_clk_ops emev2_sclkdiv_clk_ops = {
|
||||
.recalc = emev2_sclkdiv_recalc,
|
||||
};
|
||||
|
||||
static int __init emev2_sclkdiv_register(struct clk *clks, int nr)
|
||||
{
|
||||
struct clk *clkp;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
for (k = 0; !ret && (k < nr); k++) {
|
||||
clkp = clks + k;
|
||||
clkp->ops = &emev2_sclkdiv_clk_ops;
|
||||
ret |= clk_register(clkp);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]),
|
||||
CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]),
|
||||
CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]),
|
||||
CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]),
|
||||
CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]),
|
||||
CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]),
|
||||
CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]),
|
||||
CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
|
||||
CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
|
||||
CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
|
||||
};
|
||||
|
||||
void __init emev2_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
static int is_setup;
|
||||
|
||||
/* yuck, this is ugly as hell, but the non-smp case of clocks
|
||||
* code is now designed to rely on ioremap() instead of static
|
||||
* entity maps. in the case of smp we need access to the SMU
|
||||
* register earlier than ioremap() is actually working without
|
||||
* any static maps. to enable SMP in ugly but with dynamic
|
||||
* mappings we have to call emev2_clock_init() from different
|
||||
* places depending on UP and SMP...
|
||||
*/
|
||||
if (is_setup++)
|
||||
return;
|
||||
|
||||
smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
|
||||
BUG_ON(!smu_base);
|
||||
|
||||
/* setup STI timer to run on 37.768 kHz and deassert reset */
|
||||
emev2_smu_write(0, STI_CLKSEL);
|
||||
emev2_smu_write(1, STI_RSTCTRL);
|
||||
|
||||
/* deassert reset for UART0->UART3 */
|
||||
emev2_smu_write(2, USIAU0_RSTCTRL);
|
||||
emev2_smu_write(2, USIBU1_RSTCTRL);
|
||||
emev2_smu_write(2, USIBU2_RSTCTRL);
|
||||
emev2_smu_write(2, USIBU3_RSTCTRL);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = emev2_gclk_register(gclk_clks, GCLK_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup emev2 clocks\n");
|
||||
}
|
||||
@@ -47,6 +47,7 @@
|
||||
#define PLLC01CR 0xe6150028
|
||||
|
||||
#define SUBCKCR 0xe6150080
|
||||
#define USBCKCR 0xe615008c
|
||||
|
||||
#define MSTPSR0 0xe6150030
|
||||
#define MSTPSR1 0xe6150038
|
||||
@@ -181,6 +182,95 @@ static struct clk pllc1_div2_clk = {
|
||||
.parent = &pllc1_clk,
|
||||
};
|
||||
|
||||
/* USB clock */
|
||||
static struct clk *usb24s_parents[] = {
|
||||
[0] = &system_clk,
|
||||
[1] = &extal2_clk
|
||||
};
|
||||
|
||||
static int usb24s_enable(struct clk *clk)
|
||||
{
|
||||
__raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void usb24s_disable(struct clk *clk)
|
||||
{
|
||||
__raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
|
||||
}
|
||||
|
||||
static int usb24s_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
int i, ret;
|
||||
u32 val;
|
||||
|
||||
if (!clk->parent_table || !clk->parent_num)
|
||||
return -EINVAL;
|
||||
|
||||
/* Search the parent */
|
||||
for (i = 0; i < clk->parent_num; i++)
|
||||
if (clk->parent_table[i] == parent)
|
||||
break;
|
||||
|
||||
if (i == clk->parent_num)
|
||||
return -ENODEV;
|
||||
|
||||
ret = clk_reparent(clk, parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val = __raw_readl(USBCKCR);
|
||||
val &= ~(1 << 7);
|
||||
val |= i << 7;
|
||||
__raw_writel(val, USBCKCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops usb24s_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
.enable = usb24s_enable,
|
||||
.disable = usb24s_disable,
|
||||
.set_parent = usb24s_set_parent,
|
||||
};
|
||||
|
||||
static struct clk usb24s_clk = {
|
||||
.ops = &usb24s_clk_ops,
|
||||
.parent_table = usb24s_parents,
|
||||
.parent_num = ARRAY_SIZE(usb24s_parents),
|
||||
.parent = &system_clk,
|
||||
};
|
||||
|
||||
static unsigned long usb24_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate /
|
||||
((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
|
||||
};
|
||||
|
||||
static int usb24_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* closer to which ? parent->rate or parent->rate/2 */
|
||||
val = __raw_readl(USBCKCR);
|
||||
val &= ~(1 << 6);
|
||||
val |= (rate > (clk->parent->rate / 4) * 3) << 6;
|
||||
__raw_writel(val, USBCKCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops usb24_clk_ops = {
|
||||
.recalc = usb24_recalc,
|
||||
.set_rate = usb24_set_rate,
|
||||
};
|
||||
|
||||
static struct clk usb24_clk = {
|
||||
.ops = &usb24_clk_ops,
|
||||
.parent = &usb24s_clk,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&extalr_clk,
|
||||
&extal1_clk,
|
||||
@@ -196,6 +286,8 @@ struct clk *main_clks[] = {
|
||||
&pllc0_clk,
|
||||
&pllc1_clk,
|
||||
&pllc1_div2_clk,
|
||||
&usb24s_clk,
|
||||
&usb24_clk,
|
||||
};
|
||||
|
||||
static void div4_kick(struct clk *clk)
|
||||
@@ -223,7 +315,7 @@ static struct clk_div4_table div4_table = {
|
||||
|
||||
enum {
|
||||
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
|
||||
DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_NR
|
||||
};
|
||||
|
||||
@@ -234,6 +326,7 @@ struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
|
||||
[DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
|
||||
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
|
||||
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
|
||||
@@ -257,7 +350,10 @@ enum {
|
||||
MSTP222,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
|
||||
MSTP329, MSTP323,
|
||||
MSTP329, MSTP328, MSTP323, MSTP320,
|
||||
MSTP314, MSTP313, MSTP312,
|
||||
|
||||
MSTP416, MSTP415, MSTP407, MSTP406,
|
||||
|
||||
MSTP_NR
|
||||
};
|
||||
@@ -280,7 +376,17 @@ static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
|
||||
[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
|
||||
[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */
|
||||
[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
|
||||
[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
|
||||
[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
|
||||
|
||||
[MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
|
||||
[MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
|
||||
[MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */
|
||||
[MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
@@ -299,6 +405,7 @@ static struct clk_lookup lookups[] = {
|
||||
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
|
||||
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
|
||||
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
|
||||
CLKDEV_CON_ID("usb24s", &usb24s_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
||||
@@ -334,7 +441,21 @@ static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
|
||||
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
|
||||
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
|
||||
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
|
||||
|
||||
/* ICK */
|
||||
CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
|
||||
CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
|
||||
CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
|
||||
CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
|
||||
CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
|
||||
};
|
||||
|
||||
void __init r8a7740_clock_init(u8 md_ck)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user