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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: SH-4A UBC support sh: interrupt exception handling rework sh: Default enable R7780RP IRQs. sh: Zero-out coherent buffer in consistent_alloc(). sh: Convert IPR-IRQ to IRQ chip. sh: Convert INTC2 IRQ handler to irq_chip. sh: Fix pr_debug statements for sh4 sh: Convert r7780rp IRQ handler to IRQ chip. sh: Updates for IRQ handler changes. sh: Kill off timer_ops get_frequency(). sh: First step at generic timeofday support.
This commit is contained in:
Linus Torvalds
@@ -45,6 +45,9 @@ config GENERIC_CALIBRATE_DELAY
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config GENERIC_IOMAP
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bool
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config GENERIC_TIME
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def_bool n
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config ARCH_MAY_HAVE_PC_FDC
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bool
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@@ -357,6 +360,7 @@ config CPU_HAS_SR_RB
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endmenu
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menu "Timer support"
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depends on !GENERIC_TIME
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config SH_TMU
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bool "TMU timer support"
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@@ -83,7 +83,7 @@ static int hp6x0_apm_get_info(char *buf, char **start, off_t fpos, int length)
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return p - buf;
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}
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static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev, struct pt_regs *regs)
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static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev)
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{
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if (!apm_suspended)
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apm_queue_event(APM_USER_SUSPEND);
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@@ -96,7 +96,7 @@ static int __init hp6x0_apm_init(void)
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int ret;
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ret = request_irq(HP680_BTN_IRQ, hp6x0_apm_interrupt,
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SA_INTERRUPT, MODNAME, 0);
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IRQF_DISABLED, MODNAME, 0);
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if (unlikely(ret < 0)) {
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printk(KERN_ERR MODNAME ": IRQ %d request failed\n",
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HP680_BTN_IRQ);
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@@ -135,7 +135,7 @@ static int swdrv_write(struct file *filp, const char *buff, size_t count,
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return count;
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}
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static irqreturn_t sw_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t sw_interrupt(int irq, void *dev_id)
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{
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landisk_btn = (0x0ff & (~ctrl_inb(PA_STATUS)));
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disable_irq(IRQ_BUTTON);
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@@ -69,7 +69,6 @@ static void __init pci_write_config(unsigned long busNo,
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static unsigned char m_irq_mask = 0xfb;
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static unsigned char s_irq_mask = 0xff;
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volatile unsigned long irq_err_count;
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static void disable_mpc1211_irq(unsigned int irq)
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{
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@@ -118,7 +117,7 @@ static void mask_and_ack_mpc1211(unsigned int irq)
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if(irq < 8) {
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if(m_irq_mask & (1<<irq)){
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if(!mpc1211_irq_real(irq)){
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irq_err_count++;
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atomic_inc(&irq_err_count)
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printk("spurious 8259A interrupt: IRQ %x\n",irq);
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}
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} else {
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@@ -131,7 +130,7 @@ static void mask_and_ack_mpc1211(unsigned int irq)
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} else {
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if(s_irq_mask & (1<<(irq - 8))){
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if(!mpc1211_irq_real(irq)){
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irq_err_count++;
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atomic_inc(&irq_err_count);
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printk("spurious 8259A interrupt: IRQ %x\n",irq);
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}
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} else {
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@@ -1,18 +1,16 @@
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/*
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* linux/arch/sh/boards/renesas/r7780rp/irq.c
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Renesas Solutions Highlander R7780RP-1 Support.
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*
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* Modified for R7780RP-1 by
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* Atom Create Engineering Co., Ltd. 2002.
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* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/r7780rp/r7780rp.h>
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#ifdef CONFIG_SH_R7780MP
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static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
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@@ -20,71 +18,26 @@ static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
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static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
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#endif
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static void enable_r7780rp_irq(unsigned int irq);
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static void disable_r7780rp_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_r7780rp_irq disable_r7780rp_irq
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static void ack_r7780rp_irq(unsigned int irq);
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static void end_r7780rp_irq(unsigned int irq);
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static unsigned int startup_r7780rp_irq(unsigned int irq)
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static void enable_r7780rp_irq(unsigned int irq)
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{
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enable_r7780rp_irq(irq);
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return 0; /* never anything pending */
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/* Set priority in IPR back to original value */
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ctrl_outw(ctrl_inw(IRLCNTR1) | (1 << mask_pos[irq]), IRLCNTR1);
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}
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static void disable_r7780rp_irq(unsigned int irq)
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{
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unsigned short val;
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unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
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/* Set the priority in IPR to 0 */
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val = ctrl_inw(IRLCNTR1);
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val &= mask;
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ctrl_outw(val, IRLCNTR1);
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ctrl_outw(ctrl_inw(IRLCNTR1) & (0xffff ^ (1 << mask_pos[irq])),
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IRLCNTR1);
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}
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static void enable_r7780rp_irq(unsigned int irq)
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{
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unsigned short val;
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unsigned short value = (0x0001 << mask_pos[irq]);
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/* Set priority in IPR back to original value */
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val = ctrl_inw(IRLCNTR1);
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val |= value;
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ctrl_outw(val, IRLCNTR1);
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}
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static void ack_r7780rp_irq(unsigned int irq)
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{
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disable_r7780rp_irq(irq);
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}
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static void end_r7780rp_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_r7780rp_irq(irq);
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}
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static struct hw_interrupt_type r7780rp_irq_type = {
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.typename = "R7780RP-IRQ",
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.startup = startup_r7780rp_irq,
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.shutdown = shutdown_r7780rp_irq,
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.enable = enable_r7780rp_irq,
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.disable = disable_r7780rp_irq,
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.ack = ack_r7780rp_irq,
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.end = end_r7780rp_irq,
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static struct irq_chip r7780rp_irq_chip __read_mostly = {
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.name = "r7780rp",
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.mask = disable_r7780rp_irq,
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.unmask = enable_r7780rp_irq,
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.mask_ack = disable_r7780rp_irq,
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};
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static void make_r7780rp_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].chip = &r7780rp_irq_type;
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disable_r7780rp_irq(irq);
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}
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/*
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* Initialize IRQ setting
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*/
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@@ -92,24 +45,10 @@ void __init init_r7780rp_IRQ(void)
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{
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int i;
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/* IRL0=PCI Slot #A
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* IRL1=PCI Slot #B
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* IRL2=PCI Slot #C
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* IRL3=PCI Slot #D
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* IRL4=CF Card
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* IRL5=CF Card Insert
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* IRL6=M66596
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* IRL7=SD Card
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* IRL8=Touch Panel
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* IRL9=SCI
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* IRL10=Serial
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* IRL11=Extention #A
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* IRL11=Extention #B
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* IRL12=Debug LAN
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* IRL13=Push Switch
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* IRL14=ZiggBee IO
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*/
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for (i=0; i<15; i++)
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make_r7780rp_irq(i);
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for (i = 0; i < 15; i++) {
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disable_irq_nosync(i);
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set_irq_chip_and_handler(i, &r7780rp_irq_chip,
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handle_level_irq);
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enable_r7780rp_irq(i);
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}
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}
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@@ -33,7 +33,7 @@ extern void pcibios_init(void);
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* EraseConfig handling functions
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*/
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static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
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{
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volatile char dummy __attribute__((unused)) = * (volatile char *) 0xb8000000;
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@@ -71,7 +71,7 @@ static struct hw_interrupt_type hd64461_irq_type = {
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.end = end_hd64461_irq,
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};
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static irqreturn_t hd64461_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t hd64461_interrupt(int irq, void *dev_id)
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{
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printk(KERN_INFO
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"HD64461: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
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@@ -85,7 +85,7 @@ static struct {
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void *dev;
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} handlers[GPIO_NPORTS * 8];
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static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev, struct pt_regs *regs)
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static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev)
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{
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unsigned short port, pin, isr, mask, portpin;
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@@ -84,7 +84,7 @@ static struct hw_interrupt_type hd64465_irq_type = {
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};
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static irqreturn_t hd64465_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
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{
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printk(KERN_INFO
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"HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
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@@ -88,8 +88,7 @@ static struct hw_interrupt_type voyagergx_irq_type = {
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.end = end_voyagergx_irq,
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};
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static irqreturn_t voyagergx_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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static irqreturn_t voyagergx_interrupt(int irq, void *dev_id)
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{
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printk(KERN_INFO
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"VoyagerGX: spurious interrupt, status: 0x%x\n",
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@@ -51,7 +51,7 @@ static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa0
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((g2_dma->channel[i].size - \
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g2_dma->status[i].size) & 0x0fffffff)
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static irqreturn_t g2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t g2_dma_interrupt(int irq, void *dev_id)
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{
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int i;
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@@ -21,7 +21,7 @@
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static unsigned int xfer_complete;
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static int count;
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static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
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{
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if (get_dma_residue(PVR2_CASCADE_CHAN)) {
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printk(KERN_WARNING "DMA: SH DMAC did not complete transfer "
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@@ -60,9 +60,9 @@ static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
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* Besides that it needs to waken any waiting process, which should handle
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* setting up the next transfer.
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*/
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static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t dma_tei(int irq, void *dev_id)
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{
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struct dma_channel *chan = (struct dma_channel *)dev_id;
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struct dma_channel *chan = dev_id;
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u32 chcr;
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chcr = ctrl_inl(CHCR[chan->chan]);
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@@ -228,7 +228,7 @@ static inline int dmaor_reset(void)
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}
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#if defined(CONFIG_CPU_SH4)
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static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
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static irqreturn_t dma_err(int irq, void *dummy)
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{
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dmaor_reset();
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disable_irq(irq);
|
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|
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@@ -155,7 +155,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
|
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*/
|
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pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
|
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PCIBIOS_MIN_IO, (64 << 10),
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SH4_PCI_IO_BASE + PCIBIOS_MIN_IO);
|
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SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
|
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|
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/*
|
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* XXX: For now, leave this board-specific. In the event we have other
|
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@@ -163,7 +163,7 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
|
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*/
|
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#ifdef CONFIG_SH_BIGSUR
|
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bigsur_port_map(PCIBIOS_MIN_IO, (64 << 10),
|
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SH4_PCI_IO_BASE + PCIBIOS_MIN_IO, 0);
|
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SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO, 0);
|
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#endif
|
||||
|
||||
/* Make sure the MSB's of IO window are set to access PCI space
|
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|
||||
@@ -161,7 +161,7 @@ static char * pci_commands[16]={
|
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"Memory Write-and-Invalidate"
|
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};
|
||||
|
||||
static irqreturn_t st40_pci_irq(int irq, void *dev_instance, struct pt_regs *regs)
|
||||
static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
|
||||
{
|
||||
unsigned pci_int, pci_air, pci_cir, pci_aint;
|
||||
static int count=0;
|
||||
|
||||
+24
-114
@@ -10,93 +10,32 @@
|
||||
* These are the "new Hitachi style" interrupts, as present on the
|
||||
* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
struct intc2_data {
|
||||
unsigned char msk_offset;
|
||||
unsigned char msk_shift;
|
||||
|
||||
int (*clear_irq) (int);
|
||||
};
|
||||
|
||||
static struct intc2_data intc2_data[NR_INTC2_IRQS];
|
||||
|
||||
static void enable_intc2_irq(unsigned int irq);
|
||||
static void disable_intc2_irq(unsigned int irq);
|
||||
|
||||
/* shutdown is same as "disable" */
|
||||
#define shutdown_intc2_irq disable_intc2_irq
|
||||
|
||||
static void mask_and_ack_intc2(unsigned int);
|
||||
static void end_intc2_irq(unsigned int irq);
|
||||
|
||||
static unsigned int startup_intc2_irq(unsigned int irq)
|
||||
{
|
||||
enable_intc2_irq(irq);
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type intc2_irq_type = {
|
||||
.typename = "INTC2-IRQ",
|
||||
.startup = startup_intc2_irq,
|
||||
.shutdown = shutdown_intc2_irq,
|
||||
.enable = enable_intc2_irq,
|
||||
.disable = disable_intc2_irq,
|
||||
.ack = mask_and_ack_intc2,
|
||||
.end = end_intc2_irq
|
||||
};
|
||||
|
||||
static void disable_intc2_irq(unsigned int irq)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
int msk_shift, msk_offset;
|
||||
|
||||
/* Sanity check */
|
||||
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
msk_shift = intc2_data[irq_offset].msk_shift;
|
||||
msk_offset = intc2_data[irq_offset].msk_offset;
|
||||
|
||||
ctrl_outl(1 << msk_shift,
|
||||
INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset);
|
||||
struct intc2_data *p = get_irq_chip_data(irq);
|
||||
ctrl_outl(1 << p->msk_shift,
|
||||
INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
|
||||
}
|
||||
|
||||
static void enable_intc2_irq(unsigned int irq)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
int msk_shift, msk_offset;
|
||||
|
||||
/* Sanity check */
|
||||
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
msk_shift = intc2_data[irq_offset].msk_shift;
|
||||
msk_offset = intc2_data[irq_offset].msk_offset;
|
||||
|
||||
ctrl_outl(1 << msk_shift,
|
||||
INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset);
|
||||
struct intc2_data *p = get_irq_chip_data(irq);
|
||||
ctrl_outl(1 << p->msk_shift,
|
||||
INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
|
||||
}
|
||||
|
||||
static void mask_and_ack_intc2(unsigned int irq)
|
||||
{
|
||||
disable_intc2_irq(irq);
|
||||
}
|
||||
|
||||
static void end_intc2_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_intc2_irq(irq);
|
||||
|
||||
if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq))
|
||||
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);
|
||||
}
|
||||
static struct irq_chip intc2_irq_chip = {
|
||||
.typename = "intc2",
|
||||
.mask = disable_intc2_irq,
|
||||
.unmask = enable_intc2_irq,
|
||||
.mask_ack = disable_intc2_irq,
|
||||
};
|
||||
|
||||
/*
|
||||
* Setup an INTC2 style interrupt.
|
||||
@@ -108,46 +47,30 @@ static void end_intc2_irq(unsigned int irq)
|
||||
* | | | |
|
||||
* make_intc2_irq(84, 0, 16, 0, 13);
|
||||
*/
|
||||
void make_intc2_irq(unsigned int irq,
|
||||
unsigned int ipr_offset, unsigned int ipr_shift,
|
||||
unsigned int msk_offset, unsigned int msk_shift,
|
||||
unsigned int priority)
|
||||
void make_intc2_irq(struct intc2_data *p)
|
||||
{
|
||||
int irq_offset = irq - INTC2_FIRST_IRQ;
|
||||
unsigned int flags;
|
||||
unsigned long ipr;
|
||||
|
||||
if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
|
||||
return;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
/* Fill the data we need */
|
||||
intc2_data[irq_offset].msk_offset = msk_offset;
|
||||
intc2_data[irq_offset].msk_shift = msk_shift;
|
||||
intc2_data[irq_offset].clear_irq = NULL;
|
||||
disable_irq_nosync(p->irq);
|
||||
|
||||
/* Set the priority level */
|
||||
local_irq_save(flags);
|
||||
|
||||
ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
|
||||
ipr &= ~(0xf << ipr_shift);
|
||||
ipr |= priority << ipr_shift;
|
||||
ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset);
|
||||
ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
|
||||
ipr &= ~(0xf << p->ipr_shift);
|
||||
ipr |= p->priority << p->ipr_shift;
|
||||
ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
irq_desc[irq].chip = &intc2_irq_type;
|
||||
set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq);
|
||||
set_irq_chip_data(p->irq, p);
|
||||
|
||||
disable_intc2_irq(irq);
|
||||
enable_intc2_irq(p->irq);
|
||||
}
|
||||
|
||||
static struct intc2_init {
|
||||
unsigned short irq;
|
||||
unsigned char ipr_offset, ipr_shift;
|
||||
unsigned char msk_offset, msk_shift;
|
||||
unsigned char priority;
|
||||
} intc2_init_data[] __initdata = {
|
||||
static struct intc2_data intc2_irq_table[] = {
|
||||
#if defined(CONFIG_CPU_SUBTYPE_ST40)
|
||||
{64, 0, 0, 0, 0, 13}, /* PCI serr */
|
||||
{65, 0, 4, 0, 1, 13}, /* PCI err */
|
||||
@@ -266,19 +189,6 @@ void __init init_IRQ_intc2(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) {
|
||||
struct intc2_init *p = intc2_init_data + i;
|
||||
make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
|
||||
p-> msk_offset, p->msk_shift, p->priority);
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
|
||||
make_intc2_irq(intc2_irq_table + i);
|
||||
}
|
||||
|
||||
/* Adds a termination callback to the interrupt */
|
||||
void intc2_add_clear_irq(int irq, int (*fn)(int))
|
||||
{
|
||||
if (unlikely(irq < INTC2_FIRST_IRQ))
|
||||
return;
|
||||
|
||||
intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,11 +1,10 @@
|
||||
/*
|
||||
* arch/sh/kernel/cpu/irq/ipr.c
|
||||
* Interrupt handling for IPR-based IRQ.
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
|
||||
* Copyright (C) 2000 Kazumoto Kojima
|
||||
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
|
||||
*
|
||||
* Interrupt handling for IPR-based IRQ.
|
||||
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
|
||||
* Copyright (C) 2006 Paul Mundt
|
||||
*
|
||||
* Supported system:
|
||||
* On-chip supporting modules (TMU, RTC, etc.).
|
||||
@@ -13,12 +12,13 @@
|
||||
* Hitachi SolutionEngine external I/O:
|
||||
* MS7709SE01, MS7709ASE01, and MS7750SE01
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
@@ -28,93 +28,45 @@ struct ipr_data {
|
||||
int shift; /* Shifts of the 16-bit data */
|
||||
int priority; /* The priority */
|
||||
};
|
||||
static struct ipr_data ipr_data[NR_IRQS];
|
||||
|
||||
static void enable_ipr_irq(unsigned int irq);
|
||||
static void disable_ipr_irq(unsigned int irq);
|
||||
|
||||
/* shutdown is same as "disable" */
|
||||
#define shutdown_ipr_irq disable_ipr_irq
|
||||
|
||||
static void mask_and_ack_ipr(unsigned int);
|
||||
static void end_ipr_irq(unsigned int irq);
|
||||
|
||||
static unsigned int startup_ipr_irq(unsigned int irq)
|
||||
{
|
||||
enable_ipr_irq(irq);
|
||||
return 0; /* never anything pending */
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type ipr_irq_type = {
|
||||
.typename = "IPR-IRQ",
|
||||
.startup = startup_ipr_irq,
|
||||
.shutdown = shutdown_ipr_irq,
|
||||
.enable = enable_ipr_irq,
|
||||
.disable = disable_ipr_irq,
|
||||
.ack = mask_and_ack_ipr,
|
||||
.end = end_ipr_irq
|
||||
};
|
||||
|
||||
static void disable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned int addr = ipr_data[irq].addr;
|
||||
unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
|
||||
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
/* Set the priority in IPR to 0 */
|
||||
val = ctrl_inw(addr);
|
||||
val &= mask;
|
||||
ctrl_outw(val, addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
|
||||
}
|
||||
|
||||
static void enable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned int addr = ipr_data[irq].addr;
|
||||
int priority = ipr_data[irq].priority;
|
||||
unsigned short value = (priority << ipr_data[irq].shift);
|
||||
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
/* Set priority in IPR back to original value */
|
||||
val = ctrl_inw(addr);
|
||||
val |= value;
|
||||
ctrl_outw(val, addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
|
||||
}
|
||||
|
||||
static void mask_and_ack_ipr(unsigned int irq)
|
||||
{
|
||||
disable_ipr_irq(irq);
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
/* This is needed when we use edge triggered setting */
|
||||
/* XXX: Is it really needed? */
|
||||
if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
|
||||
/* Clear external interrupt request */
|
||||
int a = ctrl_inb(INTC_IRR0);
|
||||
a &= ~(1 << (irq - IRQ0_IRQ));
|
||||
ctrl_outb(a, INTC_IRR0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void end_ipr_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_ipr_irq(irq);
|
||||
}
|
||||
static struct irq_chip ipr_irq_chip = {
|
||||
.name = "ipr",
|
||||
.mask = disable_ipr_irq,
|
||||
.unmask = enable_ipr_irq,
|
||||
.mask_ack = disable_ipr_irq,
|
||||
};
|
||||
|
||||
void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
ipr_data[irq].addr = addr;
|
||||
ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
|
||||
ipr_data[irq].priority = priority;
|
||||
struct ipr_data ipr_data;
|
||||
|
||||
irq_desc[irq].chip = &ipr_irq_type;
|
||||
disable_ipr_irq(irq);
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
ipr_data.addr = addr;
|
||||
ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
|
||||
ipr_data.priority = priority;
|
||||
|
||||
set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq);
|
||||
set_irq_chip_data(irq, &ipr_data);
|
||||
|
||||
enable_ipr_irq(irq);
|
||||
}
|
||||
|
||||
/* XXX: This needs to die a horrible death.. */
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
||||
|
||||
@@ -49,198 +49,3 @@ ENTRY(nmi_slot)
|
||||
#endif
|
||||
ENTRY(user_break_point_trap)
|
||||
.long break_point_trap /* 1E0 */
|
||||
ENTRY(interrupt_table)
|
||||
! external hardware
|
||||
.long do_IRQ ! 0000 /* 200 */
|
||||
.long do_IRQ ! 0001
|
||||
.long do_IRQ ! 0010
|
||||
.long do_IRQ ! 0011
|
||||
.long do_IRQ ! 0100
|
||||
.long do_IRQ ! 0101
|
||||
.long do_IRQ ! 0110
|
||||
.long do_IRQ ! 0111
|
||||
.long do_IRQ ! 1000 /* 300 */
|
||||
.long do_IRQ ! 1001
|
||||
.long do_IRQ ! 1010
|
||||
.long do_IRQ ! 1011
|
||||
.long do_IRQ ! 1100
|
||||
.long do_IRQ ! 1101
|
||||
.long do_IRQ ! 1110
|
||||
.long exception_error
|
||||
! Internal hardware
|
||||
.long do_IRQ ! TMU0 tuni0 /* 400 */
|
||||
.long do_IRQ ! TMU1 tuni1
|
||||
.long do_IRQ ! TMU2 tuni2
|
||||
.long do_IRQ ! ticpi2
|
||||
.long do_IRQ ! RTC ati
|
||||
.long do_IRQ ! pri
|
||||
.long do_IRQ ! cui
|
||||
.long do_IRQ ! SCI eri
|
||||
.long do_IRQ ! rxi /* 500 */
|
||||
.long do_IRQ ! txi
|
||||
.long do_IRQ ! tei
|
||||
.long do_IRQ ! WDT iti /* 560 */
|
||||
.long do_IRQ ! REF rcmi
|
||||
.long do_IRQ ! rovi
|
||||
.long do_IRQ
|
||||
.long do_IRQ /* 5E0 */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
.long do_IRQ ! 32 IRQ irq0 /* 600 */
|
||||
.long do_IRQ ! 33 irq1
|
||||
.long do_IRQ ! 34 irq2
|
||||
.long do_IRQ ! 35 irq3
|
||||
.long do_IRQ ! 36 irq4
|
||||
.long do_IRQ ! 37 irq5
|
||||
.long do_IRQ ! 38
|
||||
.long do_IRQ ! 39
|
||||
.long do_IRQ ! 40 PINT pint0-7 /* 700 */
|
||||
.long do_IRQ ! 41 pint8-15
|
||||
.long do_IRQ ! 42
|
||||
.long do_IRQ ! 43
|
||||
.long do_IRQ ! 44
|
||||
.long do_IRQ ! 45
|
||||
.long do_IRQ ! 46
|
||||
.long do_IRQ ! 47
|
||||
.long do_IRQ ! 48 DMAC dei0 /* 800 */
|
||||
.long do_IRQ ! 49 dei1
|
||||
.long do_IRQ ! 50 dei2
|
||||
.long do_IRQ ! 51 dei3
|
||||
.long do_IRQ ! 52 IrDA eri1
|
||||
.long do_IRQ ! 53 rxi1
|
||||
.long do_IRQ ! 54 bri1
|
||||
.long do_IRQ ! 55 txi1
|
||||
.long do_IRQ ! 56 SCIF eri2
|
||||
.long do_IRQ ! 57 rxi2
|
||||
.long do_IRQ ! 58 bri2
|
||||
.long do_IRQ ! 59 txi2
|
||||
.long do_IRQ ! 60 ADC adi /* 980 */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
.long exception_none ! 61 /* 9A0 */
|
||||
.long exception_none ! 62
|
||||
.long exception_none ! 63
|
||||
.long exception_none ! 64 /* A00 */
|
||||
.long do_IRQ ! 65 USB usi0
|
||||
.long do_IRQ ! 66 usi1
|
||||
.long exception_none ! 67
|
||||
.long exception_none ! 68
|
||||
.long exception_none ! 69
|
||||
.long exception_none ! 70
|
||||
.long exception_none ! 71
|
||||
.long exception_none ! 72 /* B00 */
|
||||
.long exception_none ! 73
|
||||
.long exception_none ! 74
|
||||
.long exception_none ! 75
|
||||
.long exception_none ! 76
|
||||
.long exception_none ! 77
|
||||
.long exception_none ! 78
|
||||
.long exception_none ! 79
|
||||
.long do_IRQ ! 80 TPU0 tpi0 /* C00 */
|
||||
.long do_IRQ ! 81 TPU1 tpi1
|
||||
.long exception_none ! 82
|
||||
.long exception_none ! 83
|
||||
.long do_IRQ ! 84 TPU2 tpi2
|
||||
.long do_IRQ ! 85 TPU3 tpi3 /* CA0 */
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
.long do_IRQ ! 61 LCDC lcdi /* 9A0 */
|
||||
.long do_IRQ ! 62 PCC pcc0i
|
||||
.long do_IRQ ! 63 pcc1i /* 9E0 */
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
.long exception_none ! 61 /* 9A0 */
|
||||
.long exception_none ! 62
|
||||
.long exception_none ! 63
|
||||
.long exception_none ! 64 /* A00 */
|
||||
.long exception_none ! 65
|
||||
.long exception_none ! 66
|
||||
.long exception_none ! 67
|
||||
.long exception_none ! 68
|
||||
.long exception_none ! 69
|
||||
.long exception_none ! 70
|
||||
.long exception_none ! 71
|
||||
.long exception_none ! 72 /* B00 */
|
||||
.long exception_none ! 73
|
||||
.long exception_none ! 74
|
||||
.long exception_none ! 75
|
||||
.long do_IRQ ! 76 DMAC2 dei4 /* B80 */
|
||||
.long do_IRQ ! 77 DMAC2 dei5
|
||||
.long exception_none ! 78
|
||||
.long do_IRQ ! 79 IPSEC ipseci /* BE0 */
|
||||
.long do_IRQ ! 80 EDMAC eint0 /* C00 */
|
||||
.long do_IRQ ! 81 EDMAC eint1
|
||||
.long do_IRQ ! 82 EDMAC eint2
|
||||
.long exception_none ! 83 /* C60 */
|
||||
.long exception_none ! 84
|
||||
.long exception_none ! 85
|
||||
.long exception_none ! 86
|
||||
.long exception_none ! 87
|
||||
.long exception_none ! 88 /* D00 */
|
||||
.long exception_none ! 89
|
||||
.long exception_none ! 90
|
||||
.long exception_none ! 91
|
||||
.long exception_none ! 92
|
||||
.long exception_none ! 93
|
||||
.long exception_none ! 94
|
||||
.long exception_none ! 95
|
||||
.long do_IRQ ! 96 SIOF eri0 /* E00 */
|
||||
.long do_IRQ ! 97 txi0
|
||||
.long do_IRQ ! 98 rxi0
|
||||
.long do_IRQ ! 99 cci0
|
||||
.long do_IRQ ! 100 eri1 /* E80 */
|
||||
.long do_IRQ ! 101 txi1
|
||||
.long do_IRQ ! 102 rxi2
|
||||
.long do_IRQ ! 103 cci3
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
.long do_IRQ ! 64
|
||||
.long do_IRQ ! 65
|
||||
.long do_IRQ ! 66
|
||||
.long do_IRQ ! 67
|
||||
.long do_IRQ ! 68
|
||||
.long do_IRQ ! 69
|
||||
.long do_IRQ ! 70
|
||||
.long do_IRQ ! 71
|
||||
.long do_IRQ ! 72
|
||||
.long do_IRQ ! 73
|
||||
.long do_IRQ ! 74
|
||||
.long do_IRQ ! 75
|
||||
.long do_IRQ ! 76
|
||||
.long do_IRQ ! 77
|
||||
.long do_IRQ ! 78
|
||||
.long do_IRQ ! 79
|
||||
.long do_IRQ ! 80 SCIF0(SH7300)
|
||||
.long do_IRQ ! 81
|
||||
.long do_IRQ ! 82
|
||||
.long do_IRQ ! 83
|
||||
.long do_IRQ ! 84
|
||||
.long do_IRQ ! 85
|
||||
.long do_IRQ ! 86
|
||||
.long do_IRQ ! 87
|
||||
.long do_IRQ ! 88
|
||||
.long do_IRQ ! 89
|
||||
.long do_IRQ ! 90
|
||||
.long do_IRQ ! 91
|
||||
.long do_IRQ ! 92
|
||||
.long do_IRQ ! 93
|
||||
.long do_IRQ ! 94
|
||||
.long do_IRQ ! 95
|
||||
.long do_IRQ ! 96
|
||||
.long do_IRQ ! 97
|
||||
.long do_IRQ ! 98
|
||||
.long do_IRQ ! 99
|
||||
.long do_IRQ ! 100
|
||||
.long do_IRQ ! 101
|
||||
.long do_IRQ ! 102
|
||||
.long do_IRQ ! 103
|
||||
.long do_IRQ ! 104
|
||||
.long do_IRQ ! 105
|
||||
.long do_IRQ ! 106
|
||||
.long do_IRQ ! 107
|
||||
.long do_IRQ ! 108
|
||||
#endif
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+33
-10
@@ -1,9 +1,8 @@
|
||||
/* $Id: entry.S,v 1.37 2004/06/11 13:02:46 doyu Exp $
|
||||
*
|
||||
/*
|
||||
* linux/arch/sh/entry.S
|
||||
*
|
||||
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2003 - 2006 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
@@ -78,7 +77,6 @@ OFF_TRA = (16*4+6*4)
|
||||
#define k3 r3
|
||||
#define k4 r4
|
||||
|
||||
#define k_ex_code r2_bank /* r2_bank1 */
|
||||
#define g_imask r6 /* r6_bank1 */
|
||||
#define k_g_imask r6_bank /* r6_bank1 */
|
||||
#define current r7 /* r7_bank1 */
|
||||
@@ -691,7 +689,7 @@ interrupt:
|
||||
0:
|
||||
#endif /* defined(CONFIG_KGDB_NMI) */
|
||||
bra handle_exception
|
||||
mov.l @k2, k2
|
||||
mov #-1, k2 ! interrupt exception marker
|
||||
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
@@ -717,8 +715,7 @@ ENTRY(handle_exception)
|
||||
add current, k1
|
||||
mov k1, r15 ! change to kernel stack
|
||||
!
|
||||
1: mov #-1, k4
|
||||
mov.l 2f, k1
|
||||
1: mov.l 2f, k1
|
||||
!
|
||||
#ifdef CONFIG_SH_DSP
|
||||
mov.l r2, @-r15 ! Save r2, we need another reg
|
||||
@@ -763,6 +760,8 @@ skip_save:
|
||||
#endif
|
||||
! Save the user registers on the stack.
|
||||
mov.l k2, @-r15 ! EXPEVT
|
||||
|
||||
mov #-1, k4
|
||||
mov.l k4, @-r15 ! set TRA (default: -1)
|
||||
!
|
||||
sts.l macl, @-r15
|
||||
@@ -797,8 +796,21 @@ skip_save:
|
||||
mov.l r2, @-r15
|
||||
mov.l r1, @-r15
|
||||
mov.l r0, @-r15
|
||||
! Then, dispatch to the handler, according to the exception code.
|
||||
stc k_ex_code, r8
|
||||
|
||||
/*
|
||||
* This gets a bit tricky.. in the INTEVT case we don't want to use
|
||||
* the VBR offset as a destination in the jump call table, since all
|
||||
* of the destinations are the same. In this case, (interrupt) sets
|
||||
* a marker in r2 (now r2_bank since SR.RB changed), which we check
|
||||
* to determine the exception type. For all other exceptions, we
|
||||
* forcibly read EXPEVT from memory and fix up the jump address, in
|
||||
* the interrupt exception case we jump to do_IRQ() and defer the
|
||||
* INTEVT read until there. As a bonus, we can also clean up the SR.RB
|
||||
* checks that do_IRQ() was doing..
|
||||
*/
|
||||
stc r2_bank, r8
|
||||
cmp/pz r8
|
||||
bf interrupt_exception
|
||||
shlr2 r8
|
||||
shlr r8
|
||||
mov.l 4f, r9
|
||||
@@ -806,6 +818,8 @@ skip_save:
|
||||
mov.l @r9, r9
|
||||
jmp @r9
|
||||
nop
|
||||
rts
|
||||
nop
|
||||
|
||||
.align 2
|
||||
1: .long 0x00001000 ! DSP=1
|
||||
@@ -813,8 +827,17 @@ skip_save:
|
||||
3: .long 0xcfffffff ! RB=0, BL=0
|
||||
4: .long exception_handling_table
|
||||
|
||||
interrupt_exception:
|
||||
mov.l 1f, r9
|
||||
jmp @r9
|
||||
nop
|
||||
rts
|
||||
nop
|
||||
|
||||
.align 2
|
||||
1: .long do_IRQ
|
||||
|
||||
.align 2
|
||||
ENTRY(exception_none)
|
||||
rts
|
||||
nop
|
||||
|
||||
|
||||
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