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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...
This commit is contained in:
Linus Torvalds
+2
-2
@@ -1012,9 +1012,9 @@ config BOOT_ELF32
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config MIPS_L1_CACHE_SHIFT
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int
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default "4" if MACH_DECSTATION || MIKROTIK_RB532
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default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
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default "6" if MIPS_CPU_SCACHE
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default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
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default "4" if PMC_MSP4200_EVAL
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default "5"
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config HAVE_STD_PC_SERIAL_PORT
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@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr)
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au_sync();
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}
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static void au1x_ic0_maskack(unsigned int irq_nr)
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{
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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au_writel(1 << bit, IC0_WAKECLR);
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au_writel(1 << bit, IC0_MASKCLR);
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au_writel(1 << bit, IC0_RISINGCLR);
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au_writel(1 << bit, IC0_FALLINGCLR);
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au_sync();
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}
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static void au1x_ic1_maskack(unsigned int irq_nr)
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{
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unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
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au_writel(1 << bit, IC1_WAKECLR);
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au_writel(1 << bit, IC1_MASKCLR);
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au_writel(1 << bit, IC1_RISINGCLR);
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au_writel(1 << bit, IC1_FALLINGCLR);
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au_sync();
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}
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static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
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{
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unsigned int bit = irq - AU1000_INTC1_INT_BASE;
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@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
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/*
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* irq_chips for both ICs; this way the mask handlers can be
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* as short as possible.
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*
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* NOTE: the ->ack() callback is used by the handle_edge_irq
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* flowhandler only, the ->mask_ack() one by handle_level_irq,
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* so no need for an irq_chip for each type of irq (level/edge).
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*/
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static struct irq_chip au1x_ic0_chip = {
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.name = "Alchemy-IC0",
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.ack = au1x_ic0_ack, /* edge */
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.ack = au1x_ic0_ack,
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.mask = au1x_ic0_mask,
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.mask_ack = au1x_ic0_mask, /* level */
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.mask_ack = au1x_ic0_maskack,
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.unmask = au1x_ic0_unmask,
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.set_type = au1x_ic_settype,
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};
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static struct irq_chip au1x_ic1_chip = {
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.name = "Alchemy-IC1",
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.ack = au1x_ic1_ack, /* edge */
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.ack = au1x_ic1_ack,
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.mask = au1x_ic1_mask,
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.mask_ack = au1x_ic1_mask, /* level */
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.mask_ack = au1x_ic1_maskack,
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.unmask = au1x_ic1_unmask,
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.set_type = au1x_ic_settype,
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.set_wake = au1x_ic1_setwake,
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@@ -69,6 +69,7 @@ void __init board_setup(void)
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#else
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au_writel(0xf, Au1500_PCI_CFG);
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#endif
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board_pci_idsel = mtx1_pci_idsel;
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#endif
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/* Initialize sys_pinfunc */
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@@ -85,8 +86,6 @@ void __init board_setup(void)
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alchemy_gpio_direction_output(211, 1); /* green on */
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alchemy_gpio_direction_output(212, 0); /* red off */
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board_pci_idsel = mtx1_pci_idsel;
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printk(KERN_INFO "4G Systems MTX-1 Board\n");
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}
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@@ -503,6 +503,7 @@ static int __init ar7_register_devices(void)
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{
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u16 chip_id;
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int res;
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u32 *bootcr, val;
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#ifdef CONFIG_SERIAL_8250
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static struct uart_port uart_port[2];
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@@ -595,7 +596,13 @@ static int __init ar7_register_devices(void)
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ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
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res = platform_device_register(&ar7_wdt);
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bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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val = *bootcr;
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iounmap(bootcr);
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/* Register watchdog only if enabled in hardware */
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if (val & AR7_WDT_HW_ENA)
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res = platform_device_register(&ar7_wdt);
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return res;
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}
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@@ -1,5 +1,5 @@
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obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
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dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o
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dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += boards/
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@@ -24,7 +24,6 @@
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#include <bcm63xx_dev_enet.h>
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#include <bcm63xx_dev_dsp.h>
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#include <bcm63xx_dev_pcmcia.h>
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#include <bcm63xx_dev_uart.h>
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#include <board_bcm963xx.h>
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#define PFX "board_bcm963xx: "
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@@ -794,8 +793,6 @@ int __init board_register_devices(void)
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{
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u32 val;
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bcm63xx_uart_register();
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if (board.has_pccard)
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bcm63xx_pcmcia_register();
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@@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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#include <asm/cpu-info.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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@@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void)
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{
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unsigned int tmp, expected_cpu_id;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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/* soc registers location depends on cpu type */
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expected_cpu_id = 0;
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@@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void)
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* BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
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*/
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case CPU_BCM3302:
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__cpu_name[cpu] = "Broadcom BCM6338";
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expected_cpu_id = BCM6338_CPU_ID;
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bcm63xx_regs_base = bcm96338_regs_base;
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bcm63xx_irqs = bcm96338_irqs;
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@@ -10,7 +10,6 @@
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_dev_uart.h>
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static struct resource uart_resources[] = {
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{
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@@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void)
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uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
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return platform_device_register(&bcm63xx_uart_device);
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}
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arch_initcall(bcm63xx_uart_register);
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@@ -0,0 +1,37 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <bcm63xx_cpu.h>
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static struct resource wdt_resources[] = {
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{
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.start = -1, /* filled at runtime */
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.end = -1, /* filled at runtime */
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device bcm63xx_wdt_device = {
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.name = "bcm63xx-wdt",
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.id = 0,
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.num_resources = ARRAY_SIZE(wdt_resources),
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.resource = wdt_resources,
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};
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int __init bcm63xx_wdt_register(void)
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{
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wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT);
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wdt_resources[0].end = wdt_resources[0].start;
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wdt_resources[0].end += RSET_WDT_SIZE - 1;
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return platform_device_register(&bcm63xx_wdt_device);
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}
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arch_initcall(bcm63xx_wdt_register);
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@@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void)
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bcm6348_a1_reboot();
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printk(KERN_INFO "triggering watchdog soft-reset...\n");
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bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
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reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
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reg |= SYS_PLL_SOFT_RESET;
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bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
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while (1)
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;
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}
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@@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
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DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
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DEFINE_SPINLOCK(octeon_irq_msi_lock);
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static int octeon_coreid_for_cpu(int cpu)
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{
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#ifdef CONFIG_SMP
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return cpu_logical_map(cpu);
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#else
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return cvmx_get_core_num();
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#endif
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}
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static void octeon_irq_core_ack(unsigned int irq)
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{
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unsigned int bit = irq - OCTEON_IRQ_SW0;
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@@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
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int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
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unsigned long flags;
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uint64_t en0;
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#ifdef CONFIG_SMP
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int cpu;
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write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
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for_each_online_cpu(cpu) {
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int coreid = cpu_logical_map(cpu);
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int coreid = octeon_coreid_for_cpu(cpu);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 &= ~(1ull << bit);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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@@ -167,26 +175,57 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
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*/
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cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
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write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
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#else
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int coreid = cvmx_get_core_num();
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local_irq_save(flags);
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en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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en0 &= ~(1ull << bit);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
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cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
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local_irq_restore(flags);
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#endif
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}
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|
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/*
|
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
|
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*/
|
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static void octeon_irq_ciu0_enable_v2(unsigned int irq)
|
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{
|
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int index = cvmx_get_core_num() * 2;
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u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
|
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|
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
|
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}
|
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|
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/*
|
||||
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
|
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* registers.
|
||||
*/
|
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static void octeon_irq_ciu0_disable_v2(unsigned int irq)
|
||||
{
|
||||
int index = cvmx_get_core_num() * 2;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
|
||||
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
|
||||
}
|
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|
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/*
|
||||
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
|
||||
{
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
|
||||
int index;
|
||||
int cpu;
|
||||
for_each_online_cpu(cpu) {
|
||||
index = octeon_coreid_for_cpu(cpu) * 2;
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
|
||||
{
|
||||
int cpu;
|
||||
unsigned long flags;
|
||||
int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
|
||||
|
||||
write_lock(&octeon_irq_ciu0_rwlock);
|
||||
write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
|
||||
for_each_online_cpu(cpu) {
|
||||
int coreid = cpu_logical_map(cpu);
|
||||
int coreid = octeon_coreid_for_cpu(cpu);
|
||||
uint64_t en0 =
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
|
||||
if (cpumask_test_cpu(cpu, dest))
|
||||
@@ -200,12 +239,46 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
|
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* of them are done.
|
||||
*/
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
|
||||
write_unlock(&octeon_irq_ciu0_rwlock);
|
||||
write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set affinity for the irq for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
|
||||
const struct cpumask *dest)
|
||||
{
|
||||
int cpu;
|
||||
int index;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
|
||||
for_each_online_cpu(cpu) {
|
||||
index = octeon_coreid_for_cpu(cpu) * 2;
|
||||
if (cpumask_test_cpu(cpu, dest))
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
|
||||
else
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Newer octeon chips have support for lockless CIU operation.
|
||||
*/
|
||||
static struct irq_chip octeon_irq_chip_ciu0_v2 = {
|
||||
.name = "CIU0",
|
||||
.enable = octeon_irq_ciu0_enable_v2,
|
||||
.disable = octeon_irq_ciu0_disable_all_v2,
|
||||
.ack = octeon_irq_ciu0_disable_v2,
|
||||
.eoi = octeon_irq_ciu0_enable_v2,
|
||||
#ifdef CONFIG_SMP
|
||||
.set_affinity = octeon_irq_ciu0_set_affinity_v2,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct irq_chip octeon_irq_chip_ciu0 = {
|
||||
.name = "CIU0",
|
||||
.enable = octeon_irq_ciu0_enable,
|
||||
@@ -269,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
|
||||
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
||||
unsigned long flags;
|
||||
uint64_t en1;
|
||||
#ifdef CONFIG_SMP
|
||||
int cpu;
|
||||
write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
|
||||
for_each_online_cpu(cpu) {
|
||||
int coreid = cpu_logical_map(cpu);
|
||||
int coreid = octeon_coreid_for_cpu(cpu);
|
||||
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
||||
en1 &= ~(1ull << bit);
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
||||
@@ -284,26 +356,58 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
|
||||
*/
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
|
||||
write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
|
||||
#else
|
||||
int coreid = cvmx_get_core_num();
|
||||
local_irq_save(flags);
|
||||
en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
||||
en1 &= ~(1ull << bit);
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
|
||||
local_irq_restore(flags);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the irq on the current core for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static void octeon_irq_ciu1_enable_v2(unsigned int irq)
|
||||
{
|
||||
int index = cvmx_get_core_num() * 2 + 1;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable the irq on the current core for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static void octeon_irq_ciu1_disable_v2(unsigned int irq)
|
||||
{
|
||||
int index = cvmx_get_core_num() * 2 + 1;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable the irq on the all cores for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
|
||||
{
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
int index;
|
||||
int cpu;
|
||||
for_each_online_cpu(cpu) {
|
||||
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
|
||||
static int octeon_irq_ciu1_set_affinity(unsigned int irq,
|
||||
const struct cpumask *dest)
|
||||
{
|
||||
int cpu;
|
||||
unsigned long flags;
|
||||
int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
|
||||
|
||||
write_lock(&octeon_irq_ciu1_rwlock);
|
||||
write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
|
||||
for_each_online_cpu(cpu) {
|
||||
int coreid = cpu_logical_map(cpu);
|
||||
int coreid = octeon_coreid_for_cpu(cpu);
|
||||
uint64_t en1 =
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1
|
||||
(coreid * 2 + 1));
|
||||
@@ -318,12 +422,46 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
|
||||
* of them are done.
|
||||
*/
|
||||
cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
|
||||
write_unlock(&octeon_irq_ciu1_rwlock);
|
||||
write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set affinity for the irq for chips that have the EN*_W1{S,C}
|
||||
* registers.
|
||||
*/
|
||||
static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
|
||||
const struct cpumask *dest)
|
||||
{
|
||||
int cpu;
|
||||
int index;
|
||||
u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
|
||||
for_each_online_cpu(cpu) {
|
||||
index = octeon_coreid_for_cpu(cpu) * 2 + 1;
|
||||
if (cpumask_test_cpu(cpu, dest))
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
|
||||
else
|
||||
cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Newer octeon chips have support for lockless CIU operation.
|
||||
*/
|
||||
static struct irq_chip octeon_irq_chip_ciu1_v2 = {
|
||||
.name = "CIU0",
|
||||
.enable = octeon_irq_ciu1_enable_v2,
|
||||
.disable = octeon_irq_ciu1_disable_all_v2,
|
||||
.ack = octeon_irq_ciu1_disable_v2,
|
||||
.eoi = octeon_irq_ciu1_enable_v2,
|
||||
#ifdef CONFIG_SMP
|
||||
.set_affinity = octeon_irq_ciu1_set_affinity_v2,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct irq_chip octeon_irq_chip_ciu1 = {
|
||||
.name = "CIU1",
|
||||
.enable = octeon_irq_ciu1_enable,
|
||||
@@ -420,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = {
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
struct irq_chip *chip0;
|
||||
struct irq_chip *chip1;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* Set the default affinity to the boot cpu. */
|
||||
@@ -430,6 +570,16 @@ void __init arch_init_irq(void)
|
||||
if (NR_IRQS < OCTEON_IRQ_LAST)
|
||||
pr_err("octeon_irq_init: NR_IRQS is set too low\n");
|
||||
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
|
||||
OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
|
||||
chip0 = &octeon_irq_chip_ciu0_v2;
|
||||
chip1 = &octeon_irq_chip_ciu1_v2;
|
||||
} else {
|
||||
chip0 = &octeon_irq_chip_ciu0;
|
||||
chip1 = &octeon_irq_chip_ciu1;
|
||||
}
|
||||
|
||||
/* 0 - 15 reserved for i8259 master and slave controller. */
|
||||
|
||||
/* 17 - 23 Mips internal */
|
||||
@@ -440,14 +590,12 @@ void __init arch_init_irq(void)
|
||||
|
||||
/* 24 - 87 CIU_INT_SUM0 */
|
||||
for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
|
||||
set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
|
||||
handle_percpu_irq);
|
||||
set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
|
||||
}
|
||||
|
||||
/* 88 - 151 CIU_INT_SUM1 */
|
||||
for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
|
||||
set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
|
||||
handle_percpu_irq);
|
||||
set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
@@ -505,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
|
||||
{
|
||||
unsigned int isset;
|
||||
#ifdef CONFIG_SMP
|
||||
int coreid = cpu_logical_map(cpu);
|
||||
#else
|
||||
int coreid = cvmx_get_core_num();
|
||||
#endif
|
||||
unsigned int isset;
|
||||
int coreid = octeon_coreid_for_cpu(cpu);
|
||||
int bit = (irq < OCTEON_IRQ_WDOG0) ?
|
||||
irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
|
||||
irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
|
||||
if (irq < 64) {
|
||||
isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
|
||||
(1ull << bit)) >> bit;
|
||||
|
||||
@@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action)
|
||||
cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
|
||||
}
|
||||
|
||||
static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
|
||||
static inline void octeon_send_ipi_mask(const struct cpumask *mask,
|
||||
unsigned int action)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for_each_cpu_mask(i, mask)
|
||||
for_each_cpu_mask(i, *mask)
|
||||
octeon_send_ipi_single(i, action);
|
||||
}
|
||||
|
||||
|
||||
@@ -48,9 +48,9 @@ enum fixed_addresses {
|
||||
#define FIX_N_COLOURS 8
|
||||
FIX_CMAP_BEGIN,
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
|
||||
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
|
||||
#else
|
||||
FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
|
||||
FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
|
||||
#endif
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
/* reserved pte's for temporary kernel mappings */
|
||||
|
||||
@@ -19,15 +19,20 @@
|
||||
#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
|
||||
|
||||
/* Offsets to individual GCMP registers from GCMP base */
|
||||
#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
|
||||
#define GCMPOFS(block, tag, reg) \
|
||||
(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
|
||||
#define GCMPOFSn(block, tag, reg, n) \
|
||||
(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
|
||||
|
||||
#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
|
||||
#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
|
||||
#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
|
||||
#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
|
||||
#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
|
||||
|
||||
/* GCMP register access */
|
||||
#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
|
||||
#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
|
||||
#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
|
||||
#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
|
||||
#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
|
||||
@@ -49,10 +54,10 @@
|
||||
#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
|
||||
#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
|
||||
#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
|
||||
#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
|
||||
#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
|
||||
@@ -115,5 +120,6 @@
|
||||
#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
|
||||
|
||||
extern int __init gcmp_probe(unsigned long, unsigned long);
|
||||
|
||||
extern int __init gcmp_niocu(void);
|
||||
extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
|
||||
#endif /* _ASM_GCMPREGS_H */
|
||||
|
||||
+18
-170
@@ -12,7 +12,6 @@
|
||||
#define _ASM_GICREGS_H
|
||||
|
||||
#undef GICISBYTELITTLEENDIAN
|
||||
#define GICISWORDLITTLEENDIAN
|
||||
|
||||
/* Constants */
|
||||
#define GIC_POL_POS 1
|
||||
@@ -20,11 +19,7 @@
|
||||
#define GIC_TRIG_EDGE 1
|
||||
#define GIC_TRIG_LEVEL 0
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
|
||||
#else
|
||||
#define GIC_NUM_INTRS 32
|
||||
#endif
|
||||
|
||||
#define MSK(n) ((1 << (n)) - 1)
|
||||
#define REG32(addr) (*(volatile unsigned int *) (addr))
|
||||
@@ -70,13 +65,13 @@
|
||||
#define USM_VISIBLE_SECTION_SIZE 0x10000
|
||||
|
||||
/* Register Map for Shared Section */
|
||||
#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
|
||||
|
||||
#define GIC_SH_CONFIG_OFS 0x0000
|
||||
|
||||
/* Shared Global Counter */
|
||||
#define GIC_SH_COUNTER_31_00_OFS 0x0010
|
||||
#define GIC_SH_COUNTER_63_32_OFS 0x0014
|
||||
#define GIC_SH_REVISIONID_OFS 0x0020
|
||||
|
||||
/* Interrupt Polarity */
|
||||
#define GIC_SH_POL_31_0_OFS 0x0100
|
||||
@@ -164,24 +159,31 @@
|
||||
(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
|
||||
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
|
||||
|
||||
/* Convert an interrupt number to a byte offset/bit for multi-word registers */
|
||||
#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
|
||||
#define GIC_INTR_BIT(intr) ((intr) % 32)
|
||||
|
||||
/* Polarity : Reset Value is always 0 */
|
||||
#define GIC_SH_SET_POLARITY_OFS 0x0100
|
||||
#define GIC_SET_POLARITY(intr, pol) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
|
||||
GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
|
||||
|
||||
/* Triggering : Reset Value is always 0 */
|
||||
#define GIC_SH_SET_TRIGGER_OFS 0x0180
|
||||
#define GIC_SET_TRIGGER(intr, trig) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
|
||||
GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
|
||||
|
||||
/* Mask manipulation */
|
||||
#define GIC_SH_SMASK_OFS 0x0380
|
||||
#define GIC_SET_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
#define GIC_SET_INTR_MASK(intr) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
|
||||
GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
|
||||
#define GIC_SH_RMASK_OFS 0x0300
|
||||
#define GIC_CLR_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
|
||||
#define GIC_CLR_INTR_MASK(intr) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
|
||||
GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
|
||||
|
||||
/* Register Map for Local Section */
|
||||
#define GIC_VPE_CTL_OFS 0x0000
|
||||
@@ -219,161 +221,6 @@
|
||||
#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
|
||||
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
|
||||
|
||||
#else /* CONFIG_CPU_BIG_ENDIAN */
|
||||
|
||||
#define GIC_SH_CONFIG_OFS 0x0000
|
||||
|
||||
/* Shared Global Counter */
|
||||
#define GIC_SH_COUNTER_31_00_OFS 0x0014
|
||||
#define GIC_SH_COUNTER_63_32_OFS 0x0010
|
||||
|
||||
/* Interrupt Polarity */
|
||||
#define GIC_SH_POL_31_0_OFS 0x0104
|
||||
#define GIC_SH_POL_63_32_OFS 0x0100
|
||||
#define GIC_SH_POL_95_64_OFS 0x010c
|
||||
#define GIC_SH_POL_127_96_OFS 0x0108
|
||||
#define GIC_SH_POL_159_128_OFS 0x0114
|
||||
#define GIC_SH_POL_191_160_OFS 0x0110
|
||||
#define GIC_SH_POL_223_192_OFS 0x011c
|
||||
#define GIC_SH_POL_255_224_OFS 0x0118
|
||||
|
||||
/* Edge/Level Triggering */
|
||||
#define GIC_SH_TRIG_31_0_OFS 0x0184
|
||||
#define GIC_SH_TRIG_63_32_OFS 0x0180
|
||||
#define GIC_SH_TRIG_95_64_OFS 0x018c
|
||||
#define GIC_SH_TRIG_127_96_OFS 0x0188
|
||||
#define GIC_SH_TRIG_159_128_OFS 0x0194
|
||||
#define GIC_SH_TRIG_191_160_OFS 0x0190
|
||||
#define GIC_SH_TRIG_223_192_OFS 0x019c
|
||||
#define GIC_SH_TRIG_255_224_OFS 0x0198
|
||||
|
||||
/* Dual Edge Triggering */
|
||||
#define GIC_SH_DUAL_31_0_OFS 0x0204
|
||||
#define GIC_SH_DUAL_63_32_OFS 0x0200
|
||||
#define GIC_SH_DUAL_95_64_OFS 0x020c
|
||||
#define GIC_SH_DUAL_127_96_OFS 0x0208
|
||||
#define GIC_SH_DUAL_159_128_OFS 0x0214
|
||||
#define GIC_SH_DUAL_191_160_OFS 0x0210
|
||||
#define GIC_SH_DUAL_223_192_OFS 0x021c
|
||||
#define GIC_SH_DUAL_255_224_OFS 0x0218
|
||||
|
||||
/* Set/Clear corresponding bit in Edge Detect Register */
|
||||
#define GIC_SH_WEDGE_OFS 0x0280
|
||||
|
||||
/* Reset Mask - Disables Interrupt */
|
||||
#define GIC_SH_RMASK_31_0_OFS 0x0304
|
||||
#define GIC_SH_RMASK_63_32_OFS 0x0300
|
||||
#define GIC_SH_RMASK_95_64_OFS 0x030c
|
||||
#define GIC_SH_RMASK_127_96_OFS 0x0308
|
||||
#define GIC_SH_RMASK_159_128_OFS 0x0314
|
||||
#define GIC_SH_RMASK_191_160_OFS 0x0310
|
||||
#define GIC_SH_RMASK_223_192_OFS 0x031c
|
||||
#define GIC_SH_RMASK_255_224_OFS 0x0318
|
||||
|
||||
/* Set Mask (WO) - Enables Interrupt */
|
||||
#define GIC_SH_SMASK_31_0_OFS 0x0384
|
||||
#define GIC_SH_SMASK_63_32_OFS 0x0380
|
||||
#define GIC_SH_SMASK_95_64_OFS 0x038c
|
||||
#define GIC_SH_SMASK_127_96_OFS 0x0388
|
||||
#define GIC_SH_SMASK_159_128_OFS 0x0394
|
||||
#define GIC_SH_SMASK_191_160_OFS 0x0390
|
||||
#define GIC_SH_SMASK_223_192_OFS 0x039c
|
||||
#define GIC_SH_SMASK_255_224_OFS 0x0398
|
||||
|
||||
/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
|
||||
#define GIC_SH_MASK_31_0_OFS 0x0404
|
||||
#define GIC_SH_MASK_63_32_OFS 0x0400
|
||||
#define GIC_SH_MASK_95_64_OFS 0x040c
|
||||
#define GIC_SH_MASK_127_96_OFS 0x0408
|
||||
#define GIC_SH_MASK_159_128_OFS 0x0414
|
||||
#define GIC_SH_MASK_191_160_OFS 0x0410
|
||||
#define GIC_SH_MASK_223_192_OFS 0x041c
|
||||
#define GIC_SH_MASK_255_224_OFS 0x0418
|
||||
|
||||
/* Pending Global Interrupts (RO) */
|
||||
#define GIC_SH_PEND_31_0_OFS 0x0484
|
||||
#define GIC_SH_PEND_63_32_OFS 0x0480
|
||||
#define GIC_SH_PEND_95_64_OFS 0x048c
|
||||
#define GIC_SH_PEND_127_96_OFS 0x0488
|
||||
#define GIC_SH_PEND_159_128_OFS 0x0494
|
||||
#define GIC_SH_PEND_191_160_OFS 0x0490
|
||||
#define GIC_SH_PEND_223_192_OFS 0x049c
|
||||
#define GIC_SH_PEND_255_224_OFS 0x0498
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
|
||||
|
||||
/* Maps Interrupt X to a Pin */
|
||||
#define GIC_SH_MAP_TO_PIN(intr) \
|
||||
(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
|
||||
|
||||
/*
|
||||
* Maps Interrupt X to a VPE. This is more complex than the LE case, as
|
||||
* odd and even registers need to be transposed. It does work - trust me!
|
||||
*/
|
||||
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
|
||||
(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
|
||||
(((((vpe) / 32) ^ 1) - 1) * 4))
|
||||
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
|
||||
|
||||
/* Polarity */
|
||||
#define GIC_SH_SET_POLARITY_OFS 0x0100
|
||||
#define GIC_SET_POLARITY(intr, pol) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
|
||||
|
||||
/* Triggering */
|
||||
#define GIC_SH_SET_TRIGGER_OFS 0x0180
|
||||
#define GIC_SET_TRIGGER(intr, trig) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
|
||||
|
||||
/* Mask manipulation */
|
||||
#define GIC_SH_SMASK_OFS 0x0380
|
||||
#define GIC_SET_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
#define GIC_SH_RMASK_OFS 0x0300
|
||||
#define GIC_CLR_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
/* Register Map for Local Section */
|
||||
#define GIC_VPE_CTL_OFS 0x0000
|
||||
#define GIC_VPE_PEND_OFS 0x0004
|
||||
#define GIC_VPE_MASK_OFS 0x0008
|
||||
#define GIC_VPE_RMASK_OFS 0x000c
|
||||
#define GIC_VPE_SMASK_OFS 0x0010
|
||||
#define GIC_VPE_WD_MAP_OFS 0x0040
|
||||
#define GIC_VPE_COMPARE_MAP_OFS 0x0044
|
||||
#define GIC_VPE_TIMER_MAP_OFS 0x0048
|
||||
#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
|
||||
#define GIC_VPE_SWINT0_MAP_OFS 0x0054
|
||||
#define GIC_VPE_SWINT1_MAP_OFS 0x0058
|
||||
#define GIC_VPE_OTHER_ADDR_OFS 0x0080
|
||||
#define GIC_VPE_WD_CONFIG0_OFS 0x0090
|
||||
#define GIC_VPE_WD_COUNT0_OFS 0x0094
|
||||
#define GIC_VPE_WD_INITIAL0_OFS 0x0098
|
||||
#define GIC_VPE_COMPARE_LO_OFS 0x00a4
|
||||
#define GIC_VPE_COMPARE_HI_OFS 0x00a0
|
||||
|
||||
#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
|
||||
#define GIC_VPE_EIC_SS(intr) \
|
||||
(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_EIC_VEC_BASE 0x0800
|
||||
#define GIC_VPE_EIC_VEC(intr) \
|
||||
(GIC_VPE_EIC_VEC_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_TENABLE_NMI_OFS 0x1000
|
||||
#define GIC_VPE_TENABLE_YQ_OFS 0x1004
|
||||
#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
|
||||
#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
|
||||
|
||||
/* User Mode Visible Section Register Map */
|
||||
#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
|
||||
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
|
||||
|
||||
#endif /* !LE */
|
||||
|
||||
/* Masks */
|
||||
#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
|
||||
#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
|
||||
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
|
||||
* in building ipi_map.
|
||||
*/
|
||||
struct gic_intr_map {
|
||||
unsigned int intrnum; /* Ext Intr Num */
|
||||
unsigned int cpunum; /* Directed to this CPU */
|
||||
unsigned int pin; /* Directed to this Pin */
|
||||
unsigned int polarity; /* Polarity : +/- */
|
||||
unsigned int trigtype; /* Trigger : Edge/Levl */
|
||||
unsigned int ipiflag; /* Is used for IPI ? */
|
||||
unsigned int flags; /* Misc flags */
|
||||
#define GIC_FLAG_IPI 0x01
|
||||
#define GIC_FLAG_TRANSPARENT 0x02
|
||||
};
|
||||
|
||||
extern void gic_init(unsigned long gic_base_addr,
|
||||
|
||||
@@ -78,6 +78,9 @@
|
||||
#define AR7_REF_CLOCK 25000000
|
||||
#define AR7_XTAL_CLOCK 24000000
|
||||
|
||||
/* DCL */
|
||||
#define AR7_WDT_HW_ENA 0x10
|
||||
|
||||
struct plat_cpmac_data {
|
||||
int reset_bit;
|
||||
int power_bit;
|
||||
|
||||
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio)
|
||||
|
||||
if ((gpio >= 8) && (gpio <= 15))
|
||||
return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
|
||||
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef BCM63XX_DEV_UART_H_
|
||||
#define BCM63XX_DEV_UART_H_
|
||||
|
||||
int bcm63xx_uart_register(void);
|
||||
|
||||
#endif /* BCM63XX_DEV_UART_H_ */
|
||||
@@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
|
||||
.busy_factor = 32, \
|
||||
.imbalance_pct = 125, \
|
||||
.cache_nice_tries = 1, \
|
||||
.flags = SD_LOAD_BALANCE \
|
||||
| SD_BALANCE_EXEC \
|
||||
.flags = SD_LOAD_BALANCE | \
|
||||
SD_BALANCE_EXEC, \
|
||||
.last_balance = jiffies, \
|
||||
.balance_interval = 1, \
|
||||
.nr_balance_failed = 0, \
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_counter 1
|
||||
#define cpu_has_dc_aliases 1
|
||||
#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_ejtag 0
|
||||
@@ -54,6 +54,5 @@
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_icache_snoops_remote_store 1
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user