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xtensa: add test_kc705_hifi variant
This variant has HiFi3 coprocessor and is used in sample audio-enabled configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
committed by
Chris Zankel
Chris Zankel
parent
2c684d892b
commit
9da8320bb9
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,328 @@
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/*
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* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
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*
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* NOTE: This header file is not meant to be included directly.
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*/
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/* This header file contains assembly-language definitions (assembly
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macros, etc.) for this specific Xtensa processor's TIE extensions
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and options. It is customized to this Xtensa processor configuration.
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Copyright (c) 1999-2014 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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/*
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* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger store sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to store. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to store, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any store.
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional global register used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1020, 4, 4
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rur.THREADPTR \at1 // threadptr option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1020, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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rsr.ACCLO \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.ACCHI \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1000, 4, 4
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rsr.M0 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rsr.M1 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+4
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rsr.M2 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+8
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rsr.M3 \at1 // MAC16 option
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s32i \at1, \ptr, .Lxchal_ofs_+12
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rsr.BR \at1 // boolean option
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s32i \at1, \ptr, .Lxchal_ofs_+16
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rsr.SCOMPARE1 \at1 // conditional store option
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s32i \at1, \ptr, .Lxchal_ofs_+20
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1000, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.endif
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.endm // xchal_ncp_store
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/*
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* Macro to restore all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 4 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters:
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* continue If macro invoked as part of a larger load sequence, set to 1
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* if this is not the first in the sequence. Defaults to 0.
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* ofs Offset from start of larger sequence (from value of first ptr
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* in sequence) at which to load. Defaults to next available space
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* (or 0 if <continue> is 0).
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* select Select what category(ies) of registers to load, as a bitmask
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* (see XTHAL_SAS_xxx constants). Defaults to all registers.
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* alloc Select what category(ies) of registers to allocate; if any
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* category is selected here that is not in <select>, space for
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* the corresponding registers is skipped without doing any load.
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Optional global register used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
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xchal_sa_align \ptr, 0, 1020, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wur.THREADPTR \at1 // threadptr option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1020, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
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.endif
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// Optional caller-saved registers used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1016, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.ACCLO \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.ACCHI \at1 // MAC16 option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1016, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
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.endif
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// Optional caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 1000, 4, 4
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wsr.M0 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wsr.M1 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+8
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wsr.M2 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+12
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wsr.M3 \at1 // MAC16 option
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l32i \at1, \ptr, .Lxchal_ofs_+16
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wsr.BR \at1 // boolean option
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l32i \at1, \ptr, .Lxchal_ofs_+20
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wsr.SCOMPARE1 \at1 // conditional store option
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 1000, 4, 4
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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/*
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* Macro to save the state of TIE coprocessor AudioEngineLX.
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 8 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters are the same as for xchal_ncp_store.
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*/
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#define xchal_cp_AudioEngineLX_store xchal_cp1_store
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.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Custom caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 0, 8, 8
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rur.AE_OVF_SAR \at1 // ureg 240
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s32i \at1, \ptr, .Lxchal_ofs_+0
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rur.AE_BITHEAD \at1 // ureg 241
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s32i \at1, \ptr, .Lxchal_ofs_+4
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rur.AE_TS_FTS_BU_BP \at1 // ureg 242
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s32i \at1, \ptr, .Lxchal_ofs_+8
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rur.AE_CW_SD_NO \at1 // ureg 243
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s32i \at1, \ptr, .Lxchal_ofs_+12
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rur.AE_CBEGIN0 \at1 // ureg 246
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s32i \at1, \ptr, .Lxchal_ofs_+16
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rur.AE_CEND0 \at1 // ureg 247
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s32i \at1, \ptr, .Lxchal_ofs_+20
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AE_S64.I aed0, \ptr, .Lxchal_ofs_+24
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AE_S64.I aed1, \ptr, .Lxchal_ofs_+32
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AE_S64.I aed2, \ptr, .Lxchal_ofs_+40
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AE_S64.I aed3, \ptr, .Lxchal_ofs_+48
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AE_S64.I aed4, \ptr, .Lxchal_ofs_+56
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addi \ptr, \ptr, 64
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AE_S64.I aed5, \ptr, .Lxchal_ofs_+0
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AE_S64.I aed6, \ptr, .Lxchal_ofs_+8
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AE_S64.I aed7, \ptr, .Lxchal_ofs_+16
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AE_S64.I aed8, \ptr, .Lxchal_ofs_+24
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AE_S64.I aed9, \ptr, .Lxchal_ofs_+32
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AE_S64.I aed10, \ptr, .Lxchal_ofs_+40
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AE_S64.I aed11, \ptr, .Lxchal_ofs_+48
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AE_S64.I aed12, \ptr, .Lxchal_ofs_+56
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addi \ptr, \ptr, 64
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AE_S64.I aed13, \ptr, .Lxchal_ofs_+0
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AE_S64.I aed14, \ptr, .Lxchal_ofs_+8
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AE_S64.I aed15, \ptr, .Lxchal_ofs_+16
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AE_SALIGN64.I u0, \ptr, .Lxchal_ofs_+24
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AE_SALIGN64.I u1, \ptr, .Lxchal_ofs_+32
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AE_SALIGN64.I u2, \ptr, .Lxchal_ofs_+40
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AE_SALIGN64.I u3, \ptr, .Lxchal_ofs_+48
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.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
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.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 0, 8, 8
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 184
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.endif
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.endm // xchal_cp1_store
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/*
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* Macro to restore the state of TIE coprocessor AudioEngineLX.
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* Required parameters:
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* ptr Save area pointer address register (clobbered)
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* (register must contain a 8 byte aligned address).
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* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
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* registers are clobbered, the remaining are unused).
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* Optional parameters are the same as for xchal_ncp_load.
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*/
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#define xchal_cp_AudioEngineLX_load xchal_cp1_load
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.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
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xchal_sa_start \continue, \ofs
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// Custom caller-saved registers not used by default by the compiler:
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.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
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xchal_sa_align \ptr, 0, 0, 8, 8
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l32i \at1, \ptr, .Lxchal_ofs_+0
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wur.AE_OVF_SAR \at1 // ureg 240
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l32i \at1, \ptr, .Lxchal_ofs_+4
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wur.AE_BITHEAD \at1 // ureg 241
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l32i \at1, \ptr, .Lxchal_ofs_+8
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wur.AE_TS_FTS_BU_BP \at1 // ureg 242
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l32i \at1, \ptr, .Lxchal_ofs_+12
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wur.AE_CW_SD_NO \at1 // ureg 243
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l32i \at1, \ptr, .Lxchal_ofs_+16
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wur.AE_CBEGIN0 \at1 // ureg 246
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l32i \at1, \ptr, .Lxchal_ofs_+20
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wur.AE_CEND0 \at1 // ureg 247
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AE_L64.I aed0, \ptr, .Lxchal_ofs_+24
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AE_L64.I aed1, \ptr, .Lxchal_ofs_+32
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AE_L64.I aed2, \ptr, .Lxchal_ofs_+40
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AE_L64.I aed3, \ptr, .Lxchal_ofs_+48
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AE_L64.I aed4, \ptr, .Lxchal_ofs_+56
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addi \ptr, \ptr, 64
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AE_L64.I aed5, \ptr, .Lxchal_ofs_+0
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AE_L64.I aed6, \ptr, .Lxchal_ofs_+8
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AE_L64.I aed7, \ptr, .Lxchal_ofs_+16
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AE_L64.I aed8, \ptr, .Lxchal_ofs_+24
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AE_L64.I aed9, \ptr, .Lxchal_ofs_+32
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AE_L64.I aed10, \ptr, .Lxchal_ofs_+40
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AE_L64.I aed11, \ptr, .Lxchal_ofs_+48
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AE_L64.I aed12, \ptr, .Lxchal_ofs_+56
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addi \ptr, \ptr, 64
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AE_L64.I aed13, \ptr, .Lxchal_ofs_+0
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AE_L64.I aed14, \ptr, .Lxchal_ofs_+8
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AE_L64.I aed15, \ptr, .Lxchal_ofs_+16
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AE_LALIGN64.I u0, \ptr, .Lxchal_ofs_+24
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AE_LALIGN64.I u1, \ptr, .Lxchal_ofs_+32
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AE_LALIGN64.I u2, \ptr, .Lxchal_ofs_+40
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AE_LALIGN64.I u3, \ptr, .Lxchal_ofs_+48
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.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
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.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
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xchal_sa_align \ptr, 0, 0, 8, 8
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.set .Lxchal_ofs_, .Lxchal_ofs_ + 184
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.endif
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.endm // xchal_cp1_load
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#define XCHAL_CP1_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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/* Empty macros for unconfigured coprocessors: */
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.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
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.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
@@ -0,0 +1,189 @@
|
||||
/*
|
||||
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file describes this specific Xtensa processor's TIE extensions
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Copyright (c) 1999-2014 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 2 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP1_NAME "AudioEngineLX"
|
||||
#define XCHAL_CP1_IDENT AudioEngineLX
|
||||
#define XCHAL_CP1_SA_SIZE 184 /* size of state save area */
|
||||
#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP7_NAME "XTIOP"
|
||||
#define XCHAL_CP7_IDENT XTIOP
|
||||
#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
|
||||
#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP0_SA_SIZE 0
|
||||
#define XCHAL_CP0_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 36
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 9
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 0
|
||||
#define XCHAL_CP0_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 26
|
||||
#define XCHAL_CP1_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1010, aed,0 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1011, aed,1 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1012, aed,2 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1013, aed,3 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1014, aed,4 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1015, aed,5 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1016, aed,6 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1017, aed,7 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1018, aed,8 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1019, aed,9 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x101A, aed,10 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x101B, aed,11 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x101C, aed,12 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x101D, aed,13 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x101E, aed,14 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x101F, aed,15 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1020, u,0 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1021, u,1 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1022, u,2 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1023, u,3 , 64,0,0,0)
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
Reference in New Issue
Block a user