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Merge tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Radim Krčmář:
"First batch of KVM changes for 4.15
Common:
- Python 3 support in kvm_stat
- Accounting of slabs to kmemcg
ARM:
- Optimized arch timer handling for KVM/ARM
- Improvements to the VGIC ITS code and introduction of an ITS reset
ioctl
- Unification of the 32-bit fault injection logic
- More exact external abort matching logic
PPC:
- Support for running hashed page table (HPT) MMU mode on a host that
is using the radix MMU mode; single threaded mode on POWER 9 is
added as a pre-requisite
- Resolution of merge conflicts with the last second 4.14 HPT fixes
- Fixes and cleanups
s390:
- Some initial preparation patches for exitless interrupts and crypto
- New capability for AIS migration
- Fixes
x86:
- Improved emulation of LAPIC timer mode changes, MCi_STATUS MSRs,
and after-reset state
- Refined dependencies for VMX features
- Fixes for nested SMI injection
- A lot of cleanups"
* tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (89 commits)
KVM: s390: provide a capability for AIS state migration
KVM: s390: clear_io_irq() requests are not expected for adapter interrupts
KVM: s390: abstract conversion between isc and enum irq_types
KVM: s390: vsie: use common code functions for pinning
KVM: s390: SIE considerations for AP Queue virtualization
KVM: s390: document memory ordering for kvm_s390_vcpu_wakeup
KVM: PPC: Book3S HV: Cosmetic post-merge cleanups
KVM: arm/arm64: fix the incompatible matching for external abort
KVM: arm/arm64: Unify 32bit fault injection
KVM: arm/arm64: vgic-its: Implement KVM_DEV_ARM_ITS_CTRL_RESET
KVM: arm/arm64: Document KVM_DEV_ARM_ITS_CTRL_RESET
KVM: arm/arm64: vgic-its: Free caches when GITS_BASER Valid bit is cleared
KVM: arm/arm64: vgic-its: New helper functions to free the caches
KVM: arm/arm64: vgic-its: Remove kvm_its_unmap_device
arm/arm64: KVM: Load the timer state when enabling the timer
KVM: arm/arm64: Rework kvm_timer_should_fire
KVM: arm/arm64: Get rid of kvm_timer_flush_hwstate
KVM: arm/arm64: Avoid phys timer emulation in vcpu entry/exit
KVM: arm/arm64: Move phys_timer_emulate function
KVM: arm/arm64: Use kvm_arm_timer_set/get_reg for guest register traps
...
This commit is contained in:
Linus Torvalds
@@ -1124,10 +1124,14 @@ guest physical address space and must not conflict with any memory slot
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or any mmio address. The guest may malfunction if it accesses this memory
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region.
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Setting the address to 0 will result in resetting the address to its default
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(0xfffbc000).
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This ioctl is required on Intel-based hosts. This is needed on Intel hardware
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because of a quirk in the virtualization implementation (see the internals
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documentation when it pops into existence).
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Fails if any VCPU has already been created.
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4.41 KVM_SET_BOOT_CPU_ID
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@@ -4347,3 +4351,12 @@ This capability indicates that userspace can load HV_X64_MSR_VP_INDEX msr. Its
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value is used to denote the target vcpu for a SynIC interrupt. For
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compatibilty, KVM initializes this msr to KVM's internal vcpu index. When this
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capability is absent, userspace can still query this msr's value.
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8.13 KVM_CAP_S390_AIS_MIGRATION
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Architectures: s390
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Parameters: none
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This capability indicates if the flic device will be able to get/set the
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AIS states for migration via the KVM_DEV_FLIC_AISM_ALL attribute and allows
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to discover this without having to create a flic device.
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@@ -33,6 +33,10 @@ Groups:
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request the initialization of the ITS, no additional parameter in
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kvm_device_attr.addr.
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KVM_DEV_ARM_ITS_CTRL_RESET
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reset the ITS, no additional parameter in kvm_device_attr.addr.
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See "ITS Reset State" section.
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KVM_DEV_ARM_ITS_SAVE_TABLES
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save the ITS table data into guest RAM, at the location provisioned
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by the guest in corresponding registers/table entries.
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@@ -157,3 +161,19 @@ Then vcpus can be started.
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- pINTID is the physical LPI ID; if zero, it means the entry is not valid
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and other fields are not meaningful.
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- ICID is the collection ID
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ITS Reset State:
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----------------
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RESET returns the ITS to the same state that it was when first created and
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initialized. When the RESET command returns, the following things are
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guaranteed:
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- The ITS is not enabled and quiescent
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GITS_CTLR.Enabled = 0 .Quiescent=1
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- There is no internally cached state
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- No collection or device table are used
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GITS_BASER<n>.Valid = 0
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- GITS_CBASER = 0, GITS_CREADR = 0, GITS_CWRITER = 0
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- The ABI version is unchanged and remains the one set when the ITS
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device was first created.
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@@ -151,8 +151,13 @@ struct kvm_s390_ais_all {
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to an ISC (MSB0 bit 0 to ISC 0 and so on). The combination of simm bit and
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nimm bit presents AIS mode for a ISC.
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KVM_DEV_FLIC_AISM_ALL is indicated by KVM_CAP_S390_AIS_MIGRATION.
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Note: The KVM_SET_DEVICE_ATTR/KVM_GET_DEVICE_ATTR device ioctls executed on
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FLIC with an unknown group or attribute gives the error code EINVAL (instead of
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ENXIO, as specified in the API documentation). It is not possible to conclude
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that a FLIC operation is unavailable based on the error code resulting from a
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usage attempt.
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Note: The KVM_DEV_FLIC_CLEAR_IO_IRQ ioctl will return EINVAL in case a zero
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schid is specified.
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@@ -68,6 +68,8 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
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extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
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extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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extern void __init_stage2_translation(void);
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@@ -25,7 +25,22 @@
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#include <asm/kvm_arm.h>
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#include <asm/cputype.h>
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/* arm64 compatibility macros */
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#define COMPAT_PSR_MODE_ABT ABT_MODE
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#define COMPAT_PSR_MODE_UND UND_MODE
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#define COMPAT_PSR_T_BIT PSR_T_BIT
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#define COMPAT_PSR_I_BIT PSR_I_BIT
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#define COMPAT_PSR_A_BIT PSR_A_BIT
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#define COMPAT_PSR_E_BIT PSR_E_BIT
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#define COMPAT_PSR_IT_MASK PSR_IT_MASK
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
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static inline unsigned long *vcpu_reg32(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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return vcpu_reg(vcpu, reg_num);
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}
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
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static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
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@@ -42,10 +57,25 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_undef32(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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static inline void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undef32(vcpu);
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}
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static inline void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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kvm_inject_dabt32(vcpu, addr);
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}
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static inline void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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kvm_inject_pabt32(vcpu, addr);
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}
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static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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@@ -203,7 +233,7 @@ static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
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static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
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{
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switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
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switch (kvm_vcpu_trap_get_fault(vcpu)) {
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case FSC_SEA:
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case FSC_SEA_TTW0:
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case FSC_SEA_TTW1:
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@@ -98,8 +98,8 @@
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#define cntvoff_el2 CNTVOFF
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#define cnthctl_el2 CNTHCTL
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void __timer_save_state(struct kvm_vcpu *vcpu);
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void __timer_restore_state(struct kvm_vcpu *vcpu);
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void __timer_enable_traps(struct kvm_vcpu *vcpu);
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void __timer_disable_traps(struct kvm_vcpu *vcpu);
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void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
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@@ -152,6 +152,12 @@ struct kvm_arch_memory_slot {
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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/* PL1 Physical Timer Registers */
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#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
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#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
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#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
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/* Virtual Timer Registers */
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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@@ -216,6 +222,7 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_ITS_CTRL_RESET 4
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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@@ -165,143 +165,6 @@ unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
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* Inject exceptions into the guest
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*/
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static u32 exc_vector_base(struct kvm_vcpu *vcpu)
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{
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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u32 vbar = vcpu_cp15(vcpu, c12_VBAR);
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if (sctlr & SCTLR_V)
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return 0xffff0000;
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else /* always have security exceptions */
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return vbar;
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}
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/*
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* Switch to an exception mode, updating both CPSR and SPSR. Follow
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* the logic described in AArch32.EnterMode() from the ARMv8 ARM.
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*/
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static void kvm_update_psr(struct kvm_vcpu *vcpu, unsigned long mode)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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*vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | mode;
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switch (mode) {
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case FIQ_MODE:
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*vcpu_cpsr(vcpu) |= PSR_F_BIT;
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/* Fall through */
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case ABT_MODE:
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case IRQ_MODE:
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*vcpu_cpsr(vcpu) |= PSR_A_BIT;
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/* Fall through */
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default:
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*vcpu_cpsr(vcpu) |= PSR_I_BIT;
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}
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*vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
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if (sctlr & SCTLR_TE)
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*vcpu_cpsr(vcpu) |= PSR_T_BIT;
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if (sctlr & SCTLR_EE)
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*vcpu_cpsr(vcpu) |= PSR_E_BIT;
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/* Note: These now point to the mode banked copies */
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*vcpu_spsr(vcpu) = cpsr;
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}
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/**
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* kvm_inject_undefined - inject an undefined exception into the guest
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* @vcpu: The VCPU to receive the undefined exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Modelled after TakeUndefInstrException() pseudocode.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_thumb = (cpsr & PSR_T_BIT);
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u32 vect_offset = 4;
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u32 return_offset = (is_thumb) ? 2 : 4;
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kvm_update_psr(vcpu, UND_MODE);
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*vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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}
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/*
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* Modelled after TakeDataAbortException() and TakePrefetchAbortException
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* pseudocode.
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*/
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static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
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{
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u32 vect_offset;
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u32 return_offset = (is_pabt) ? 4 : 8;
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bool is_lpae;
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kvm_update_psr(vcpu, ABT_MODE);
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*vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
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if (is_pabt)
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vect_offset = 12;
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else
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vect_offset = 16;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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if (is_pabt) {
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/* Set IFAR and IFSR */
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vcpu_cp15(vcpu, c6_IFAR) = addr;
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is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
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/* Always give debug fault for now - should give guest a clue */
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if (is_lpae)
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vcpu_cp15(vcpu, c5_IFSR) = 1 << 9 | 0x22;
|
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else
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vcpu_cp15(vcpu, c5_IFSR) = 2;
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} else { /* !iabt */
|
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/* Set DFAR and DFSR */
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vcpu_cp15(vcpu, c6_DFAR) = addr;
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is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
|
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/* Always give debug fault for now - should give guest a clue */
|
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if (is_lpae)
|
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vcpu_cp15(vcpu, c5_DFSR) = 1 << 9 | 0x22;
|
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else
|
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vcpu_cp15(vcpu, c5_DFSR) = 2;
|
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}
|
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|
||||
}
|
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|
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/**
|
||||
* kvm_inject_dabt - inject a data abort into the guest
|
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* @vcpu: The VCPU to receive the undefined exception
|
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* @addr: The address to report in the DFAR
|
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*
|
||||
* It is assumed that this code is called from the VCPU thread and that the
|
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* VCPU therefore is not currently executing guest code.
|
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*/
|
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
{
|
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inject_abt(vcpu, false, addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_inject_pabt - inject a prefetch abort into the guest
|
||||
* @vcpu: The VCPU to receive the undefined exception
|
||||
* @addr: The address to report in the DFAR
|
||||
*
|
||||
* It is assumed that this code is called from the VCPU thread and that the
|
||||
* VCPU therefore is not currently executing guest code.
|
||||
*/
|
||||
void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
{
|
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inject_abt(vcpu, true, addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_inject_vabt - inject an async abort / SError into the guest
|
||||
* @vcpu: The VCPU to receive the exception
|
||||
|
||||
@@ -174,7 +174,7 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
__activate_vm(vcpu);
|
||||
|
||||
__vgic_restore_state(vcpu);
|
||||
__timer_restore_state(vcpu);
|
||||
__timer_enable_traps(vcpu);
|
||||
|
||||
__sysreg_restore_state(guest_ctxt);
|
||||
__banked_restore_state(guest_ctxt);
|
||||
@@ -191,7 +191,8 @@ again:
|
||||
|
||||
__banked_save_state(guest_ctxt);
|
||||
__sysreg_save_state(guest_ctxt);
|
||||
__timer_save_state(vcpu);
|
||||
__timer_disable_traps(vcpu);
|
||||
|
||||
__vgic_save_state(vcpu);
|
||||
|
||||
__deactivate_traps(vcpu);
|
||||
@@ -237,7 +238,7 @@ void __hyp_text __noreturn __hyp_panic(int cause)
|
||||
|
||||
vcpu = (struct kvm_vcpu *)read_sysreg(HTPIDR);
|
||||
host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
|
||||
__timer_save_state(vcpu);
|
||||
__timer_disable_traps(vcpu);
|
||||
__deactivate_traps(vcpu);
|
||||
__deactivate_vm(vcpu);
|
||||
__banked_restore_state(host_ctxt);
|
||||
|
||||
@@ -52,6 +52,7 @@ struct arch_timer_erratum_workaround {
|
||||
const char *desc;
|
||||
u32 (*read_cntp_tval_el0)(void);
|
||||
u32 (*read_cntv_tval_el0)(void);
|
||||
u64 (*read_cntpct_el0)(void);
|
||||
u64 (*read_cntvct_el0)(void);
|
||||
int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
|
||||
int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
|
||||
@@ -149,11 +150,8 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
|
||||
|
||||
static inline u64 arch_counter_get_cntpct(void)
|
||||
{
|
||||
/*
|
||||
* AArch64 kernel and user space mandate the use of CNTVCT.
|
||||
*/
|
||||
BUG();
|
||||
return 0;
|
||||
isb();
|
||||
return arch_timer_reg_read_stable(cntpct_el0);
|
||||
}
|
||||
|
||||
static inline u64 arch_counter_get_cntvct(void)
|
||||
|
||||
@@ -55,6 +55,8 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
|
||||
extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
|
||||
extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
|
||||
|
||||
extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
|
||||
|
||||
extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
|
||||
|
||||
extern u64 __vgic_v3_get_ich_vtr_el2(void);
|
||||
|
||||
@@ -41,6 +41,9 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu);
|
||||
void kvm_inject_vabt(struct kvm_vcpu *vcpu);
|
||||
void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
|
||||
void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
|
||||
void kvm_inject_undef32(struct kvm_vcpu *vcpu);
|
||||
void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
|
||||
void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
|
||||
|
||||
static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
@@ -237,7 +240,7 @@ static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
|
||||
|
||||
static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
|
||||
{
|
||||
switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
|
||||
switch (kvm_vcpu_trap_get_fault(vcpu)) {
|
||||
case FSC_SEA:
|
||||
case FSC_SEA_TTW0:
|
||||
case FSC_SEA_TTW1:
|
||||
|
||||
@@ -129,8 +129,8 @@ void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
|
||||
void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
|
||||
int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu);
|
||||
|
||||
void __timer_save_state(struct kvm_vcpu *vcpu);
|
||||
void __timer_restore_state(struct kvm_vcpu *vcpu);
|
||||
void __timer_enable_traps(struct kvm_vcpu *vcpu);
|
||||
void __timer_disable_traps(struct kvm_vcpu *vcpu);
|
||||
|
||||
void __sysreg_save_host_state(struct kvm_cpu_context *ctxt);
|
||||
void __sysreg_restore_host_state(struct kvm_cpu_context *ctxt);
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
* Use the current timer as a cycle counter since this is what we use for
|
||||
* the delay loop.
|
||||
*/
|
||||
#define get_cycles() arch_counter_get_cntvct()
|
||||
#define get_cycles() arch_timer_read_counter()
|
||||
|
||||
#include <asm-generic/timex.h>
|
||||
|
||||
|
||||
@@ -196,6 +196,12 @@ struct kvm_arch_memory_slot {
|
||||
|
||||
#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
|
||||
|
||||
/* Physical Timer EL0 Registers */
|
||||
#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
|
||||
#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
|
||||
#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
|
||||
|
||||
/* EL0 Virtual Timer Registers */
|
||||
#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
|
||||
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
|
||||
@@ -228,6 +234,7 @@ struct kvm_arch_memory_slot {
|
||||
#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
|
||||
#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
|
||||
#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
|
||||
#define KVM_DEV_ARM_ITS_CTRL_RESET 4
|
||||
|
||||
/* Device Control API on vcpu fd */
|
||||
#define KVM_ARM_VCPU_PMU_V3_CTRL 0
|
||||
|
||||
@@ -304,7 +304,7 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
|
||||
__activate_vm(vcpu);
|
||||
|
||||
__vgic_restore_state(vcpu);
|
||||
__timer_restore_state(vcpu);
|
||||
__timer_enable_traps(vcpu);
|
||||
|
||||
/*
|
||||
* We must restore the 32-bit state before the sysregs, thanks
|
||||
@@ -374,7 +374,7 @@ again:
|
||||
|
||||
__sysreg_save_guest_state(guest_ctxt);
|
||||
__sysreg32_save_state(vcpu);
|
||||
__timer_save_state(vcpu);
|
||||
__timer_disable_traps(vcpu);
|
||||
__vgic_save_state(vcpu);
|
||||
|
||||
__deactivate_traps(vcpu);
|
||||
@@ -442,7 +442,7 @@ void __hyp_text __noreturn __hyp_panic(void)
|
||||
|
||||
vcpu = (struct kvm_vcpu *)read_sysreg(tpidr_el2);
|
||||
host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
|
||||
__timer_save_state(vcpu);
|
||||
__timer_disable_traps(vcpu);
|
||||
__deactivate_traps(vcpu);
|
||||
__deactivate_vm(vcpu);
|
||||
__sysreg_restore_host_state(host_ctxt);
|
||||
|
||||
@@ -33,88 +33,6 @@
|
||||
#define LOWER_EL_AArch64_VECTOR 0x400
|
||||
#define LOWER_EL_AArch32_VECTOR 0x600
|
||||
|
||||
/*
|
||||
* Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
|
||||
*/
|
||||
static const u8 return_offsets[8][2] = {
|
||||
[0] = { 0, 0 }, /* Reset, unused */
|
||||
[1] = { 4, 2 }, /* Undefined */
|
||||
[2] = { 0, 0 }, /* SVC, unused */
|
||||
[3] = { 4, 4 }, /* Prefetch abort */
|
||||
[4] = { 8, 8 }, /* Data abort */
|
||||
[5] = { 0, 0 }, /* HVC, unused */
|
||||
[6] = { 4, 4 }, /* IRQ, unused */
|
||||
[7] = { 4, 4 }, /* FIQ, unused */
|
||||
};
|
||||
|
||||
static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
|
||||
{
|
||||
unsigned long cpsr;
|
||||
unsigned long new_spsr_value = *vcpu_cpsr(vcpu);
|
||||
bool is_thumb = (new_spsr_value & COMPAT_PSR_T_BIT);
|
||||
u32 return_offset = return_offsets[vect_offset >> 2][is_thumb];
|
||||
u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
|
||||
|
||||
cpsr = mode | COMPAT_PSR_I_BIT;
|
||||
|
||||
if (sctlr & (1 << 30))
|
||||
cpsr |= COMPAT_PSR_T_BIT;
|
||||
if (sctlr & (1 << 25))
|
||||
cpsr |= COMPAT_PSR_E_BIT;
|
||||
|
||||
*vcpu_cpsr(vcpu) = cpsr;
|
||||
|
||||
/* Note: These now point to the banked copies */
|
||||
*vcpu_spsr(vcpu) = new_spsr_value;
|
||||
*vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
|
||||
|
||||
/* Branch to exception vector */
|
||||
if (sctlr & (1 << 13))
|
||||
vect_offset += 0xffff0000;
|
||||
else /* always have security exceptions */
|
||||
vect_offset += vcpu_cp15(vcpu, c12_VBAR);
|
||||
|
||||
*vcpu_pc(vcpu) = vect_offset;
|
||||
}
|
||||
|
||||
static void inject_undef32(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
prepare_fault32(vcpu, COMPAT_PSR_MODE_UND, 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Modelled after TakeDataAbortException() and TakePrefetchAbortException
|
||||
* pseudocode.
|
||||
*/
|
||||
static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
|
||||
unsigned long addr)
|
||||
{
|
||||
u32 vect_offset;
|
||||
u32 *far, *fsr;
|
||||
bool is_lpae;
|
||||
|
||||
if (is_pabt) {
|
||||
vect_offset = 12;
|
||||
far = &vcpu_cp15(vcpu, c6_IFAR);
|
||||
fsr = &vcpu_cp15(vcpu, c5_IFSR);
|
||||
} else { /* !iabt */
|
||||
vect_offset = 16;
|
||||
far = &vcpu_cp15(vcpu, c6_DFAR);
|
||||
fsr = &vcpu_cp15(vcpu, c5_DFSR);
|
||||
}
|
||||
|
||||
prepare_fault32(vcpu, COMPAT_PSR_MODE_ABT | COMPAT_PSR_A_BIT, vect_offset);
|
||||
|
||||
*far = addr;
|
||||
|
||||
/* Give the guest an IMPLEMENTATION DEFINED exception */
|
||||
is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
|
||||
if (is_lpae)
|
||||
*fsr = 1 << 9 | 0x34;
|
||||
else
|
||||
*fsr = 0x14;
|
||||
}
|
||||
|
||||
enum exception_type {
|
||||
except_type_sync = 0,
|
||||
except_type_irq = 0x80,
|
||||
@@ -211,7 +129,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
|
||||
void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
{
|
||||
if (!(vcpu->arch.hcr_el2 & HCR_RW))
|
||||
inject_abt32(vcpu, false, addr);
|
||||
kvm_inject_dabt32(vcpu, addr);
|
||||
else
|
||||
inject_abt64(vcpu, false, addr);
|
||||
}
|
||||
@@ -227,7 +145,7 @@ void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
{
|
||||
if (!(vcpu->arch.hcr_el2 & HCR_RW))
|
||||
inject_abt32(vcpu, true, addr);
|
||||
kvm_inject_pabt32(vcpu, addr);
|
||||
else
|
||||
inject_abt64(vcpu, true, addr);
|
||||
}
|
||||
@@ -241,7 +159,7 @@ void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
|
||||
void kvm_inject_undefined(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (!(vcpu->arch.hcr_el2 & HCR_RW))
|
||||
inject_undef32(vcpu);
|
||||
kvm_inject_undef32(vcpu);
|
||||
else
|
||||
inject_undef64(vcpu);
|
||||
}
|
||||
|
||||
+14
-27
@@ -842,13 +842,16 @@ static bool access_cntp_tval(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *p,
|
||||
const struct sys_reg_desc *r)
|
||||
{
|
||||
struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
|
||||
u64 now = kvm_phys_timer_read();
|
||||
u64 cval;
|
||||
|
||||
if (p->is_write)
|
||||
ptimer->cnt_cval = p->regval + now;
|
||||
else
|
||||
p->regval = ptimer->cnt_cval - now;
|
||||
if (p->is_write) {
|
||||
kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL,
|
||||
p->regval + now);
|
||||
} else {
|
||||
cval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
|
||||
p->regval = cval - now;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -857,24 +860,10 @@ static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *p,
|
||||
const struct sys_reg_desc *r)
|
||||
{
|
||||
struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
|
||||
|
||||
if (p->is_write) {
|
||||
/* ISTATUS bit is read-only */
|
||||
ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
|
||||
} else {
|
||||
u64 now = kvm_phys_timer_read();
|
||||
|
||||
p->regval = ptimer->cnt_ctl;
|
||||
/*
|
||||
* Set ISTATUS bit if it's expired.
|
||||
* Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
|
||||
* UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
|
||||
* regardless of ENABLE bit for our implementation convenience.
|
||||
*/
|
||||
if (ptimer->cnt_cval <= now)
|
||||
p->regval |= ARCH_TIMER_CTRL_IT_STAT;
|
||||
}
|
||||
if (p->is_write)
|
||||
kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, p->regval);
|
||||
else
|
||||
p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL);
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -883,12 +872,10 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,
|
||||
struct sys_reg_params *p,
|
||||
const struct sys_reg_desc *r)
|
||||
{
|
||||
struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
|
||||
|
||||
if (p->is_write)
|
||||
ptimer->cnt_cval = p->regval;
|
||||
kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, p->regval);
|
||||
else
|
||||
p->regval = ptimer->cnt_cval;
|
||||
p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -216,7 +216,8 @@ extern kvm_pfn_t kvmppc_gpa_to_pfn(struct kvm_vcpu *vcpu, gpa_t gpa,
|
||||
bool writing, bool *writable);
|
||||
extern void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
|
||||
unsigned long *rmap, long pte_index, int realmode);
|
||||
extern void kvmppc_update_rmap_change(unsigned long *rmap, unsigned long psize);
|
||||
extern void kvmppc_update_dirty_map(struct kvm_memory_slot *memslot,
|
||||
unsigned long gfn, unsigned long psize);
|
||||
extern void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep,
|
||||
unsigned long pte_index);
|
||||
void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep,
|
||||
|
||||
@@ -20,6 +20,8 @@
|
||||
#ifndef __ASM_KVM_BOOK3S_64_H__
|
||||
#define __ASM_KVM_BOOK3S_64_H__
|
||||
|
||||
#include <linux/string.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/book3s/64/mmu-hash.h>
|
||||
|
||||
/* Power architecture requires HPT is at least 256kiB, at most 64TiB */
|
||||
@@ -107,18 +109,96 @@ static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
|
||||
hpte[0] = cpu_to_be64(hpte_v);
|
||||
}
|
||||
|
||||
/*
|
||||
* These functions encode knowledge of the POWER7/8/9 hardware
|
||||
* interpretations of the HPTE LP (large page size) field.
|
||||
*/
|
||||
static inline int kvmppc_hpte_page_shifts(unsigned long h, unsigned long l)
|
||||
{
|
||||
unsigned int lphi;
|
||||
|
||||
if (!(h & HPTE_V_LARGE))
|
||||
return 12; /* 4kB */
|
||||
lphi = (l >> 16) & 0xf;
|
||||
switch ((l >> 12) & 0xf) {
|
||||
case 0:
|
||||
return !lphi ? 24 : -1; /* 16MB */
|
||||
break;
|
||||
case 1:
|
||||
return 16; /* 64kB */
|
||||
break;
|
||||
case 3:
|
||||
return !lphi ? 34 : -1; /* 16GB */
|
||||
break;
|
||||
case 7:
|
||||
return (16 << 8) + 12; /* 64kB in 4kB */
|
||||
break;
|
||||
case 8:
|
||||
if (!lphi)
|
||||
return (24 << 8) + 16; /* 16MB in 64kkB */
|
||||
if (lphi == 3)
|
||||
return (24 << 8) + 12; /* 16MB in 4kB */
|
||||
break;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int kvmppc_hpte_base_page_shift(unsigned long h, unsigned long l)
|
||||
{
|
||||
return kvmppc_hpte_page_shifts(h, l) & 0xff;
|
||||
}
|
||||
|
||||
static inline int kvmppc_hpte_actual_page_shift(unsigned long h, unsigned long l)
|
||||
{
|
||||
int tmp = kvmppc_hpte_page_shifts(h, l);
|
||||
|
||||
if (tmp >= 0x100)
|
||||
tmp >>= 8;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r)
|
||||
{
|
||||
return 1ul << kvmppc_hpte_actual_page_shift(v, r);
|
||||
}
|
||||
|
||||
static inline int kvmppc_pgsize_lp_encoding(int base_shift, int actual_shift)
|
||||
{
|
||||
switch (base_shift) {
|
||||
case 12:
|
||||
switch (actual_shift) {
|
||||
case 12:
|
||||
return 0;
|
||||
case 16:
|
||||
return 7;
|
||||
case 24:
|
||||
return 0x38;
|
||||
}
|
||||
break;
|
||||
case 16:
|
||||
switch (actual_shift) {
|
||||
case 16:
|
||||
return 1;
|
||||
case 24:
|
||||
return 8;
|
||||
}
|
||||
break;
|
||||
case 24:
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
|
||||
unsigned long pte_index)
|
||||
{
|
||||
int i, b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
|
||||
unsigned int penc;
|
||||
int a_pgshift, b_pgshift;
|
||||
unsigned long rb = 0, va_low, sllp;
|
||||
unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
|
||||
|
||||
if (v & HPTE_V_LARGE) {
|
||||
i = hpte_page_sizes[lp];
|
||||
b_psize = i & 0xf;
|
||||
a_psize = i >> 4;
|
||||
b_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r);
|
||||
if (a_pgshift >= 0x100) {
|
||||
b_pgshift &= 0xff;
|
||||
a_pgshift >>= 8;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -152,37 +232,33 @@ static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
|
||||
va_low ^= v >> (SID_SHIFT_1T - 16);
|
||||
va_low &= 0x7ff;
|
||||
|
||||
switch (b_psize) {
|
||||
case MMU_PAGE_4K:
|
||||
sllp = get_sllp_encoding(a_psize);
|
||||
rb |= sllp << 5; /* AP field */
|
||||
if (b_pgshift == 12) {
|
||||
if (a_pgshift > 12) {
|
||||
sllp = (a_pgshift == 16) ? 5 : 4;
|
||||
rb |= sllp << 5; /* AP field */
|
||||
}
|
||||
rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
|
||||
break;
|
||||
default:
|
||||
{
|
||||
} else {
|
||||
int aval_shift;
|
||||
/*
|
||||
* remaining bits of AVA/LP fields
|
||||
* Also contain the rr bits of LP
|
||||
*/
|
||||
rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
|
||||
rb |= (va_low << b_pgshift) & 0x7ff000;
|
||||
/*
|
||||
* Now clear not needed LP bits based on actual psize
|
||||
*/
|
||||
rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
|
||||
rb &= ~((1ul << a_pgshift) - 1);
|
||||
/*
|
||||
* AVAL field 58..77 - base_page_shift bits of va
|
||||
* we have space for 58..64 bits, Missing bits should
|
||||
* be zero filled. +1 is to take care of L bit shift
|
||||
*/
|
||||
aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
|
||||
aval_shift = 64 - (77 - b_pgshift) + 1;
|
||||
rb |= ((va_low << aval_shift) & 0xfe);
|
||||
|
||||
rb |= 1; /* L field */
|
||||
penc = mmu_psize_defs[b_psize].penc[a_psize];
|
||||
rb |= penc << 12; /* LP field */
|
||||
break;
|
||||
}
|
||||
rb |= r & 0xff000 & ((1ul << a_pgshift) - 1); /* LP field */
|
||||
}
|
||||
rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
|
||||
return rb;
|
||||
@@ -370,6 +446,28 @@ static inline unsigned long kvmppc_hpt_mask(struct kvm_hpt_info *hpt)
|
||||
return (1UL << (hpt->order - 7)) - 1;
|
||||
}
|
||||
|
||||
/* Set bits in a dirty bitmap, which is in LE format */
|
||||
static inline void set_dirty_bits(unsigned long *map, unsigned long i,
|
||||
unsigned long npages)
|
||||
{
|
||||
|
||||
if (npages >= 8)
|
||||
memset((char *)map + i / 8, 0xff, npages / 8);
|
||||
else
|
||||
for (; npages; ++i, --npages)
|
||||
__set_bit_le(i, map);
|
||||
}
|
||||
|
||||
static inline void set_dirty_bits_atomic(unsigned long *map, unsigned long i,
|
||||
unsigned long npages)
|
||||
{
|
||||
if (npages >= 8)
|
||||
memset((char *)map + i / 8, 0xff, npages / 8);
|
||||
else
|
||||
for (; npages; ++i, --npages)
|
||||
set_bit_le(i, map);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
|
||||
|
||||
#endif /* __ASM_KVM_BOOK3S_64_H__ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user