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[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Martin Schwidefsky
@@ -13,7 +13,6 @@
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#ifndef __ASM_S390_PROCESSOR_H
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#define __ASM_S390_PROCESSOR_H
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#ifdef __KERNEL__
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@@ -21,7 +20,7 @@
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; __asm__("basr %0,0":"=a"(pc)); pc; })
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#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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@@ -202,7 +201,7 @@ unsigned long get_wchan(struct task_struct *p);
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static inline void cpu_relax(void)
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{
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if (MACHINE_HAS_DIAG44)
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asm volatile ("diag 0,0,68" : : : "memory");
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asm volatile("diag 0,0,68" : : : "memory");
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else
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barrier();
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}
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@@ -213,9 +212,9 @@ static inline void cpu_relax(void)
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static inline void __load_psw(psw_t psw)
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{
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#ifndef __s390x__
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asm volatile ("lpsw 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
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asm volatile("lpsw 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
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#else
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asm volatile ("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
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asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
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#endif
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}
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@@ -232,20 +231,20 @@ static inline void __load_psw_mask (unsigned long mask)
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psw.mask = mask;
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#ifndef __s390x__
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asm volatile (
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" basr %0,0\n"
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"0: ahi %0,1f-0b\n"
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" st %0,4(%1)\n"
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" lpsw 0(%1)\n"
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asm volatile(
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" basr %0,0\n"
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"0: ahi %0,1f-0b\n"
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" st %0,4(%1)\n"
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" lpsw 0(%1)\n"
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"1:"
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: "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc" );
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: "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
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#else /* __s390x__ */
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asm volatile (
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" larl %0,1f\n"
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" stg %0,8(%1)\n"
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" lpswe 0(%1)\n"
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asm volatile(
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" larl %0,1f\n"
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" stg %0,8(%1)\n"
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" lpswe 0(%1)\n"
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"1:"
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: "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc" );
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: "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
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#endif /* __s390x__ */
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}
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@@ -274,56 +273,57 @@ static inline void disabled_wait(unsigned long code)
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* the processor is dead afterwards
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*/
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#ifndef __s390x__
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asm volatile (" stctl 0,0,0(%2)\n"
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" ni 0(%2),0xef\n" /* switch off protection */
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" lctl 0,0,0(%2)\n"
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" stpt 0xd8\n" /* store timer */
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" stckc 0xe0\n" /* store clock comparator */
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" stpx 0x108\n" /* store prefix register */
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" stam 0,15,0x120\n" /* store access registers */
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" std 0,0x160\n" /* store f0 */
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" std 2,0x168\n" /* store f2 */
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" std 4,0x170\n" /* store f4 */
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" std 6,0x178\n" /* store f6 */
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" stm 0,15,0x180\n" /* store general registers */
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" stctl 0,15,0x1c0\n" /* store control registers */
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" oi 0x1c0,0x10\n" /* fake protection bit */
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" lpsw 0(%1)"
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: "=m" (ctl_buf)
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: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc" );
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asm volatile(
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" stctl 0,0,0(%2)\n"
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" ni 0(%2),0xef\n" /* switch off protection */
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" lctl 0,0,0(%2)\n"
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" stpt 0xd8\n" /* store timer */
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" stckc 0xe0\n" /* store clock comparator */
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" stpx 0x108\n" /* store prefix register */
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" stam 0,15,0x120\n" /* store access registers */
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" std 0,0x160\n" /* store f0 */
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" std 2,0x168\n" /* store f2 */
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" std 4,0x170\n" /* store f4 */
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" std 6,0x178\n" /* store f6 */
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" stm 0,15,0x180\n" /* store general registers */
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" stctl 0,15,0x1c0\n" /* store control registers */
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" oi 0x1c0,0x10\n" /* fake protection bit */
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" lpsw 0(%1)"
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: "=m" (ctl_buf)
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: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
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#else /* __s390x__ */
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asm volatile (" stctg 0,0,0(%2)\n"
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" ni 4(%2),0xef\n" /* switch off protection */
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" lctlg 0,0,0(%2)\n"
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" lghi 1,0x1000\n"
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" stpt 0x328(1)\n" /* store timer */
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" stckc 0x330(1)\n" /* store clock comparator */
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" stpx 0x318(1)\n" /* store prefix register */
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" stam 0,15,0x340(1)\n" /* store access registers */
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" stfpc 0x31c(1)\n" /* store fpu control */
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" std 0,0x200(1)\n" /* store f0 */
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" std 1,0x208(1)\n" /* store f1 */
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" std 2,0x210(1)\n" /* store f2 */
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" std 3,0x218(1)\n" /* store f3 */
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" std 4,0x220(1)\n" /* store f4 */
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" std 5,0x228(1)\n" /* store f5 */
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" std 6,0x230(1)\n" /* store f6 */
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" std 7,0x238(1)\n" /* store f7 */
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" std 8,0x240(1)\n" /* store f8 */
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" std 9,0x248(1)\n" /* store f9 */
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" std 10,0x250(1)\n" /* store f10 */
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" std 11,0x258(1)\n" /* store f11 */
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" std 12,0x260(1)\n" /* store f12 */
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" std 13,0x268(1)\n" /* store f13 */
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" std 14,0x270(1)\n" /* store f14 */
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" std 15,0x278(1)\n" /* store f15 */
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" stmg 0,15,0x280(1)\n" /* store general registers */
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" stctg 0,15,0x380(1)\n" /* store control registers */
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" oi 0x384(1),0x10\n" /* fake protection bit */
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" lpswe 0(%1)"
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: "=m" (ctl_buf)
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: "a" (&dw_psw), "a" (&ctl_buf),
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"m" (dw_psw) : "cc", "0", "1");
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asm volatile(
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" stctg 0,0,0(%2)\n"
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" ni 4(%2),0xef\n" /* switch off protection */
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" lctlg 0,0,0(%2)\n"
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" lghi 1,0x1000\n"
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" stpt 0x328(1)\n" /* store timer */
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" stckc 0x330(1)\n" /* store clock comparator */
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" stpx 0x318(1)\n" /* store prefix register */
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" stam 0,15,0x340(1)\n"/* store access registers */
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" stfpc 0x31c(1)\n" /* store fpu control */
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" std 0,0x200(1)\n" /* store f0 */
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" std 1,0x208(1)\n" /* store f1 */
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" std 2,0x210(1)\n" /* store f2 */
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" std 3,0x218(1)\n" /* store f3 */
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" std 4,0x220(1)\n" /* store f4 */
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" std 5,0x228(1)\n" /* store f5 */
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" std 6,0x230(1)\n" /* store f6 */
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" std 7,0x238(1)\n" /* store f7 */
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" std 8,0x240(1)\n" /* store f8 */
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" std 9,0x248(1)\n" /* store f9 */
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" std 10,0x250(1)\n" /* store f10 */
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" std 11,0x258(1)\n" /* store f11 */
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" std 12,0x260(1)\n" /* store f12 */
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" std 13,0x268(1)\n" /* store f13 */
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" std 14,0x270(1)\n" /* store f14 */
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" std 15,0x278(1)\n" /* store f15 */
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" stmg 0,15,0x280(1)\n"/* store general registers */
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" stctg 0,15,0x380(1)\n"/* store control registers */
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" oi 0x384(1),0x10\n"/* fake protection bit */
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" lpswe 0(%1)"
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: "=m" (ctl_buf)
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: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0");
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#endif /* __s390x__ */
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}
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