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Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge the 4.8 pull request state from Dave - conflicts were getting out of hand, and Chris has some patches which outright don't apply without everything merged together again. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter
@@ -21,6 +21,7 @@ Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
|
||||
Andrew Morton <akpm@linux-foundation.org>
|
||||
Andrew Vasquez <andrew.vasquez@qlogic.com>
|
||||
Andy Adamson <andros@citi.umich.edu>
|
||||
Antoine Tenart <antoine.tenart@free-electrons.com>
|
||||
Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
|
||||
Archit Taneja <archit@ti.com>
|
||||
Arnaud Patard <arnaud.patard@rtp-net.org>
|
||||
@@ -30,6 +31,9 @@ Axel Lin <axel.lin@gmail.com>
|
||||
Ben Gardner <bgardner@wabtec.com>
|
||||
Ben M Cahill <ben.m.cahill@intel.com>
|
||||
Björn Steinbrink <B.Steinbrink@gmx.de>
|
||||
Boris Brezillon <boris.brezillon@free-electrons.com>
|
||||
Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon.dev@gmail.com>
|
||||
Boris Brezillon <boris.brezillon@free-electrons.com> <b.brezillon@overkiz.com>
|
||||
Brian Avery <b.avery@hp.com>
|
||||
Brian King <brking@us.ibm.com>
|
||||
Christoph Hellwig <hch@lst.de>
|
||||
@@ -89,6 +93,7 @@ Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
Linas Vepstas <linas@austin.ibm.com>
|
||||
Mark Brown <broonie@sirena.org.uk>
|
||||
Matthieu CASTET <castet.matthieu@free.fr>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com> <mchehab@infradead.org> <mchehab@redhat.com> <m.chehab@samsung.com> <mchehab@osg.samsung.com> <mchehab@s-opensource.com>
|
||||
Mayuresh Janorkar <mayur@ti.com>
|
||||
Michael Buesch <m@bues.ch>
|
||||
Michel Dänzer <michel@tungstengraphics.com>
|
||||
@@ -122,6 +127,7 @@ Santosh Shilimkar <santosh.shilimkar@oracle.org>
|
||||
Sascha Hauer <s.hauer@pengutronix.de>
|
||||
S.Çağlar Onur <caglar@pardus.org.tr>
|
||||
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com> <shuah.khan@hp.com> <shuahkh@osg.samsung.com> <shuah.kh@samsung.com>
|
||||
Simon Kelley <simon@thekelleys.org.uk>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <shemminger@osdl.org>
|
||||
|
||||
@@ -649,6 +649,7 @@ D: Configure, Menuconfig, xconfig
|
||||
|
||||
N: Mauro Carvalho Chehab
|
||||
E: m.chehab@samsung.org
|
||||
E: mchehab@osg.samsung.com
|
||||
E: mchehab@infradead.org
|
||||
D: Media subsystem (V4L/DVB) drivers and core
|
||||
D: EDAC drivers and EDAC 3.0 core rework
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: UVC function directory
|
||||
|
||||
streaming_maxburst - 0..15 (ss only)
|
||||
@@ -9,37 +9,37 @@ Description: UVC function directory
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Control descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class/ss
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Super speed control class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/class/fs
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||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Full speed control class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Output terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/output/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default output terminal descriptors
|
||||
|
||||
All attributes read only:
|
||||
@@ -53,12 +53,12 @@ Description: Default output terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/camera
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Camera terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/terminal/camera/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default camera terminal descriptors
|
||||
|
||||
All attributes read only:
|
||||
@@ -75,12 +75,12 @@ Description: Default camera terminal descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/processing
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Processing unit descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/processing/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default processing unit descriptors
|
||||
|
||||
All attributes read only:
|
||||
@@ -94,49 +94,49 @@ Description: Default processing unit descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/header
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Control header descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/control/header/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific control header descriptors
|
||||
|
||||
dwClockFrequency
|
||||
bcdUVC
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/ss
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Super speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/hs
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: High speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/class/fs
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Full speed streaming class descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/color_matching
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Color matching descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/color_matching/default
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Default color matching descriptors
|
||||
|
||||
All attributes read only:
|
||||
@@ -150,12 +150,12 @@ Description: Default color matching descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: MJPEG format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific MJPEG format descriptors
|
||||
|
||||
All attributes read only,
|
||||
@@ -174,7 +174,7 @@ Description: Specific MJPEG format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/mjpeg/name/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific MJPEG frame descriptors
|
||||
|
||||
dwFrameInterval - indicates how frame interval can be
|
||||
@@ -196,12 +196,12 @@ Description: Specific MJPEG frame descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Uncompressed format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific uncompressed format descriptors
|
||||
|
||||
bmaControls - this format's data for bmaControls in
|
||||
@@ -221,7 +221,7 @@ Description: Specific uncompressed format descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/uncompressed/name/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific uncompressed frame descriptors
|
||||
|
||||
dwFrameInterval - indicates how frame interval can be
|
||||
@@ -243,12 +243,12 @@ Description: Specific uncompressed frame descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Streaming header descriptors
|
||||
|
||||
What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header/name
|
||||
Date: Dec 2014
|
||||
KernelVersion: 3.20
|
||||
KernelVersion: 4.0
|
||||
Description: Specific streaming header descriptors
|
||||
|
||||
All attributes read only:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
What /sys/bus/iio/devices/iio:deviceX/in_proximity_raw
|
||||
What /sys/bus/iio/devices/iio:deviceX/in_proximity_input
|
||||
Date: March 2014
|
||||
KernelVersion: 3.15
|
||||
Contact: Matt Ranostay <mranostay@gmail.com>
|
||||
|
||||
@@ -1,13 +1,19 @@
|
||||
Analog Device ADV7511(W)/13 HDMI Encoders
|
||||
Analog Device ADV7511(W)/13/33 HDMI Encoders
|
||||
-----------------------------------------
|
||||
|
||||
The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters
|
||||
The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
|
||||
compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
|
||||
S/PDIF, CEC and HDCP.
|
||||
S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
|
||||
the others support RGB interface.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513"
|
||||
- compatible: Should be one of:
|
||||
"adi,adv7511"
|
||||
"adi,adv7511w"
|
||||
"adi,adv7513"
|
||||
"adi,adv7533"
|
||||
|
||||
- reg: I2C slave address
|
||||
|
||||
The ADV7511 supports a large number of input data formats that differ by their
|
||||
@@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and
|
||||
- adi,input-justification: The input bit justification ("left", "evenly",
|
||||
"right").
|
||||
|
||||
The following properties are required for ADV7533:
|
||||
|
||||
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
|
||||
be one of 1, 2, 3 or 4.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts: Specifier for the ADV7511 interrupt
|
||||
@@ -42,13 +53,18 @@ Optional properties:
|
||||
- adi,embedded-sync: The input uses synchronization signals embedded in the
|
||||
data stream (similar to BT.656). Defaults to separate H/V synchronization
|
||||
signals.
|
||||
- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
|
||||
generator. The chip will rely on the sync signals in the DSI data lanes,
|
||||
rather than generate its own timings for HDMI output.
|
||||
|
||||
Required nodes:
|
||||
|
||||
The ADV7511 has two video ports. Their connections are modelled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
- Video port 0 for the RGB or YUV input
|
||||
- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
|
||||
remote endpoint phandle should be a reference to a valid mipi_dsi_host device
|
||||
node.
|
||||
- Video port 1 for the HDMI output
|
||||
|
||||
|
||||
|
||||
@@ -5,6 +5,7 @@ Required properties for dp-controller:
|
||||
platform specific such as:
|
||||
* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
* "rockchip,rk3399-edp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
Toshiba TC358767 eDP bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "toshiba,tc358767"
|
||||
- reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
|
||||
- clock-names: should be "ref"
|
||||
- clocks: OF device-tree clock specification for refclk input. The reference
|
||||
clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
|
||||
|
||||
Optional properties:
|
||||
- shutdown-gpios: OF device-tree gpio specification for SD pin
|
||||
(active high shutdown input)
|
||||
- reset-gpios: OF device-tree gpio specification for RSTX pin
|
||||
(active low system reset)
|
||||
- ports: the ports node can contain video interface port nodes to connect
|
||||
to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
|
||||
- port@0: DSI input port
|
||||
- port@1: DPI input port
|
||||
- port@2: eDP/DP output port
|
||||
|
||||
[1]: Documentation/devicetree/bindings/graph.txt
|
||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
edp-bridge@68 {
|
||||
compatible = "toshiba,tc358767";
|
||||
reg = <0x68>;
|
||||
shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
|
||||
clock-names = "ref";
|
||||
clocks = <&edp_refclk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -12,7 +12,7 @@ Required properties:
|
||||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
- port Video port for the panel output
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
@@ -24,6 +24,11 @@ dcu: dcu@2ce0000 {
|
||||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
|
||||
port {
|
||||
dcu_out: endpoint {
|
||||
remote-endpoint = <&panel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -11,8 +11,7 @@ Required properties:
|
||||
be 0 or 1, since we have 2 DSI controllers at most for now.
|
||||
- interrupts: The interrupt signal from the DSI block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks.
|
||||
- clock-names: the following clocks are required:
|
||||
* "mdp_core_clk"
|
||||
* "iface_clk"
|
||||
@@ -23,16 +22,21 @@ Required properties:
|
||||
* "core_clk"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src_clk"
|
||||
- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
|
||||
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||
by a DSI PHY block. See [1] for details on clock bindings.
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- qcom,dsi-phy: phandle to DSI PHY device node
|
||||
- phys: phandle to DSI PHY device node
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||
an endpoint subnode as defined in [2] and [3].
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
See files in Documentation/devicetree/bindings/display/panel/ for each supported
|
||||
panel.
|
||||
See files in [4] for each supported panel.
|
||||
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||
driving a panel which needs 2 DSI links.
|
||||
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||
@@ -44,34 +48,38 @@ Optional properties:
|
||||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- port: DSI controller output port, containing one endpoint subnode.
|
||||
- ports: contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: set to phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
|
||||
to the physical lanes on the given platform. The value contained in
|
||||
index n describes what logical data lane is mapped to the physical data
|
||||
lane n (DATAn, where n lies between 0 and 3).
|
||||
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||
device graph info.
|
||||
|
||||
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||
to the logical lanes on the given platform. The value contained in
|
||||
index n describes what physical lane is mapped to the logical lane n
|
||||
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||
[3] for more info on the data-lanes property.
|
||||
|
||||
For example:
|
||||
|
||||
qcom,data-lane-map = <3 0 1 2>;
|
||||
data-lanes = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA3 is mapped to
|
||||
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
|
||||
to phys DATA2 and logic DATA2 to phys DATA3.
|
||||
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
|
||||
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
|
||||
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
|
||||
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
|
||||
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
|
||||
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
|
||||
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
|
||||
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
|
||||
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
|
||||
<0 1 2 3>
|
||||
<1 2 3 0>
|
||||
<2 3 0 1>
|
||||
<3 0 1 2>
|
||||
<0 3 2 1>
|
||||
<1 0 3 2>
|
||||
<2 1 0 3>
|
||||
<3 2 1 0>
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
@@ -86,11 +94,12 @@ Required properties:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
|
||||
be 0 or 1, since we have 2 DSI PHYs at most for now.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface_clk"
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
@@ -99,11 +108,16 @@ Optional properties:
|
||||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||
regulator is wanted.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
Example:
|
||||
mdss_dsi0: qcom,mdss_dsi@fd922800 {
|
||||
dsi0: dsi@fd922800 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
qcom,dsi-host-index = <0>;
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupt-parent = <&mdp>;
|
||||
interrupts = <4 0>;
|
||||
reg-names = "dsi_ctrl";
|
||||
reg = <0xfd922800 0x200>;
|
||||
@@ -124,19 +138,48 @@ Example:
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>;
|
||||
|
||||
assigned-clocks =
|
||||
<&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents =
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>;
|
||||
|
||||
vdda-supply = <&pma8084_l2>;
|
||||
vdd-supply = <&pma8084_l22>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0>;
|
||||
phys = <&dsi_phy0>;
|
||||
phy-names ="dsi-phy";
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
qcom,sync-dual-dsi;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mdss_dsi_active>;
|
||||
pinctrl-1 = <&mdss_dsi_suspend>;
|
||||
pinctrl-0 = <&dsi_active>;
|
||||
pinctrl-1 = <&dsi_suspend>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "sharp,lq101r1sx01";
|
||||
@@ -152,16 +195,9 @@ Example:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
@@ -173,6 +209,7 @@ Example:
|
||||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface_clk";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
|
||||
@@ -1,59 +0,0 @@
|
||||
Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
* "qcom,mdp5" - mdp5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
For MDP4:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mdp_clk"
|
||||
For MDP5:
|
||||
* "bus_clk"
|
||||
* "iface_clk"
|
||||
* "core_clk_src"
|
||||
* "core_clk"
|
||||
* "lut_clk" (some MDP5 versions may not need this)
|
||||
* "vsync_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
gpus = <&gpu>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"src_clk",
|
||||
"hdmi_clk",
|
||||
"mdp_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_SRC>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc TV_SRC>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,112 @@
|
||||
Qualcomm adreno/snapdragon MDP4 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the MDP4 display controller found in
|
||||
SoCs like MSM8960, APQ8064 and MSM8660.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "lut_clk"
|
||||
* "hdmi_clk"
|
||||
* "tv_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The output port mappings are:
|
||||
Port 0 -> LCDC/LVDS
|
||||
Port 1 -> DSI1 Cmd/Video
|
||||
Port 2 -> DSI2 Cmd/Video
|
||||
Port 3 -> DTV
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: hdmi@4a00000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&mdp_dtv_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
mdp: mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"hdmi_clk",
|
||||
"tv_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_CLK>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp_lvds_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
mdp_dsi2_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
mdp_dtv_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,160 @@
|
||||
Qualcomm adreno/snapdragon MDP5 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
|
||||
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss" - MDSS
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdss_phys"
|
||||
* "vbif_phys"
|
||||
- interrupts: The interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "vsync_clk"
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
MDP5:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp5" - MDP5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdp_phys"
|
||||
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
|
||||
- interrupt-parent: phandle to the MDSS block
|
||||
through MDP block
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
- * "bus_clk"
|
||||
- * "iface_clk"
|
||||
- * "core_clk"
|
||||
- * "vsync_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The availability of output ports can vary across SoC revisions:
|
||||
|
||||
For MSM8974 and APQ8084:
|
||||
Port 0 -> MDP_INTF0 (eDP)
|
||||
Port 1 -> MDP_INTF1 (DSI1)
|
||||
Port 2 -> MDP_INTF2 (DSI2)
|
||||
Port 3 -> MDP_INTF3 (HDMI)
|
||||
|
||||
For MSM8916:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
|
||||
For MSM8994 and MSM8996:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
Port 1 -> MDP_INTF2 (DSI2)
|
||||
Port 2 -> MDP_INTF3 (HDMI)
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdss: mdss@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"vsync_clk"
|
||||
|
||||
interrupts = <0 72 0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp: mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0 0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"core_clk",
|
||||
"vsync_clk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@1a98000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@1a98300 {
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp079qx1-sp0v"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
LG 9.7" (2048x1536 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp097qx1-spa1"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
Samsung 12.2" (2560x1600 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "samsung,lsn122dl01-c01"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq101k1ly04"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
Sharp 12.3" (2400x1600 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq123p1jx31"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
Starry 12.2" (1920x1200 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "starry,kr122ea0sra"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
|
||||
================================
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-edp";
|
||||
- compatible: "rockchip,rk3288-dp",
|
||||
"rockchip,rk3399-edp";
|
||||
|
||||
- reg: physical base address of the controller and length
|
||||
|
||||
@@ -27,6 +28,12 @@ Required properties:
|
||||
Port 0: contained 2 endpoints, connecting to the output of vop.
|
||||
Port 1: contained 1 endpoint, connecting to the input of panel.
|
||||
|
||||
Optional property for different chips:
|
||||
- clocks: from common clock binding: handle to grf_vio clock.
|
||||
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "grf"
|
||||
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
|
||||
- phys (required)
|
||||
|
||||
@@ -208,6 +208,7 @@ of the following host1x client modules:
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- sor: clock input for the SOR hardware
|
||||
- source: source clock for the SOR clock
|
||||
- parent: input for the pixel clock
|
||||
- dp: reference clock for the SOR clock
|
||||
- safe: safe reference for the SOR clock during power up
|
||||
@@ -226,9 +227,9 @@ of the following host1x client modules:
|
||||
- nvidia,dpaux: phandle to a DispayPort AUX interface
|
||||
|
||||
- dpaux: DisplayPort AUX interface
|
||||
- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
|
||||
must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
|
||||
<chip> is tegra132.
|
||||
- compatible : Should contain one of the following:
|
||||
- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
|
||||
- "nvidia,tegra210-dpaux": for Tegra210
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
@@ -241,6 +242,12 @@ of the following host1x client modules:
|
||||
- reset-names: Must include the following entries:
|
||||
- dpaux
|
||||
- vdd-supply: phandle of a supply that powers the DisplayPort link
|
||||
- i2c-bus: Subnode where I2C slave devices are listed. This subnode
|
||||
must be always present. If there are no I2C slave devices, an empty
|
||||
node should be added. See ../../i2c/i2c.txt for more information.
|
||||
|
||||
See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
|
||||
regarding the DPAUX pad controller bindings.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user