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Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main pull request for drm for 4.10 kernel. New drivers: - ZTE VOU display driver (zxdrm) - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson) - MXSFB support (mxsfb) Core: - Format handling has been reworked - Better atomic state debugging - drm_mm leak debugging - Atomic explicit fencing support - fbdev helper ops - Documentation updates - MST fbcon fixes Bridge: - Silicon Image SiI8620 driver Panel: - Add support for new simple panels i915: - GVT Device model - Better HDMI2.0 support on skylake - More watermark fixes - GPU idling rework for suspend/resume - DP Audio workarounds - Scheduler prep-work - Opregion CADL handling - GPU scheduler and priority boosting amdgfx/radeon: - Support for virtual devices - New VM manager for non-contig VRAM buffers - UVD powergating - SI register header cleanup - Cursor fixes - Powermanagement fixes nouveau: - Powermangement reworks for better voltage/clock changes - Atomic modesetting support - Displayport Multistream (MST) support. - GP102/104 hang and cursor fixes - GP106 support hisilicon: - hibmc support (BMC chip for aarch64 servers) armada: - add tracing support for overlay change - refactor plane support - de-midlayer the driver omapdrm: - Timing code cleanups rcar-du: - R8A7792/R8A7796 support - Misc fixes. sunxi: - A31 SoC display engine support imx-drm: - YUV format support - Cleanup plane atomic update mali-dp: - Misc fixes dw-hdmi: - Add support for HDMI i2c master controller tegra: - IOMMU support fixes - Error handling fixes tda998x: - Fix connector registration - Improved robustness - Fix infoframe/audio compliance virtio: - fix busid issues - allocate more vbufs qxl: - misc fixes and cleanups. vc4: - Fragment shader threading - ETC1 support - VEC (tv-out) support msm: - A5XX GPU support - Lots of atomic changes tilcdc: - Misc fixes and cleanups. etnaviv: - Fix dma-buf export path - DRAW_INSTANCED support - fix driver on i.MX6SX exynos: - HDMI refactoring fsl-dcu: - fbdev changes" * tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits) drm/nouveau/kms/nv50: fix atomic regression on original G80 drm/nouveau/bl: Do not register interface if Apple GMUX detected drm/nouveau/bl: Assign different names to interfaces drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2 drm/nouveau/ltc: protect clearing of comptags with mutex drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap drm/nouveau/core: recognise GP106 chipset drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode drm/nouveau/gr/gf100-: properly ack all FECS error interrupts drm/nouveau/fifo/gf100-: recover from host mmu faults drm: Add fake controlD* symlinks for backwards compat drm/vc4: Don't use drm_put_dev drm/vc4: Document VEC DT binding drm/vc4: Add support for the VEC (Video Encoder) IP drm: Add TV connector states to drm_connector_state drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum drm/vc4: Fix ->clock_select setting for the VEC encoder drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well drm/amdgpu: use pin rather than pin_restricted in a few cases ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,112 @@
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Amlogic Meson Display Controller
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================================
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The Amlogic Meson Display controller is composed of several components
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that are going to be documented below:
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DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
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| vd1 _______ _____________ _________________ | |
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D |-------| |----| | | | | HDMI PLL |
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D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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R |-------| |----| Processing | | | | |
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| osd2 | | | |---| Enci ----------|----|-----VDAC------|
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R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
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A | osd1 | | | Blenders | | Encl ----------|----|---------------|
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M |-------|______|----|____________| |________________| | |
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___|__________________________________________________________|_______________|
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VIU: Video Input Unit
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---------------------
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The Video Input Unit is in charge of the pixel scanout from the DDR memory.
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It fetches the frames addresses, stride and parameters from the "Canvas" memory.
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This part is also in charge of the CSC (Colorspace Conversion).
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It can handle 2 OSD Planes and 2 Video Planes.
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VPP: Video Post Processing
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--------------------------
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The Video Post Processing is in charge of the scaling and blending of the
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various planes into a single pixel stream.
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There is a special "pre-blending" used by the video planes with a dedicated
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scaler and a "post-blending" to merge with the OSD Planes.
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The OSD planes also have a dedicated scaler for one of the OSD.
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VENC: Video Encoders
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--------------------
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The VENC is composed of the multiple pixel encoders :
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- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
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- ENCP : Progressive Video Encoder for HDMI
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- ENCL : LCD LVDS Encoder
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The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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tree and provides the scanout clock to the VPP and VIU.
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The ENCI is connected to a single VDAC for Composite Output.
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The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
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Device Tree Bindings:
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---------------------
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VPU: Video Processing Unit
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--------------------------
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Required properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-vpu"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
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- GXM (S912) : "amlogic,meson-gxm-vpu"
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followed by the common "amlogic,meson-gx-vpu"
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- reg: base address and size of he following memory-mapped regions :
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- vpu
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- hhi
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- dmc
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- reg-names: should contain the names of the previous memory regions
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- interrupts: should contain the VENC Vsync interrupt number
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Required nodes:
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The connections to the VPU output video ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each VPU output.
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Port 0 Port 1
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-----------------------------------------
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S905 (GXBB) CVBS VDAC HDMI-TX
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S905X (GXL) CVBS VDAC HDMI-TX
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S905D (GXL) CVBS VDAC HDMI-TX
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S912 (GXM) CVBS VDAC HDMI-TX
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Example:
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tv-connector {
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compatible = "composite-video-connector";
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port {
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tv_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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vpu: vpu@d0100000 {
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compatible = "amlogic,meson-gxbb-vpu";
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reg = <0x0 0xd0100000 0x0 0x100000>,
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<0x0 0xc883c000 0x0 0x1000>,
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<0x0 0xc8838000 0x0 0x1000>;
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reg-names = "vpu", "hhi", "dmc";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* CVBS VDAC output port */
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port@0 {
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reg = <0>;
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&tv_connector_in>;
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};
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};
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};
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@@ -43,6 +43,13 @@ Required properties for DPI:
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- port: Port node with a single endpoint connecting to the panel
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device, as defined in [1]
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Required properties for VEC:
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- compatible: Should be "brcm,bcm2835-vec"
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- reg: Physical base address and length of the registers
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- clocks: The core clock the unit runs on
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- interrupts: The interrupt number
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See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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Required properties for V3D:
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- compatible: Should be "brcm,bcm2835-v3d"
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- reg: Physical base address and length of the V3D's registers
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@@ -92,6 +99,13 @@ dpi: dpi@7e208000 {
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};
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};
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vec: vec@7e806000 {
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compatible = "brcm,bcm2835-vec";
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reg = <0x7e806000 0x1000>;
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clocks = <&clocks BCM2835_CLOCK_VEC>;
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interrupts = <2 27>;
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};
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v3d: v3d@7ec00000 {
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compatible = "brcm,bcm2835-v3d";
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reg = <0x7ec00000 0x1000>;
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@@ -16,6 +16,8 @@ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
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- Video port 0 for RGB input
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- Video port 1 for VGA output
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Optional properties:
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- vdd-supply: Power supply for DAC
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Example
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-------
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@@ -19,7 +19,9 @@ Required properties:
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Optional properties
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- reg-io-width: the width of the reg:1,4, default set to 1 if not present
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
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if the property is omitted, a functionally reduced I2C bus
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controller on DW HDMI is probed
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- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
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Example:
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+7
-2
@@ -6,10 +6,15 @@ Required properties:
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Optional properties:
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- powerdown-gpios: power-down gpio
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- reg: I2C address. If and only if present the device node
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should be placed into the i2c controller node where the
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tfp410 i2c is connected to.
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Required nodes:
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- Video port 0 for DPI input
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- Video port 1 for DVI output
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- Video port 0 for DPI input [1].
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- Video port 1 for DVI output [1].
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[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
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Example
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-------
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@@ -1,20 +1,57 @@
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* Freescale MXS LCD Interface (LCDIF)
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New bindings:
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=============
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Required properties:
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- compatible: Should be "fsl,<chip>-lcdif". Supported chips include
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imx23 and imx28.
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- reg: Address and length of the register set for lcdif
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- interrupts: Should contain lcdif interrupts
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- display : phandle to display node (see below for details)
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- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
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Should be "fsl,imx28-lcdif" for i.MX28.
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Should be "fsl,imx6sx-lcdif" for i.MX6SX.
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- reg: Address and length of the register set for LCDIF
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- interrupts: Should contain LCDIF interrupt
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- clocks: A list of phandle + clock-specifier pairs, one for each
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entry in 'clock-names'.
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- clock-names: A list of clock names. For MXSFB it should contain:
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- "pix" for the LCDIF block clock
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- (MX6SX-only) "axi", "disp_axi" for the bus interface clock
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Required sub-nodes:
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- port: The connection to an encoder chip.
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Example:
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lcdif1: display-controller@2220000 {
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compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
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reg = <0x02220000 0x4000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
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<&clks IMX6SX_CLK_LCDIF_APB>,
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<&clks IMX6SX_CLK_DISPLAY_AXI>;
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clock-names = "pix", "axi", "disp_axi";
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port {
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parallel_out: endpoint {
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remote-endpoint = <&panel_in_parallel>;
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};
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};
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};
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Deprecated bindings:
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====================
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Required properties:
|
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- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
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Should be "fsl,imx28-lcdif" for i.MX28.
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- reg: Address and length of the register set for LCDIF
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- interrupts: Should contain LCDIF interrupts
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- display: phandle to display node (see below for details)
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* display node
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Required properties:
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- bits-per-pixel : <16> for RGB565, <32> for RGB888/666.
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- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>.
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- bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
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- bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
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Required sub-node:
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- display-timings : Refer to binding doc display-timing.txt for details.
|
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- display-timings: Refer to binding doc display-timing.txt for details.
|
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|
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Examples:
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|
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@@ -0,0 +1,7 @@
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AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
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Required properties:
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- compatible: should be "auo,g133han01"
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|
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This binding is compatible with the simple-panel binding, which is specified
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in simple-panel.txt in this directory.
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@@ -0,0 +1,7 @@
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AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
|
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|
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Required properties:
|
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- compatible: should be "auo,g185han01"
|
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|
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This binding is compatible with the simple-panel binding, which is specified
|
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in simple-panel.txt in this directory.
|
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@@ -0,0 +1,7 @@
|
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AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel
|
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|
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Required properties:
|
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- compatible: should be "auo,t215hvn01"
|
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|
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This binding is compatible with the simple-panel binding, which is specified
|
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in simple-panel.txt in this directory.
|
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@@ -0,0 +1,7 @@
|
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Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
|
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|
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Required properties:
|
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- compatible: should be "chunghwa,claa070wp03xg"
|
||||
|
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This binding is compatible with the simple-panel binding, which is specified
|
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in simple-panel.txt in this directory.
|
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@@ -32,6 +32,14 @@ optional properties:
|
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- active low = drive pixel data on falling edge/
|
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sample data on rising edge
|
||||
- ignored = ignored
|
||||
- syncclk-active: with
|
||||
- active high = drive sync on rising edge/
|
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sample sync on falling edge of pixel
|
||||
clock
|
||||
- active low = drive sync on falling edge/
|
||||
sample sync on rising edge of pixel
|
||||
clock
|
||||
- omitted = same configuration as pixelclk-active
|
||||
- interlaced (bool): boolean to enable interlaced mode
|
||||
- doublescan (bool): boolean to enable doublescan mode
|
||||
- doubleclk (bool): boolean to enable doubleclock mode
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nvd,9128"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,36 @@
|
||||
Sharp 15" LQ150X1LG11 XGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq150x1lg11"
|
||||
- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device
|
||||
- rlud-gpios: a single GPIO for the RL/UD (rotate 180 degrees) pin.
|
||||
- sellvds-gpios: a single GPIO for the SELLVDS pin.
|
||||
|
||||
If rlud-gpios and/or sellvds-gpios are not specified, the RL/UD and/or SELLVDS
|
||||
pins are assumed to be handled appropriately by the hardware.
|
||||
|
||||
Example:
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 0 100000>; /* VBR */
|
||||
|
||||
brightness-levels = <0 20 40 60 80 100>;
|
||||
default-brightness-level = <2>;
|
||||
|
||||
power-supply = <&vdd_12v_reg>; /* VDD */
|
||||
enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; /* XSTABY */
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "sharp,lq150x1lg11";
|
||||
|
||||
power-supply = <&vcc_3v3_reg>; /* VCC */
|
||||
|
||||
backlight = <&backlight>;
|
||||
rlud-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* RL/UD */
|
||||
sellvds-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; /* SELLVDS */
|
||||
};
|
||||
@@ -6,9 +6,11 @@ Required Properties:
|
||||
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
|
||||
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
|
||||
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
|
||||
- "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
|
||||
- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
|
||||
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
|
||||
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
|
||||
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
|
||||
|
||||
- reg: A list of base address and length of each memory resource, one for
|
||||
each entry in the reg-names property.
|
||||
@@ -25,10 +27,10 @@ Required Properties:
|
||||
- clock-names: Name of the clocks. This property is model-dependent.
|
||||
- R8A7779 uses a single functional clock. The clock doesn't need to be
|
||||
named.
|
||||
- R8A779[01345] use one functional clock per channel and one clock per LVDS
|
||||
encoder (if available). The functional clocks must be named "du.x" with
|
||||
"x" being the channel numerical index. The LVDS clocks must be named
|
||||
"lvds.x" with "x" being the LVDS encoder numerical index.
|
||||
- R8A779[0123456] use one functional clock per channel and one clock per
|
||||
LVDS encoder (if available). The functional clocks must be named "du.x"
|
||||
with "x" being the channel numerical index. The LVDS clocks must be
|
||||
named "lvds.x" with "x" being the LVDS encoder numerical index.
|
||||
- In addition to the functional and encoder clocks, all DU versions also
|
||||
support externally supplied pixel clocks. Those clocks are optional.
|
||||
When supplied they must be named "dclkin.x" with "x" being the input
|
||||
@@ -47,9 +49,11 @@ corresponding to each DU output.
|
||||
R8A7779 (H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
|
||||
R8A7791 (M2-W) DPAD LVDS 0 - -
|
||||
R8A7792 (V2H) DPAD 0 DPAD 1 - -
|
||||
R8A7793 (M2-N) DPAD LVDS 0 - -
|
||||
R8A7794 (E2) DPAD 0 DPAD 1 - -
|
||||
R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
|
||||
R8A7796 (M3-W) DPAD HDMI LVDS -
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) DU
|
||||
|
||||
@@ -28,6 +28,8 @@ The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
|
||||
Required properties:
|
||||
- compatible: value must be either:
|
||||
* allwinner,sun5i-a13-tcon
|
||||
* allwinner,sun6i-a31-tcon
|
||||
* allwinner,sun6i-a31s-tcon
|
||||
* allwinner,sun8i-a33-tcon
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
@@ -50,7 +52,7 @@ Required properties:
|
||||
second the block connected to the TCON channel 1 (usually the TV
|
||||
encoder)
|
||||
|
||||
On the A13, there is one more clock required:
|
||||
On SoCs other than the A33, there is one more clock required:
|
||||
- 'tcon-ch1': The clock driving the TCON channel 1
|
||||
|
||||
DRC
|
||||
@@ -64,6 +66,8 @@ adaptive backlight control.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-drc
|
||||
* allwinner,sun6i-a31s-drc
|
||||
* allwinner,sun8i-a33-drc
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- interrupts: interrupt associated to this IP
|
||||
@@ -87,6 +91,7 @@ system.
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-backend
|
||||
* allwinner,sun6i-a31-display-backend
|
||||
* allwinner,sun8i-a33-display-backend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- clocks: phandles to the clocks feeding the frontend and backend
|
||||
@@ -117,6 +122,7 @@ deinterlacing and color space conversion.
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-frontend
|
||||
* allwinner,sun6i-a31-display-frontend
|
||||
* allwinner,sun8i-a33-display-frontend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- interrupts: interrupt associated to this IP
|
||||
@@ -142,6 +148,8 @@ extra node.
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-engine
|
||||
* allwinner,sun6i-a31-display-engine
|
||||
* allwinner,sun6i-a31s-display-engine
|
||||
* allwinner,sun8i-a33-display-engine
|
||||
|
||||
- allwinner,pipelines: list of phandle to the display engine
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
Device-Tree bindings for tilcdc DRM driver
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "ti,am33xx-tilcdc".
|
||||
- compatible: value should be one of the following:
|
||||
- "ti,am33xx-tilcdc" for AM335x based boards
|
||||
- "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards
|
||||
- interrupts: the interrupt number
|
||||
- reg: base address and size of the LCDC device
|
||||
|
||||
@@ -51,7 +53,7 @@ Optional nodes:
|
||||
Example:
|
||||
|
||||
fb: fb@4830e000 {
|
||||
compatible = "ti,am33xx-tilcdc";
|
||||
compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc";
|
||||
reg = <0x4830e000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <36>;
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
ZTE VOU Display Controller
|
||||
|
||||
This is a display controller found on ZTE ZX296718 SoC. It includes multiple
|
||||
Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
|
||||
handling scaling, color space conversion etc. VOU also integrates the support
|
||||
for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
|
||||
|
||||
* Master VOU node
|
||||
|
||||
It must be the parent node of all the sub-device nodes.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-vou"
|
||||
- #address-cells: should be <1>
|
||||
- #size-cells: should be <1>
|
||||
- ranges: list of address translations between VOU and sub-devices
|
||||
|
||||
* VOU DPC device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-dpc"
|
||||
- reg: Physical base address and length of DPC register regions, one for each
|
||||
entry in 'reg-names'
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
"osd"
|
||||
"timing_ctrl"
|
||||
"dtrc"
|
||||
"vou_ctrl"
|
||||
"otfppu"
|
||||
- interrupts: VOU DPC interrupt number to CPU
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. The following clocks are required:
|
||||
"aclk"
|
||||
"ppu_wclk"
|
||||
"main_wclk"
|
||||
"aux_wclk"
|
||||
|
||||
* HDMI output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-hdmi"
|
||||
- reg: Physical base address and length of the HDMI device IO region
|
||||
- interrupts : HDMI interrupt number to CPU
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. The following clocks are required:
|
||||
"osc_cec"
|
||||
"osc_clk"
|
||||
"xclk"
|
||||
|
||||
Example:
|
||||
|
||||
vou: vou@1440000 {
|
||||
compatible = "zte,zx296718-vou";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1440000 0x10000>;
|
||||
|
||||
dpc: dpc@0 {
|
||||
compatible = "zte,zx296718-dpc";
|
||||
reg = <0x0000 0x1000>, <0x1000 0x1000>,
|
||||
<0x5000 0x1000>, <0x6000 0x1000>,
|
||||
<0xa000 0x1000>;
|
||||
reg-names = "osd", "timing_ctrl",
|
||||
"dtrc", "vou_ctrl",
|
||||
"otfppu";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
|
||||
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
|
||||
clock-names = "aclk", "ppu_wclk",
|
||||
"main_wclk", "aux_wclk";
|
||||
};
|
||||
|
||||
hdmi: hdmi@c000 {
|
||||
compatible = "zte,zx296718-hdmi";
|
||||
reg = <0xc000 0x4000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&topcrm HDMI_OSC_CEC>,
|
||||
<&topcrm HDMI_OSC_CLK>,
|
||||
<&topcrm HDMI_XCLK>;
|
||||
clock-names = "osc_cec", "osc_clk", "xclk";
|
||||
};
|
||||
};
|
||||
@@ -187,6 +187,7 @@ netgear NETGEAR
|
||||
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
|
||||
netxeon Shenzhen Netxeon Technology CO., LTD
|
||||
newhaven Newhaven Display International
|
||||
nvd New Vision Display
|
||||
nintendo Nintendo
|
||||
nokia Nokia
|
||||
nuvoton Nuvoton Technology Corporation
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
Silicon Image SiI8620 HDMI/MHL bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "sil,sii8620"
|
||||
- reg: i2c address of the bridge
|
||||
- cvcc10-supply: Digital Core Supply Voltage (1.0V)
|
||||
- iovcc18-supply: I/O Supply Voltage (1.8V)
|
||||
- interrupts, interrupt-parent: interrupt specifier of INT pin
|
||||
- reset-gpios: gpio specifier of RESET pin
|
||||
- clocks, clock-names: specification and name of "xtal" clock
|
||||
- video interfaces: Device node can contain video interface port
|
||||
node for HDMI encoder according to [1].
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
sii8620@39 {
|
||||
reg = <0x39>;
|
||||
compatible = "sil,sii8620";
|
||||
cvcc10-supply = <&ldo36_reg>;
|
||||
iovcc18-supply = <&ldo34_reg>;
|
||||
interrupt-parent = <&gpf0>;
|
||||
interrupts = <2 0>;
|
||||
reset-gpio = <&gpv7 0 0>;
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
clock-names = "xtal";
|
||||
|
||||
port {
|
||||
mhl_to_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_to_mhl>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -143,6 +143,9 @@ Device Instance and Driver Handling
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_drv.c
|
||||
:export:
|
||||
|
||||
.. kernel-doc:: include/drm/drm_drv.h
|
||||
:internal:
|
||||
|
||||
Driver Load
|
||||
-----------
|
||||
|
||||
@@ -350,6 +353,23 @@ how the ioctl is allowed to be called.
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
|
||||
:export:
|
||||
|
||||
|
||||
Misc Utilities
|
||||
==============
|
||||
|
||||
Printer
|
||||
-------
|
||||
|
||||
.. kernel-doc:: include/drm/drm_print.h
|
||||
:doc: print
|
||||
|
||||
.. kernel-doc:: include/drm/drm_print.h
|
||||
:internal:
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_print.c
|
||||
:export:
|
||||
|
||||
|
||||
Legacy Support Code
|
||||
===================
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user