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Merge tag 'omap-cleanup-sparseirq-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren: This branch contains changes needed to make omap2+ work properly with sparse IRQ. It also removes dependencies to mach/hardware.h. These help moving things towards ARM single zImage support. This branch is based on a commit in tty-next branch with omap-devel-gpmc-fixed-for-v3.7 and cleanup-omap-tags-for-v3.7 merged in to keep things compiling and sort out some merge conflicts. * tag 'omap-cleanup-sparseirq-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP1: Move SoC specific headers from plat to mach for omap1 ARM: OMAP2+ Move SoC specific headers to be local to mach-omap2 ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+ ARM: OMAP: Remove unused old gpio-switch.h ARM: OMAP1: Move plat/irqs.h to mach/irqs.h ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ ARM: OMAP2+: Prepare for irqs.h removal W1: OMAP HDQ1W: Remove dependencies to mach/hardware.h Input: omap-keypad: Remove dependencies to mach includes ARM: OMAP: Move gpio.h to include/linux/platform_data ARM: OMAP2+: Remove hardcoded twl4030 gpio_base, irq_base and irq_end ARM: OMAP2+: Remove unused nand_irq for GPMC ARM: OMAP2+: Make INTCPS_NR_IRQS local for mach-omap2/irq.c ARM: OMAP1: Define OMAP1_INT_I2C locally ARM: OMAP1: Move define of OMAP_LCD_DMA to dma.h
This commit is contained in:
Olof Johansson
@@ -18,6 +18,7 @@
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#include <plat/board-ams-delta.h>
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#include <mach/irqs.h>
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#include <mach/ams-delta-fiq.h>
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#include "iomap.h"
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@@ -26,6 +26,7 @@
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#include <linux/export.h>
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#include <linux/omapfb.h>
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#include <linux/io.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <media/soc_camera.h>
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@@ -41,7 +41,7 @@
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <plat/omap7xx.h>
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#include <mach/omap7xx.h>
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#include <plat/keypad.h>
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#include <plat/mmc.h>
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@@ -39,6 +39,7 @@
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/i2c/tps65010.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <linux/platform_data/omap1_bl.h>
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#include <asm/mach-types.h>
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@@ -23,8 +23,8 @@
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#include <plat/mux.h>
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#include <plat/dma.h>
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#include <plat/mmc.h>
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#include <plat/omap7xx.h>
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#include <mach/omap7xx.h>
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#include <mach/camera.h>
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#include <mach/hardware.h>
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@@ -27,7 +27,8 @@
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#include <plat/dma.h>
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#include <plat/tc.h>
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#include <plat/irqs.h>
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#include <mach/irqs.h>
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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@@ -17,6 +17,7 @@
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*/
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
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#define OMAP1510_GPIO_BASE 0xFFFCE000
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@@ -17,6 +17,7 @@
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*/
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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#define OMAP1610_GPIO1_BASE 0xfffbe400
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#define OMAP1610_GPIO2_BASE 0xfffbec00
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@@ -17,6 +17,7 @@
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*/
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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#define OMAP7XX_GPIO1_BASE 0xfffbc000
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#define OMAP7XX_GPIO2_BASE 0xfffbc800
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@@ -14,8 +14,6 @@
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#ifndef __AMS_DELTA_FIQ_H
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#define __AMS_DELTA_FIQ_H
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#include <plat/irqs.h>
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/*
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* Interrupt number used for passing control from FIQ to IRQ.
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* IRQ12, described as reserved, has been selected.
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@@ -1,5 +1,3 @@
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/*
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* arch/arm/mach-omap1/include/mach/gpio.h
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*/
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#include <plat/gpio.h>
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@@ -1,11 +1,46 @@
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/*
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* arch/arm/mach-omap1/include/mach/hardware.h
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*
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* Hardware definitions for TI OMAP processors and boards
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*
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* NOTE: Please put device driver specific defines into a separate header
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* file for each driver.
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*
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* Copyright (C) 2001 RidgeRun, Inc.
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* Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
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*
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* Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
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* and Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
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* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __MACH_HARDWARE_H
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#define __MACH_HARDWARE_H
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#ifndef __ASM_ARCH_OMAP_HARDWARE_H
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#define __ASM_ARCH_OMAP_HARDWARE_H
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#include <asm/sizes.h>
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#ifndef __ASSEMBLER__
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#include <asm/types.h>
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#include <plat/cpu.h>
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/*
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* NOTE: Please use ioremap + __raw_read/write where possible instead of these
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*/
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@@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void)
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? 0 : OMAP_CS3_PHYS;
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}
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#endif
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#endif /* ifndef __ASSEMBLER__ */
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#include <plat/serial.h>
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/*
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* ---------------------------------------------------------------------------
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* Common definitions for all OMAP processors
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* NOTE: Put all processor or board specific parts to the special header
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* files.
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* ---------------------------------------------------------------------------
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*/
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/*
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* ----------------------------------------------------------------------------
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* Timers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_MPU_TIMER1_BASE (0xfffec500)
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#define OMAP_MPU_TIMER2_BASE (0xfffec600)
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#define OMAP_MPU_TIMER3_BASE (0xfffec700)
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#define MPU_TIMER_FREE (1 << 6)
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#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
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#define MPU_TIMER_AR (1 << 1)
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#define MPU_TIMER_ST (1 << 0)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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* ----------------------------------------------------------------------------
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*/
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#define CLKGEN_REG_BASE (0xfffece00)
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#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
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#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
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#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
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#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
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#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
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#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
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#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
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#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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#define CK_RATEF 1
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#define CK_IDLEF 2
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#define CK_ENABLEF 4
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#define CK_SELECTF 8
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#define SETARM_IDLE_SHIFT
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/* DPLL control registers */
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#define DPLL_CTL (0xfffecf00)
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/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
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#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
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#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
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/*
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* ---------------------------------------------------------------------------
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* UPLD
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* ---------------------------------------------------------------------------
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*/
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#define ULPD_REG_BASE (0xfffe0800)
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#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
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# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
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#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
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# define SOFT_UDC_REQ (1 << 4)
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# define SOFT_USB_CLK_REQ (1 << 3)
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# define SOFT_DPLL_REQ (1 << 0)
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#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
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#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
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#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
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#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
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#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
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# define DIS_MMC2_DPLL_REQ (1 << 11)
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# define DIS_MMC1_DPLL_REQ (1 << 10)
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# define DIS_UART3_DPLL_REQ (1 << 9)
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# define DIS_UART2_DPLL_REQ (1 << 8)
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# define DIS_UART1_DPLL_REQ (1 << 7)
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# define DIS_USB_HOST_DPLL_REQ (1 << 6)
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#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
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#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
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/*
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* ---------------------------------------------------------------------------
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* Watchdog timer
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* ---------------------------------------------------------------------------
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*/
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/* Watchdog timer within the OMAP3.2 gigacell */
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#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
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#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
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#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
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/*
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* ---------------------------------------------------------------------------
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* Interrupts
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* ---------------------------------------------------------------------------
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*/
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#ifdef CONFIG_ARCH_OMAP1
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/*
|
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* XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
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* or something similar.. -- PFM.
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*/
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#define OMAP_IH1_BASE 0xfffecb00
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#define OMAP_IH2_BASE 0xfffe0000
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#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
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#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
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#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
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#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
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#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
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#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
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#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
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#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
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#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
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#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
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#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
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#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
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#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
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#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
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|
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#define IRQ_ITR_REG_OFFSET 0x00
|
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#define IRQ_MIR_REG_OFFSET 0x04
|
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#define IRQ_SIR_IRQ_REG_OFFSET 0x10
|
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#define IRQ_SIR_FIQ_REG_OFFSET 0x14
|
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#define IRQ_CONTROL_REG_OFFSET 0x18
|
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#define IRQ_ISR_REG_OFFSET 0x9c
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#define IRQ_ILR0_REG_OFFSET 0x1c
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#define IRQ_GMR_REG_OFFSET 0xa0
|
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|
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#endif
|
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|
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#include <plat/hardware.h>
|
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/*
|
||||
* ----------------------------------------------------------------------------
|
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* System control registers
|
||||
* ----------------------------------------------------------------------------
|
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*/
|
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#define MOD_CONF_CTRL_0 0xfffe1080
|
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#define MOD_CONF_CTRL_1 0xfffe1110
|
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|
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/*
|
||||
* ----------------------------------------------------------------------------
|
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* Pin multiplexing registers
|
||||
* ----------------------------------------------------------------------------
|
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*/
|
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#define FUNC_MUX_CTRL_0 0xfffe1000
|
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#define FUNC_MUX_CTRL_1 0xfffe1004
|
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#define FUNC_MUX_CTRL_2 0xfffe1008
|
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#define COMP_MODE_CTRL_0 0xfffe100c
|
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#define FUNC_MUX_CTRL_3 0xfffe1010
|
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#define FUNC_MUX_CTRL_4 0xfffe1014
|
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#define FUNC_MUX_CTRL_5 0xfffe1018
|
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#define FUNC_MUX_CTRL_6 0xfffe101C
|
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#define FUNC_MUX_CTRL_7 0xfffe1020
|
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#define FUNC_MUX_CTRL_8 0xfffe1024
|
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#define FUNC_MUX_CTRL_9 0xfffe1028
|
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#define FUNC_MUX_CTRL_A 0xfffe102C
|
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#define FUNC_MUX_CTRL_B 0xfffe1030
|
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#define FUNC_MUX_CTRL_C 0xfffe1034
|
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#define FUNC_MUX_CTRL_D 0xfffe1038
|
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#define PULL_DWN_CTRL_0 0xfffe1040
|
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#define PULL_DWN_CTRL_1 0xfffe1044
|
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#define PULL_DWN_CTRL_2 0xfffe1048
|
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#define PULL_DWN_CTRL_3 0xfffe104c
|
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#define PULL_DWN_CTRL_4 0xfffe10ac
|
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|
||||
/* OMAP-1610 specific multiplexing registers */
|
||||
#define FUNC_MUX_CTRL_E 0xfffe1090
|
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#define FUNC_MUX_CTRL_F 0xfffe1094
|
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#define FUNC_MUX_CTRL_10 0xfffe1098
|
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#define FUNC_MUX_CTRL_11 0xfffe109c
|
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#define FUNC_MUX_CTRL_12 0xfffe10a0
|
||||
#define PU_PD_SEL_0 0xfffe10b4
|
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#define PU_PD_SEL_1 0xfffe10b8
|
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#define PU_PD_SEL_2 0xfffe10bc
|
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#define PU_PD_SEL_3 0xfffe10c0
|
||||
#define PU_PD_SEL_4 0xfffe10c4
|
||||
|
||||
/* Timer32K for 1610 and 1710*/
|
||||
#define OMAP_TIMER32K_BASE 0xFFFBC400
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* TIPB bus interface
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
|
||||
#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
|
||||
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
|
||||
#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* MPUI interface
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define MPUI_BASE (0xfffec900)
|
||||
#define MPUI_CTRL (MPUI_BASE + 0x0)
|
||||
#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
|
||||
#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
|
||||
#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
|
||||
#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
|
||||
#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
|
||||
#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
|
||||
#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* LED Pulse Generator
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP_LPG1_BASE 0xfffbd000
|
||||
#define OMAP_LPG2_BASE 0xfffbd800
|
||||
#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
|
||||
#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
|
||||
#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
|
||||
#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
|
||||
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* Pulse-Width Light
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP_PWL_BASE 0xfffb5800
|
||||
#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
|
||||
#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* Processor specific defines
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include "omap7xx.h"
|
||||
#include "omap1510.h"
|
||||
#include "omap16xx.h"
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
|
||||
|
||||
@@ -1,5 +1,268 @@
|
||||
/*
|
||||
* arch/arm/mach-omap1/include/mach/irqs.h
|
||||
* arch/arm/plat-omap/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (C) Greg Lonnon 2001
|
||||
* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
|
||||
* are different.
|
||||
*/
|
||||
|
||||
#include <plat/irqs.h>
|
||||
#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
|
||||
#define __ASM_ARCH_OMAP15XX_IRQS_H
|
||||
|
||||
/*
|
||||
* IRQ numbers for interrupt handler 1
|
||||
*
|
||||
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
|
||||
*
|
||||
*/
|
||||
#define INT_CAMERA 1
|
||||
#define INT_FIQ 3
|
||||
#define INT_RTDX 6
|
||||
#define INT_DSP_MMU_ABORT 7
|
||||
#define INT_HOST 8
|
||||
#define INT_ABORT 9
|
||||
#define INT_BRIDGE_PRIV 13
|
||||
#define INT_GPIO_BANK1 14
|
||||
#define INT_UART3 15
|
||||
#define INT_TIMER3 16
|
||||
#define INT_DMA_CH0_6 19
|
||||
#define INT_DMA_CH1_7 20
|
||||
#define INT_DMA_CH2_8 21
|
||||
#define INT_DMA_CH3 22
|
||||
#define INT_DMA_CH4 23
|
||||
#define INT_DMA_CH5 24
|
||||
#define INT_TIMER1 26
|
||||
#define INT_WD_TIMER 27
|
||||
#define INT_BRIDGE_PUB 28
|
||||
#define INT_TIMER2 30
|
||||
#define INT_LCD_CTRL 31
|
||||
|
||||
/*
|
||||
* OMAP-1510 specific IRQ numbers for interrupt handler 1
|
||||
*/
|
||||
#define INT_1510_IH2_IRQ 0
|
||||
#define INT_1510_RES2 2
|
||||
#define INT_1510_SPI_TX 4
|
||||
#define INT_1510_SPI_RX 5
|
||||
#define INT_1510_DSP_MAILBOX1 10
|
||||
#define INT_1510_DSP_MAILBOX2 11
|
||||
#define INT_1510_RES12 12
|
||||
#define INT_1510_LB_MMU 17
|
||||
#define INT_1510_RES18 18
|
||||
#define INT_1510_LOCAL_BUS 29
|
||||
|
||||
/*
|
||||
* OMAP-1610 specific IRQ numbers for interrupt handler 1
|
||||
*/
|
||||
#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
|
||||
#define INT_1610_IH2_FIQ 2
|
||||
#define INT_1610_McBSP2_TX 4
|
||||
#define INT_1610_McBSP2_RX 5
|
||||
#define INT_1610_DSP_MAILBOX1 10
|
||||
#define INT_1610_DSP_MAILBOX2 11
|
||||
#define INT_1610_LCD_LINE 12
|
||||
#define INT_1610_GPTIMER1 17
|
||||
#define INT_1610_GPTIMER2 18
|
||||
#define INT_1610_SSR_FIFO_0 29
|
||||
|
||||
/*
|
||||
* OMAP-7xx specific IRQ numbers for interrupt handler 1
|
||||
*/
|
||||
#define INT_7XX_IH2_FIQ 0
|
||||
#define INT_7XX_IH2_IRQ 1
|
||||
#define INT_7XX_USB_NON_ISO 2
|
||||
#define INT_7XX_USB_ISO 3
|
||||
#define INT_7XX_ICR 4
|
||||
#define INT_7XX_EAC 5
|
||||
#define INT_7XX_GPIO_BANK1 6
|
||||
#define INT_7XX_GPIO_BANK2 7
|
||||
#define INT_7XX_GPIO_BANK3 8
|
||||
#define INT_7XX_McBSP2TX 10
|
||||
#define INT_7XX_McBSP2RX 11
|
||||
#define INT_7XX_McBSP2RX_OVF 12
|
||||
#define INT_7XX_LCD_LINE 14
|
||||
#define INT_7XX_GSM_PROTECT 15
|
||||
#define INT_7XX_TIMER3 16
|
||||
#define INT_7XX_GPIO_BANK5 17
|
||||
#define INT_7XX_GPIO_BANK6 18
|
||||
#define INT_7XX_SPGIO_WR 29
|
||||
|
||||
/*
|
||||
* IRQ numbers for interrupt handler 2
|
||||
*
|
||||
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
|
||||
*/
|
||||
#define IH2_BASE 32
|
||||
|
||||
#define INT_KEYBOARD (1 + IH2_BASE)
|
||||
#define INT_uWireTX (2 + IH2_BASE)
|
||||
#define INT_uWireRX (3 + IH2_BASE)
|
||||
#define INT_I2C (4 + IH2_BASE)
|
||||
#define INT_MPUIO (5 + IH2_BASE)
|
||||
#define INT_USB_HHC_1 (6 + IH2_BASE)
|
||||
#define INT_McBSP3TX (10 + IH2_BASE)
|
||||
#define INT_McBSP3RX (11 + IH2_BASE)
|
||||
#define INT_McBSP1TX (12 + IH2_BASE)
|
||||
#define INT_McBSP1RX (13 + IH2_BASE)
|
||||
#define INT_UART1 (14 + IH2_BASE)
|
||||
#define INT_UART2 (15 + IH2_BASE)
|
||||
#define INT_BT_MCSI1TX (16 + IH2_BASE)
|
||||
#define INT_BT_MCSI1RX (17 + IH2_BASE)
|
||||
#define INT_SOSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_USB_W2FC (20 + IH2_BASE)
|
||||
#define INT_1WIRE (21 + IH2_BASE)
|
||||
#define INT_OS_TIMER (22 + IH2_BASE)
|
||||
#define INT_MMC (23 + IH2_BASE)
|
||||
#define INT_GAUGE_32K (24 + IH2_BASE)
|
||||
#define INT_RTC_TIMER (25 + IH2_BASE)
|
||||
#define INT_RTC_ALARM (26 + IH2_BASE)
|
||||
#define INT_MEM_STICK (27 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-1510 specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_1510_DSP_MMU (28 + IH2_BASE)
|
||||
#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-1610 specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_1610_FAC (0 + IH2_BASE)
|
||||
#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
|
||||
#define INT_1610_USB_OTG (8 + IH2_BASE)
|
||||
#define INT_1610_SoSSI (9 + IH2_BASE)
|
||||
#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_1610_DSP_MMU (28 + IH2_BASE)
|
||||
#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
|
||||
#define INT_1610_STI (32 + IH2_BASE)
|
||||
#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER3 (34 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER4 (35 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER5 (36 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER6 (37 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER7 (38 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER8 (39 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
|
||||
#define INT_1610_MMC2 (42 + IH2_BASE)
|
||||
#define INT_1610_CF (43 + IH2_BASE)
|
||||
#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
|
||||
#define INT_1610_SPI (49 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH6 (53 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH7 (54 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH8 (55 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH9 (56 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH10 (57 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH11 (58 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH12 (59 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH13 (60 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_1610_NAND (63 + IH2_BASE)
|
||||
#define INT_1610_SHA1MD5 (91 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-7xx specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
|
||||
#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
|
||||
#define INT_7XX_CFCD (2 + IH2_BASE)
|
||||
#define INT_7XX_CFIREQ (3 + IH2_BASE)
|
||||
#define INT_7XX_I2C (4 + IH2_BASE)
|
||||
#define INT_7XX_PCC (5 + IH2_BASE)
|
||||
#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
|
||||
#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
|
||||
#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
|
||||
#define INT_7XX_VLYNQ (9 + IH2_BASE)
|
||||
#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1TX (11 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1RX (12 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
|
||||
#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
|
||||
#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
|
||||
#define INT_7XX_MCSI (16 + IH2_BASE)
|
||||
#define INT_7XX_uWireTX (17 + IH2_BASE)
|
||||
#define INT_7XX_uWireRX (18 + IH2_BASE)
|
||||
#define INT_7XX_SMC_CD (19 + IH2_BASE)
|
||||
#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
|
||||
#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
|
||||
#define INT_7XX_TIMER32K (22 + IH2_BASE)
|
||||
#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
|
||||
#define INT_7XX_UPLD (24 + IH2_BASE)
|
||||
#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
|
||||
#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
|
||||
#define INT_7XX_USB_GENI (29 + IH2_BASE)
|
||||
#define INT_7XX_USB_OTG (30 + IH2_BASE)
|
||||
#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
|
||||
#define INT_7XX_RNG (32 + IH2_BASE)
|
||||
#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
|
||||
#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
|
||||
#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
|
||||
#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
|
||||
#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
|
||||
#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
|
||||
#define INT_7XX_MPUIO (39 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
|
||||
#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_7XX_NAND (63 + IH2_BASE)
|
||||
|
||||
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
|
||||
* 16 MPUIO lines */
|
||||
#define OMAP_MAX_GPIO_LINES 192
|
||||
#define IH_GPIO_BASE (128 + IH2_BASE)
|
||||
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
|
||||
#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
|
||||
|
||||
/* External FPGA handles interrupts on Innovator boards */
|
||||
#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
|
||||
#ifdef CONFIG_MACH_OMAP_INNOVATOR
|
||||
#define OMAP_FPGA_NR_IRQS 24
|
||||
#else
|
||||
#define OMAP_FPGA_NR_IRQS 0
|
||||
#endif
|
||||
#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
|
||||
|
||||
#define NR_IRQS OMAP_FPGA_IRQ_END
|
||||
|
||||
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#ifdef CONFIG_FIQ
|
||||
#define FIQ_START 1024
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
+1
-2
@@ -1,5 +1,4 @@
|
||||
/* arch/arm/plat-omap/include/mach/omap1510.h
|
||||
*
|
||||
/*
|
||||
* Hardware definitions for TI OMAP1510 processor.
|
||||
*
|
||||
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
|
||||
+1
-2
@@ -1,5 +1,4 @@
|
||||
/* arch/arm/plat-omap/include/mach/omap16xx.h
|
||||
*
|
||||
/*
|
||||
* Hardware definitions for TI OMAP1610/5912/1710 processors.
|
||||
*
|
||||
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
|
||||
+1
-2
@@ -1,5 +1,4 @@
|
||||
/* arch/arm/plat-omap/include/mach/omap7xx.h
|
||||
*
|
||||
/*
|
||||
* Hardware definitions for TI OMAP7XX processor.
|
||||
*
|
||||
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/gpio-omap.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/leds.h>
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_data/gpio-omap.h>
|
||||
|
||||
#include <asm/leds.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
@@ -211,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = {
|
||||
};
|
||||
|
||||
static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
|
||||
.gpio_base = OMAP_MAX_GPIO_LINES,
|
||||
.irq_base = TWL4030_GPIO_IRQ_BASE,
|
||||
.irq_end = TWL4030_GPIO_IRQ_END,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data sdp2430_twldata = {
|
||||
@@ -234,7 +231,7 @@ static int __init omap2430_i2c_init(void)
|
||||
sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
|
||||
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
|
||||
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
|
||||
omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
|
||||
omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
|
||||
&sdp2430_twldata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user