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drm/msm: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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||||
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select {
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SAMPLE_0123 = 6,
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};
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enum a2xx_rb_blend_opcode {
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BLEND_DST_PLUS_SRC = 0,
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BLEND_SRC_MINUS_DST = 1,
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BLEND_MIN_DST_SRC = 2,
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BLEND_MAX_DST_SRC = 3,
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BLEND_DST_MINUS_SRC = 4,
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BLEND_DST_PLUS_SRC_BIAS = 5,
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};
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enum adreno_mmu_clnt_beh {
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BEH_NEVR = 0,
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BEH_TRAN_RNG = 1,
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@@ -890,6 +899,39 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
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#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
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#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
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#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
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#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
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#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
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#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
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#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
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}
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#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
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#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
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#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
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#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
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static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)
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{
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return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;
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}
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#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
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@@ -963,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend
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}
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#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0
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#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5
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static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)
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static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
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{
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return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
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}
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@@ -981,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend
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}
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#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000
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#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21
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static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)
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static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
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{
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return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
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}
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File diff suppressed because it is too large
Load Diff
@@ -19,6 +19,11 @@
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#define __A3XX_GPU_H__
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#include "adreno_gpu.h"
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/* arrg, somehow fb.h is getting pulled in: */
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#undef ROP_COPY
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#undef ROP_XOR
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#include "a3xx.xml.h"
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struct a3xx_gpu {
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@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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@@ -87,15 +87,6 @@ enum adreno_rb_blend_factor {
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FACTOR_SRC_ALPHA_SATURATE = 16,
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};
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enum adreno_rb_blend_opcode {
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BLEND_DST_PLUS_SRC = 0,
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BLEND_SRC_MINUS_DST = 1,
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BLEND_MIN_DST_SRC = 2,
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BLEND_MAX_DST_SRC = 3,
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BLEND_DST_MINUS_SRC = 4,
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BLEND_DST_PLUS_SRC_BIAS = 5,
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};
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enum adreno_rb_surface_endian {
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ENDIAN_NONE = 0,
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ENDIAN_8IN16 = 1,
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@@ -116,6 +107,39 @@ enum adreno_rb_depth_format {
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DEPTHX_24_8 = 1,
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};
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enum adreno_rb_copy_control_mode {
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RB_COPY_RESOLVE = 1,
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RB_COPY_CLEAR = 2,
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RB_COPY_DEPTH_STENCIL = 5,
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};
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enum a3xx_render_mode {
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RB_RENDERING_PASS = 0,
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RB_TILING_PASS = 1,
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RB_RESOLVE_PASS = 2,
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RB_COMPUTE_PASS = 3,
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};
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enum a3xx_msaa_samples {
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MSAA_ONE = 0,
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MSAA_TWO = 1,
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MSAA_FOUR = 2,
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};
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enum a3xx_threadmode {
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MULTI = 0,
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SINGLE = 1,
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};
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enum a3xx_instrbuffermode {
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BUFFER = 1,
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};
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enum a3xx_threadsize {
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TWO_QUADS = 0,
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FOUR_QUADS = 1,
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};
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#define REG_AXXX_CP_RB_BASE 0x000001c0
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#define REG_AXXX_CP_RB_CNTL 0x000001c1
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@@ -264,6 +288,8 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
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#define REG_AXXX_CP_INT_ACK 0x000001f4
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#define REG_AXXX_CP_ME_CNTL 0x000001f6
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#define AXXX_CP_ME_CNTL_BUSY 0x20000000
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#define AXXX_CP_ME_CNTL_HALT 0x10000000
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#define REG_AXXX_CP_ME_STATUS 0x000001f7
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@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
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Copyright (C) 2013 by the following authors:
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Copyright (C) 2013-2014 by the following authors:
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||||
- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
|
||||
@@ -105,6 +105,7 @@ enum pc_di_index_size {
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enum pc_di_vis_cull_mode {
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IGNORE_VISIBILITY = 0,
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USE_VISIBILITY = 1,
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};
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enum adreno_pm4_packet_type {
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@@ -163,6 +164,11 @@ enum adreno_pm4_type3_packets {
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CP_SET_BIN = 76,
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CP_TEST_TWO_MEMS = 113,
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CP_WAIT_FOR_ME = 19,
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CP_SET_DRAW_STATE = 67,
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CP_DRAW_INDX_OFFSET = 56,
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CP_DRAW_INDIRECT = 40,
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CP_DRAW_INDX_INDIRECT = 41,
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CP_DRAW_AUTO = 36,
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IN_IB_PREFETCH_END = 23,
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IN_SUBBLK_PREFETCH = 31,
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IN_INSTR_PREFETCH = 32,
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@@ -232,6 +238,211 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
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return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
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}
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#define REG_CP_DRAW_INDX_0 0x00000000
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#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
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#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
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}
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#define REG_CP_DRAW_INDX_1 0x00000001
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#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
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#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
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static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
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}
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#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
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#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
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static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
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{
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return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
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}
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#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
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#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
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#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
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#define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
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#define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
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static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
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||||
{
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return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
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||||
}
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||||
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||||
#define REG_CP_DRAW_INDX_2 0x00000002
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||||
#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
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||||
#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
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||||
{
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return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
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||||
}
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||||
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||||
#define REG_CP_DRAW_INDX_2 0x00000002
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||||
#define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
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||||
#define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
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||||
static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
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||||
{
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||||
return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
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||||
}
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||||
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||||
#define REG_CP_DRAW_INDX_2 0x00000002
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||||
#define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_0 0x00000000
|
||||
#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_1 0x00000001
|
||||
#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
|
||||
#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
|
||||
#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
|
||||
#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
|
||||
#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
|
||||
#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
|
||||
#define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
|
||||
#define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
|
||||
static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_2_2 0x00000002
|
||||
#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700
|
||||
#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800
|
||||
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000
|
||||
#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000
|
||||
#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000
|
||||
#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK 0xffff0000
|
||||
#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT 16
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_DRAW_STATE_0 0x00000000
|
||||
#define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
|
||||
#define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
|
||||
static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
|
||||
}
|
||||
#define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
|
||||
#define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
|
||||
#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
|
||||
#define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
|
||||
#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
|
||||
#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
|
||||
static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_DRAW_STATE_1 0x00000001
|
||||
#define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
|
||||
#define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_0 0x00000000
|
||||
|
||||
#define REG_CP_SET_BIN_1 0x00000001
|
||||
@@ -262,5 +473,21 @@ static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
|
||||
return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA_0 0x00000000
|
||||
#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA_1 0x00000001
|
||||
#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@@ -12,14 +12,14 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
@@ -148,9 +148,9 @@ static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*
|
||||
|
||||
static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_HDMI_ACR(uint32_t i0) { return 0x000000c4 + 0x8*i0; }
|
||||
static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
|
||||
|
||||
static inline uint32_t REG_HDMI_ACR_0(uint32_t i0) { return 0x000000c4 + 0x8*i0; }
|
||||
static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
|
||||
#define HDMI_ACR_0_CTS__MASK 0xfffff000
|
||||
#define HDMI_ACR_0_CTS__SHIFT 12
|
||||
static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
|
||||
@@ -158,7 +158,7 @@ static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
|
||||
return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_HDMI_ACR_1(uint32_t i0) { return 0x000000c8 + 0x8*i0; }
|
||||
static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
|
||||
#define HDMI_ACR_1_N__MASK 0xffffffff
|
||||
#define HDMI_ACR_1_N__SHIFT 0
|
||||
static inline uint32_t HDMI_ACR_1_N(uint32_t val)
|
||||
@@ -552,6 +552,103 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
|
||||
#define REG_HDMI_8960_PHY_REG11 0x0000042c
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG12 0x00000430
|
||||
#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
|
||||
#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434
|
||||
|
||||
#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG13 0x00000440
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG14 0x00000444
|
||||
|
||||
#define REG_HDMI_8960_PHY_REG15 0x00000448
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518
|
||||
#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
|
||||
#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598
|
||||
#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
|
||||
|
||||
#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c
|
||||
|
||||
#define REG_HDMI_8x74_ANA_CFG0 0x00000000
|
||||
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@@ -12,14 +12,14 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
Copyright (C) 2013-2014 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Reference in New Issue
Block a user