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Merge tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late
Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski: Topic branch for Device Tree changes adding new generic devfreq driver, for v4.7: 1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x. 2. Split out common PPMU (Performance Monitoring Unit) nodes into separate DTSI. The PPMU provides performance data for devfreq. 3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU on older designs, provides performance data for devfreq. 4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards: - Exynos3250 Rinato, - Exynos4412 Odroid-X/X2/U3 and Trats2, - Exynos5422 Odroid XU3/XU3-Lite/XU4. * tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
This commit is contained in:
Arnd Bergmann
@@ -14,6 +14,7 @@
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/dts-v1/;
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#include "exynos3250.dtsi"
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#include "exynos4412-ppmu-common.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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@@ -156,6 +157,12 @@
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};
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};
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&bus_dmc {
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
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vdd-supply = <&buck1_reg>;
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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@@ -458,46 +465,6 @@
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status = "okay";
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};
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&ppmu_dmc0 {
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status = "okay";
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events {
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ppmu_dmc0_3: ppmu-event3-dmc0 {
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event-name = "ppmu-event3-dmc0";
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};
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};
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};
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&ppmu_dmc1 {
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status = "okay";
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events {
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ppmu_dmc1_3: ppmu-event3-dmc1 {
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event-name = "ppmu-event3-dmc1";
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};
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};
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};
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&ppmu_leftbus {
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status = "okay";
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events {
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ppmu_leftbus_3: ppmu-event3-leftbus {
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event-name = "ppmu-event3-leftbus";
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};
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};
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};
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&ppmu_rightbus {
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status = "okay";
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events {
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ppmu_rightbus_3: ppmu-event3-rightbus {
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event-name = "ppmu-event3-rightbus";
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};
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};
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};
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&xusbxti {
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clock-frequency = <24000000>;
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};
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@@ -14,6 +14,7 @@
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/dts-v1/;
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#include "exynos3250.dtsi"
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#include "exynos4412-ppmu-common.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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@@ -147,6 +148,53 @@
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};
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};
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&bus_dmc {
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
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vdd-supply = <&buck1_reg>;
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status = "okay";
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};
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&bus_leftbus {
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devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
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vdd-supply = <&buck3_reg>;
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status = "okay";
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};
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&bus_rightbus {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_lcd0 {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_fsys {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_mcuisp {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_isp {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_peril {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&bus_mfc {
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devfreq = <&bus_leftbus>;
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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@@ -635,46 +683,6 @@
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status = "okay";
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};
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&ppmu_dmc0 {
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status = "okay";
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events {
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ppmu_dmc0_3: ppmu-event3-dmc0 {
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event-name = "ppmu-event3-dmc0";
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};
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};
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};
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&ppmu_dmc1 {
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status = "okay";
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events {
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ppmu_dmc1_3: ppmu-event3-dmc1 {
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event-name = "ppmu-event3-dmc1";
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};
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};
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};
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&ppmu_leftbus {
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status = "okay";
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events {
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ppmu_leftbus_3: ppmu-event3-leftbus {
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event-name = "ppmu-event3-leftbus";
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};
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};
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};
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&ppmu_rightbus {
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status = "okay";
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events {
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ppmu_rightbus_3: ppmu-event3-rightbus {
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event-name = "ppmu-event3-rightbus";
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};
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};
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};
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&xusbxti {
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clock-frequency = <24000000>;
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};
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@@ -688,6 +688,187 @@
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clock-names = "ppmu";
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status = "disabled";
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu_dmc CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_dmc_opp_table: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <800000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <800000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <800000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <825000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <875000>;
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};
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};
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bus_leftbus: bus_leftbus {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_GDL>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_rightbus: bus_rightbus {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_GDR>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_lcd0: bus_lcd0 {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_160>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_200>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_mcuisp: bus_mcuisp {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
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clock-names = "bus";
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operating-points-v2 = <&bus_mcuisp_opp_table>;
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status = "disabled";
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};
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bus_isp: bus_isp {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_266>;
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clock-names = "bus";
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operating-points-v2 = <&bus_isp_opp_table>;
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status = "disabled";
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};
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bus_peril: bus_peril {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_DIV_ACLK_100>;
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clock-names = "bus";
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operating-points-v2 = <&bus_peril_opp_table>;
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status = "disabled";
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};
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bus_mfc: bus_mfc {
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compatible = "samsung,exynos-bus";
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clocks = <&cmu CLK_SCLK_MFC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_leftbus_opp_table>;
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status = "disabled";
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};
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bus_leftbus_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <900000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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opp-microvolt = <900000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <1000000>;
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};
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opp@134000000 {
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opp-hz = /bits/ 64 <134000000>;
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opp-microvolt = <1000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1000000>;
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};
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};
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bus_mcuisp_opp_table: opp_table3 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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};
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};
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bus_isp_opp_table: opp_table4 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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};
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opp@300000000 {
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opp-hz = /bits/ 64 <300000000>;
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};
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};
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bus_peril_opp_table: opp_table5 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@50000000 {
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opp-hz = /bits/ 64 <50000000>;
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};
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opp@80000000 {
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opp-hz = /bits/ 64 <80000000>;
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};
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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};
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};
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};
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@@ -257,6 +257,165 @@
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power-domains = <&pd_lcd1>;
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#iommu-cells = <0>;
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};
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bus_dmc: bus_dmc {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_DMC>;
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clock-names = "bus";
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operating-points-v2 = <&bus_dmc_opp_table>;
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status = "disabled";
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};
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bus_acp: bus_acp {
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compatible = "samsung,exynos-bus";
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clocks = <&clock CLK_DIV_ACP>;
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clock-names = "bus";
|
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operating-points-v2 = <&bus_acp_opp_table>;
|
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status = "disabled";
|
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};
|
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bus_peri: bus_peri {
|
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compatible = "samsung,exynos-bus";
|
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clocks = <&clock CLK_ACLK100>;
|
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clock-names = "bus";
|
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operating-points-v2 = <&bus_peri_opp_table>;
|
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status = "disabled";
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};
|
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|
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bus_fsys: bus_fsys {
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compatible = "samsung,exynos-bus";
|
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clocks = <&clock CLK_ACLK133>;
|
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clock-names = "bus";
|
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operating-points-v2 = <&bus_fsys_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
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bus_display: bus_display {
|
||||
compatible = "samsung,exynos-bus";
|
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clocks = <&clock CLK_ACLK160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_display_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_lcd0: bus_lcd0 {
|
||||
compatible = "samsung,exynos-bus";
|
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clocks = <&clock CLK_ACLK200>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_acp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@5000000 {
|
||||
opp-hz = /bits/ 64 <5000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@10000000 {
|
||||
opp-hz = /bits/ 64 <10000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_display_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gic {
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
#include "exynos4412.dtsi"
|
||||
#include "exynos4412-ppmu-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
@@ -108,6 +109,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_acp {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_c2c {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_display {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
@@ -355,8 +403,8 @@
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
@@ -371,8 +419,8 @@
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Device tree sources for Exynos4412 PPMU common device tree
|
||||
*
|
||||
* Copyright (C) 2015 Samsung Electronics
|
||||
* Author: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -14,6 +14,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos4412.dtsi"
|
||||
#include "exynos4412-ppmu-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/maxim,max77686.h>
|
||||
@@ -288,6 +289,53 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_acp {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_c2c {
|
||||
devfreq = <&bus_dmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_display {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&buck2_reg>;
|
||||
};
|
||||
@@ -871,46 +919,6 @@
|
||||
assigned-clock-parents = <&clock CLK_XUSBXTI>;
|
||||
};
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_dmc1 {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_dmc1_3: ppmu-event3-dmc1 {
|
||||
event-name = "ppmu-event3-dmc1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_leftbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_leftbus_3: ppmu-event3-leftbus {
|
||||
event-name = "ppmu-event3-leftbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ppmu_rightbus {
|
||||
status = "okay";
|
||||
|
||||
events {
|
||||
ppmu_rightbus_3: ppmu-event3-rightbus {
|
||||
event-name = "ppmu-event3-rightbus";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sleep0>;
|
||||
|
||||
@@ -281,6 +281,180 @@
|
||||
clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
bus_dmc: bus_dmc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_DMC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_acp: bus_acp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_ACP>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_acp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_c2c: bus_c2c {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_C2C>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_acp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@267000000 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_display: bus_display {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_display_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK133>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peri: bus_peri {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_ACLK100>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peri_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_display_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combiner {
|
||||
|
||||
@@ -294,6 +294,42 @@
|
||||
};
|
||||
};
|
||||
|
||||
nocp_mem0_0: nocp@10CA1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem0_1: nocp@10CA1400 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1400 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem1_0: nocp@10CA1800 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1800 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_mem1_1: nocp@10CA1C00 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1C00 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_g3d_0: nocp@11A51000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x11A51000 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nocp_g3d_1: nocp@11A51400 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x11A51400 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsc_pd: power-domain@10044000 {
|
||||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
@@ -1188,6 +1224,377 @@
|
||||
power-domains = <&disp_pd>;
|
||||
#iommu-cells = <0>;
|
||||
};
|
||||
|
||||
bus_wcore: bus_wcore {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_wcore_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_noc: bus_noc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_noc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys_apb: bus_fsys_apb {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys2: bus_fsys2 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_fsys2_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK333>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mfc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_gen: bus_gen {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK266>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_gen_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peri: bus_peri {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK66>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peri_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_g2d: bus_g2d {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_g2d_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_g2d_acp: bus_g2d_acp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_g2d_acp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_jpeg: bus_jpeg {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_jpeg_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_jpeg_apb: bus_jpeg_apb {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK166>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_disp1_fimd: bus_disp1_fimd {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_disp1: bus_disp1 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_disp1_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_gscl_scaler: bus_gscl_scaler {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_gscl_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mscl: bus_mscl {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mscl_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_wcore_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <987500>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_noc_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <86000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys_apb_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_fsys2_opp_table: opp_table5 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mfc_opp_table: opp_table6 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <96000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_gen_opp_table: opp_table7 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <89000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <133000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <178000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peri_opp_table: opp_table8 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_g2d_opp_table: opp_table9 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_g2d_acp_opp_table: opp_table10 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <67000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <133000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <178000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <267000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_jpeg_opp_table: opp_table11 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_jpeg_apb_opp_table: opp_table12 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <111000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_disp1_fimd_opp_table: opp_table13 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_disp1_opp_table: opp_table14 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_gscl_opp_table: opp_table15 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mscl_opp_table: opp_table16 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <84000000>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <167000000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <222000000>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <333000000>;
|
||||
};
|
||||
opp04 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dp {
|
||||
|
||||
@@ -56,6 +56,89 @@
|
||||
};
|
||||
};
|
||||
|
||||
&bus_wcore {
|
||||
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
|
||||
<&nocp_mem1_0>, <&nocp_mem1_1>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
exynos,saturation-ratio = <100>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_noc {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys_apb {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys2 {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_gen {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peri {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_g2d {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_g2d_acp {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_jpeg {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_jpeg_apb {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_disp1_fimd {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_disp1 {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_gscl_scaler {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mscl {
|
||||
devfreq = <&bus_wcore>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clock_audss {
|
||||
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
|
||||
<&clock_audss EXYNOS_MOUT_I2S>,
|
||||
@@ -361,6 +444,22 @@
|
||||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
&nocp_mem0_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem0_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem1_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nocp_mem1_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
hdmi_hpd_irq: hdmi-hpd-irq {
|
||||
samsung,pins = "gpx3-7";
|
||||
|
||||
@@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
|
||||
};
|
||||
|
||||
static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
|
||||
DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
|
||||
|
||||
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
|
||||
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
|
||||
DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
|
||||
DIV_TOP8, 16, 3),
|
||||
DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
|
||||
@@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
|
||||
};
|
||||
|
||||
static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
|
||||
DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
|
||||
DIV_TOP0, 16, 3),
|
||||
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
|
||||
"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
|
||||
@@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
|
||||
DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
|
||||
DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
|
||||
|
||||
DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
|
||||
DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
|
||||
DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
|
||||
DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
|
||||
DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
|
||||
DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
|
||||
DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
|
||||
DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
|
||||
DIV_TOP0, 0, 3),
|
||||
DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
|
||||
DIV_TOP0, 4, 3),
|
||||
DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
|
||||
DIV_TOP0, 8, 3),
|
||||
DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
|
||||
DIV_TOP0, 12, 3),
|
||||
DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
|
||||
DIV_TOP0, 20, 3),
|
||||
DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
|
||||
DIV_TOP0, 24, 3),
|
||||
DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
|
||||
DIV_TOP0, 28, 3),
|
||||
DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
|
||||
"mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
|
||||
DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
|
||||
"mout_aclk333_432_isp", DIV_TOP1, 4, 3),
|
||||
DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
|
||||
DIV_TOP1, 8, 6),
|
||||
DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
|
||||
"mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
|
||||
DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
|
||||
DIV_TOP1, 20, 3),
|
||||
DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
|
||||
DIV_TOP1, 24, 3),
|
||||
DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
|
||||
DIV_TOP1, 28, 3),
|
||||
|
||||
DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
|
||||
DIV_TOP1, 0, 3),
|
||||
DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
|
||||
DIV_TOP1, 4, 3),
|
||||
DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
|
||||
DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
|
||||
DIV_TOP1, 16, 3),
|
||||
DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
|
||||
DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
|
||||
DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
|
||||
|
||||
DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
|
||||
DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
|
||||
DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
|
||||
DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
|
||||
DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
|
||||
DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
|
||||
DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
|
||||
DIV_TOP2, 8, 3),
|
||||
DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
|
||||
DIV_TOP2, 12, 3),
|
||||
DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
|
||||
16, 3),
|
||||
DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
|
||||
DIV_TOP2, 20, 3),
|
||||
DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
|
||||
"mout_aclk300_disp1", DIV_TOP2, 24, 3),
|
||||
DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
|
||||
DIV_TOP2, 28, 3),
|
||||
|
||||
/* DISP1 Block */
|
||||
DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
|
||||
@@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
|
||||
DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
|
||||
DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
|
||||
DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
|
||||
DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
|
||||
DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
|
||||
"mout_aclk400_disp1", DIV_TOP2, 4, 3),
|
||||
|
||||
/* Audio Block */
|
||||
DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
|
||||
|
||||
@@ -217,8 +217,30 @@
|
||||
|
||||
/* divider clocks */
|
||||
#define CLK_DOUT_PIXEL 768
|
||||
#define CLK_DOUT_ACLK400_WCORE 769
|
||||
#define CLK_DOUT_ACLK400_ISP 770
|
||||
#define CLK_DOUT_ACLK400_MSCL 771
|
||||
#define CLK_DOUT_ACLK200 772
|
||||
#define CLK_DOUT_ACLK200_FSYS2 773
|
||||
#define CLK_DOUT_ACLK100_NOC 774
|
||||
#define CLK_DOUT_PCLK200_FSYS 775
|
||||
#define CLK_DOUT_ACLK200_FSYS 776
|
||||
#define CLK_DOUT_ACLK333_432_GSCL 777
|
||||
#define CLK_DOUT_ACLK333_432_ISP 778
|
||||
#define CLK_DOUT_ACLK66 779
|
||||
#define CLK_DOUT_ACLK333_432_ISP0 780
|
||||
#define CLK_DOUT_ACLK266 781
|
||||
#define CLK_DOUT_ACLK166 782
|
||||
#define CLK_DOUT_ACLK333 783
|
||||
#define CLK_DOUT_ACLK333_G2D 784
|
||||
#define CLK_DOUT_ACLK266_G2D 785
|
||||
#define CLK_DOUT_ACLK_G3D 786
|
||||
#define CLK_DOUT_ACLK300_JPEG 787
|
||||
#define CLK_DOUT_ACLK300_DISP1 788
|
||||
#define CLK_DOUT_ACLK300_GSCL 789
|
||||
#define CLK_DOUT_ACLK400_DISP1 790
|
||||
|
||||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 769
|
||||
#define CLK_NR_CLKS 791
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
|
||||
|
||||
Reference in New Issue
Block a user