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[PPC] Remove mpc885ads and mpc86x ads boards from arch/ppc
We have a board port in arch/powerpc so we dont need this one anymore. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
@@ -946,29 +946,6 @@ static int __init scc_enet_init(void)
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*((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
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#endif
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#ifdef CONFIG_MPC885ADS
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/* Deassert PHY reset and enable the PHY.
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*/
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{
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volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
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uint tmp;
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tmp = in_be32(bcsr + 1 /* BCSR1 */);
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tmp |= BCSR1_ETHEN;
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out_be32(bcsr + 1, tmp);
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tmp = in_be32(bcsr + 4 /* BCSR4 */);
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tmp |= BCSR4_ETH10_RST;
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out_be32(bcsr + 4, tmp);
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iounmap(bcsr);
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}
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/* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
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* upon reset. SCC is set to half duplex by default. So this
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* inconsistency should be better fixed by the software.
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*/
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#endif
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dev->base_addr = (unsigned long)ep;
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#if 0
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dev->name = "CPM_ENET";
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@@ -372,22 +372,6 @@ config MPC8XXFADS
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bool "FADS"
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select FADS
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config MPC86XADS
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bool "MPC86XADS"
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help
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MPC86x Application Development System by Freescale Semiconductor.
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The MPC86xADS is meant to serve as a platform for s/w and h/w
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development around the MPC86X processor families.
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select FADS
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config MPC885ADS
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bool "MPC885ADS"
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help
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Freescale Semiconductor MPC885 Application Development System (ADS).
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Also known as DUET.
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The MPC885ADS is meant to serve as a platform for s/w and h/w
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development around the MPC885 processor family.
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config TQM823L
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bool "TQM823L"
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help
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@@ -479,53 +463,6 @@ config WINCEPT
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endchoice
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menu "Freescale Ethernet driver platform-specific options"
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depends on FS_ENET
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config MPC8xx_SECOND_ETH
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bool "Second Ethernet channel"
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depends on (MPC885ADS || MPC86XADS)
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default y
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help
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This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
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The latter will use SCC1, for 885ADS you can select it below.
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choice
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prompt "Second Ethernet channel"
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depends on MPC8xx_SECOND_ETH
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default MPC8xx_SECOND_ETH_FEC2
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config MPC8xx_SECOND_ETH_FEC2
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bool "FEC2"
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depends on MPC885ADS
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help
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Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
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(often 2-nd UART) will not work if this is enabled.
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config MPC8xx_SECOND_ETH_SCC1
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bool "SCC1"
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depends on MPC86XADS
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select MPC8xx_SCC_ENET_FIXED
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help
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Enable SCC1 to serve as 2-nd Ethernet channel. Note that SMC1
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(often 1-nd UART) will not work if this is enabled.
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config MPC8xx_SECOND_ETH_SCC3
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bool "SCC3"
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depends on MPC885ADS
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help
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Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
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(often 1-nd UART) will not work if this is enabled.
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endchoice
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config MPC8xx_SCC_ENET_FIXED
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depends on MPC8xx_SECOND_ETH_SCC
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default n
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bool "Use fixed MII-less mode for SCC Ethernet"
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endmenu
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choice
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prompt "Machine Type"
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depends on 6xx
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -23,5 +23,3 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
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obj-$(CONFIG_SPRUCE) += spruce.o
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obj-$(CONFIG_LITE5200) += lite5200.o
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obj-$(CONFIG_EV64360) += ev64360.o
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obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
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obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
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@@ -22,29 +22,6 @@
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#include <asm/ppcboot.h>
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#if defined(CONFIG_MPC86XADS)
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#define BOARD_CHIP_NAME "MPC86X"
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/* U-Boot maps BCSR to 0xff080000 */
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#define BCSR_ADDR ((uint)0xff080000)
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/* MPC86XADS has one more CPLD and an additional BCSR.
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*/
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* There is no PHY link change interrupt */
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#define PHY_INTERRUPT (-1)
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#else /* FADS */
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/* Memory map is configured by the PROM startup.
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* I tried to follow the FADS manual, although the startup PROM
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* dictates this and we simply have to move some of the physical
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@@ -55,8 +32,6 @@
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/* PHY link change interrupt */
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#define PHY_INTERRUPT SIU_IRQ2
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#endif /* CONFIG_MPC86XADS */
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#define BCSR_SIZE ((uint)(64 * 1024))
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#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
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#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
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@@ -1,93 +0,0 @@
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/*
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* A collection of structures, addresses, and values associated with
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* the Freescale MPC885ADS board.
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* Copied from the FADS stuff.
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_MPC885ADS_H__
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#define __ASM_MPC885ADS_H__
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#include <asm/ppcboot.h>
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/* U-Boot maps BCSR to 0xff080000 */
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#define BCSR_ADDR ((uint)0xff080000)
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#define BCSR_SIZE ((uint)32)
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#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
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#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
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#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
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#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define IMAP_ADDR ((uint)0xff000000)
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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/* Bits of interest in the BCSRs.
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*/
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDAEN ((uint)0x10000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP0 ((uint)0x00200000)
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#define BCSR1_PCCVPP1 ((uint)0x00100000)
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#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
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#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
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#define BCSR4_USB_LO_SPD ((uint)0x04000000)
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#define BCSR4_USB_VCC ((uint)0x02000000)
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#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
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#define BCSR4_USB_EN ((uint)0x00020000)
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#define BCSR5_MII2_EN 0x40
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#define BCSR5_MII2_RST 0x20
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* Interrupt level assignments */
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#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
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#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
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#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
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#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
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/* We don't use the 8259 */
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#define NR_8259_INTS 0
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/* CPM Ethernet through SCC3 */
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#define PA_ENET_RXD ((ushort)0x0040)
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#define PA_ENET_TXD ((ushort)0x0080)
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#define PE_ENET_TCLK ((uint)0x00004000)
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#define PE_ENET_RCLK ((uint)0x00008000)
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#define PE_ENET_TENA ((uint)0x00000010)
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#define PC_ENET_CLSN ((ushort)0x0400)
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#define PC_ENET_RENA ((ushort)0x0800)
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/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
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* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
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#define SICR_ENET_MASK ((uint)0x00ff0000)
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#define SICR_ENET_CLKRT ((uint)0x002c0000)
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#define BOARD_CHIP_NAME "MPC885"
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#endif /* __ASM_MPC885ADS_H__ */
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#endif /* __KERNEL__ */
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@@ -1,476 +0,0 @@
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/*arch/ppc/platforms/mpc885ads_setup.c
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*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/mii.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/ppcboot.h>
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#include <asm/8xx_immap.h>
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#include <asm/cpm1.h>
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#include <asm/ppc_sys.h>
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extern unsigned char __res[];
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static void setup_smc1_ioports(struct fs_uart_platform_info*);
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static void setup_smc2_ioports(struct fs_uart_platform_info*);
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static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
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static void setup_fec1_ioports(struct fs_platform_info*);
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static void setup_fec2_ioports(struct fs_platform_info*);
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static void setup_scc3_ioports(struct fs_platform_info*);
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static struct fs_uart_platform_info mpc885_uart_pdata[] = {
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[fsid_smc1_uart] = {
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.brg = 1,
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.fs_no = fsid_smc1_uart,
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.init_ioports = setup_smc1_ioports,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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[fsid_smc2_uart] = {
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.brg = 2,
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.fs_no = fsid_smc2_uart,
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.init_ioports = setup_smc2_ioports,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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};
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static struct fs_platform_info mpc8xx_enet_pdata[] = {
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[fsid_fec1] = {
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_fec1_ioports,
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.bus_id = "0:00",
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.has_phy = 1,
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},
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[fsid_fec2] = {
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_fec2_ioports,
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.bus_id = "0:01",
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.has_phy = 1,
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},
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[fsid_scc3] = {
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.rx_ring = 64,
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.tx_ring = 8,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_scc3_ioports,
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#ifdef CONFIG_FIXED_MII_10_FDX
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.bus_id = "fixed@100:1",
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#else
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.bus_id = "0:02",
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#endif
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},
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};
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void __init board_init(void)
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{
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cpm8xx_t *cp = cpmp;
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unsigned int *bcsr_io;
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#ifdef CONFIG_FS_ENET
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immap_t *immap = (immap_t *) IMAP_ADDR;
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#endif
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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#ifdef CONFIG_SERIAL_CPM_SMC1
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cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
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clrbits32(bcsr_io, BCSR1_RS232EN_1);
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cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
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cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_1);
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cp->cp_smc[0].smc_smcmr = 0;
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cp->cp_smc[0].smc_smce = 0;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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cp->cp_simode &= ~(0xe0000000 >> 1);
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cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
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cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_2);
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cp->cp_smc[1].smc_smcmr = 0;
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cp->cp_smc[1].smc_smce = 0;
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#endif
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iounmap(bcsr_io);
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#ifdef CONFIG_FS_ENET
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/* use MDC for MII (common) */
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setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
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clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
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bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
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clrbits32(bcsr_io,BCSR5_MII1_EN);
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clrbits32(bcsr_io,BCSR5_MII1_RST);
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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clrbits32(bcsr_io,BCSR5_MII2_EN);
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clrbits32(bcsr_io,BCSR5_MII2_RST);
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#endif
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iounmap(bcsr_io);
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#endif
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}
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static void setup_fec1_ioports(struct fs_platform_info* pdata)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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/* configure FEC1 pins */
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setbits16(&immap->im_ioport.iop_papar, 0xf830);
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setbits16(&immap->im_ioport.iop_padir, 0x0830);
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clrbits16(&immap->im_ioport.iop_padir, 0xf000);
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setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
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clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
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setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
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clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
|
||||
setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
|
||||
|
||||
setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
|
||||
clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
|
||||
clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
|
||||
}
|
||||
|
||||
static void setup_fec2_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
|
||||
/* configure FEC2 pins */
|
||||
setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
|
||||
setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
|
||||
clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
|
||||
setbits32(&immap->im_cpm.cp_peso, 0x00037800);
|
||||
clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
|
||||
}
|
||||
|
||||
static void setup_scc3_ioports(struct fs_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
|
||||
bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable the PHY.
|
||||
*/
|
||||
clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
udelay(1000);
|
||||
setbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
/* Configure port A pins for Txd and Rxd.
|
||||
*/
|
||||
setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
|
||||
|
||||
/* Configure port C pins to enable CLSN and RENA.
|
||||
*/
|
||||
clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
|
||||
/* Configure port E for TCLK and RCLK.
|
||||
*/
|
||||
setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_pedir,
|
||||
PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
|
||||
|
||||
/* Configure Serial Interface clock routing.
|
||||
* First, clear all SCC bits to zero, then set the ones we want.
|
||||
*/
|
||||
clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
|
||||
setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
|
||||
|
||||
/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
|
||||
*/
|
||||
immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
|
||||
/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
|
||||
* by H/W setting after reset. SCC ethernet controller support only half duplex.
|
||||
* This discrepancy of modes causes a lot of carrier lost errors.
|
||||
*/
|
||||
|
||||
/* In the original SCC enet driver the following code is placed at
|
||||
the end of the initialization */
|
||||
setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
|
||||
setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
|
||||
|
||||
setbits32(bcsr_io+4, BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static int mac_count = 0;
|
||||
|
||||
static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
|
||||
{
|
||||
struct fs_platform_info *fpi;
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
char *e;
|
||||
int i;
|
||||
|
||||
if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
|
||||
printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
|
||||
return;
|
||||
}
|
||||
|
||||
fpi = &mpc8xx_enet_pdata[fs_no];
|
||||
|
||||
switch (fs_no) {
|
||||
case fsid_fec1:
|
||||
fpi->init_ioports = &setup_fec1_ioports;
|
||||
break;
|
||||
case fsid_fec2:
|
||||
fpi->init_ioports = &setup_fec2_ioports;
|
||||
break;
|
||||
case fsid_scc3:
|
||||
fpi->init_ioports = &setup_scc3_ioports;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
|
||||
return;
|
||||
}
|
||||
|
||||
pdev->dev.platform_data = fpi;
|
||||
fpi->fs_no = fs_no;
|
||||
|
||||
e = (unsigned char *)&bd->bi_enetaddr;
|
||||
for (i = 0; i < 6; i++)
|
||||
fpi->macaddr[i] = *e++;
|
||||
|
||||
fpi->macaddr[5] += mac_count++;
|
||||
|
||||
}
|
||||
|
||||
static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
/* This is for FEC devices only */
|
||||
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
|
||||
return;
|
||||
mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
|
||||
}
|
||||
|
||||
static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
/* This is for SCC devices only */
|
||||
if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
|
||||
return;
|
||||
|
||||
mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
|
||||
}
|
||||
|
||||
static void setup_smc1_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
unsigned int iobits = 0x000000c0;
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
iounmap(bcsr_io);
|
||||
|
||||
setbits32(&immap->im_cpm.cp_pbpar, iobits);
|
||||
clrbits32(&immap->im_cpm.cp_pbdir, iobits);
|
||||
clrbits16(&immap->im_cpm.cp_pbodr, iobits);
|
||||
}
|
||||
|
||||
static void setup_smc2_ioports(struct fs_uart_platform_info* pdata)
|
||||
{
|
||||
immap_t *immap = (immap_t *) IMAP_ADDR;
|
||||
unsigned *bcsr_io;
|
||||
unsigned int iobits = 0x00000c00;
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
iounmap(bcsr_io);
|
||||
|
||||
#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
|
||||
setbits32(&immap->im_cpm.cp_pbpar, iobits);
|
||||
clrbits32(&immap->im_cpm.cp_pbdir, iobits);
|
||||
clrbits16(&immap->im_cpm.cp_pbodr, iobits);
|
||||
#else
|
||||
setbits16(&immap->im_ioport.iop_papar, iobits);
|
||||
clrbits16(&immap->im_ioport.iop_padir, iobits);
|
||||
clrbits16(&immap->im_ioport.iop_paodr, iobits);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init mpc885ads_fixup_uart_pdata(struct platform_device *pdev,
|
||||
int idx)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
int num = ARRAY_SIZE(mpc885_uart_pdata);
|
||||
|
||||
int id = fs_uart_id_smc2fsid(idx);
|
||||
|
||||
/* no need to alter anything if console */
|
||||
if ((id < num) && (!pdev->dev.platform_data)) {
|
||||
pinfo = &mpc885_uart_pdata[id];
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static int mpc885ads_platform_notify(struct device *dev)
|
||||
{
|
||||
|
||||
static const struct platform_notify_dev_map dev_map[] = {
|
||||
{
|
||||
.bus_id = "fsl-cpm-fec",
|
||||
.rtn = mpc885ads_fixup_fec_enet_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-cpm-scc",
|
||||
.rtn = mpc885ads_fixup_scc_enet_pdata,
|
||||
},
|
||||
{
|
||||
.bus_id = "fsl-cpm-smc:uart",
|
||||
.rtn = mpc885ads_fixup_uart_pdata
|
||||
},
|
||||
{
|
||||
.bus_id = NULL
|
||||
}
|
||||
};
|
||||
|
||||
platform_notify_map(dev_map,dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mpc885ads_init(void)
|
||||
{
|
||||
struct fs_mii_fec_platform_info* fmpi;
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
|
||||
printk(KERN_NOTICE "mpc885ads: Init\n");
|
||||
|
||||
platform_notify = mpc885ads_platform_notify;
|
||||
|
||||
ppc_sys_device_initfunc();
|
||||
ppc_sys_device_disable_all();
|
||||
|
||||
ppc_sys_device_enable(MPC8xx_CPM_FEC1);
|
||||
|
||||
ppc_sys_device_enable(MPC8xx_MDIO_FEC);
|
||||
fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
|
||||
&mpc8xx_mdio_fec_pdata;
|
||||
|
||||
fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
|
||||
|
||||
/* No PHY interrupt line here */
|
||||
fmpi->irq[0xf] = SIU_IRQ7;
|
||||
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SCC3);
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
|
||||
ppc_sys_device_enable(MPC8xx_CPM_FEC2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SMC1);
|
||||
ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
ppc_sys_device_enable(MPC8xx_CPM_SMC2);
|
||||
ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(mpc885ads_init);
|
||||
|
||||
/*
|
||||
To prevent confusion, console selection is gross:
|
||||
by 0 assumed SMC1 and by 1 assumed SMC2
|
||||
*/
|
||||
struct platform_device* early_uart_get_pdev(int index)
|
||||
{
|
||||
bd_t *bd = (bd_t *) __res;
|
||||
struct fs_uart_platform_info *pinfo;
|
||||
|
||||
struct platform_device* pdev = NULL;
|
||||
if(index) { /*assume SMC2 here*/
|
||||
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
|
||||
pinfo = &mpc885_uart_pdata[1];
|
||||
} else { /*over SMC1*/
|
||||
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
|
||||
pinfo = &mpc885_uart_pdata[0];
|
||||
}
|
||||
|
||||
pinfo->uart_clk = bd->bi_intfreq;
|
||||
pdev->dev.platform_data = pinfo;
|
||||
ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -141,16 +141,6 @@ m8xx_setup_arch(void)
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
|
||||
#if defined(CONFIG_MTD_PHYSMAP)
|
||||
physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
|
||||
MPC8xxADS_BANK_WIDTH, NULL);
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
|
||||
#endif /* CONFIG_MTD_PARTITIONS */
|
||||
#endif /* CONFIG_MTD_PHYSMAP */
|
||||
#endif
|
||||
|
||||
board_init();
|
||||
|
||||
@@ -63,10 +63,6 @@
|
||||
#include <platforms/lantec.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC885ADS)
|
||||
#include <platforms/mpc885ads.h>
|
||||
#endif
|
||||
|
||||
/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
|
||||
* use the same memory map.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user