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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull part one of ARM SoC updates from Olof Johansson:
"A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support
for big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation
and moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as
most of the other v7 platforms in the tree. \o/
The work isn't quite complete, there's some driver fixes still
needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
plus a large set of various smaller updates for different platforms.
I'm probably missing some important one here"
* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
ARM: exynos: don't run exynos4 l2x0 setup on other platforms
ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
ARM: EXYNOS: mcpm rename the power_down_finish
ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
ARM: EXYNOS: Enable multi-platform build support
ARM: EXYNOS: Consolidate Kconfig entries
ARM: EXYNOS: Add support for EXYNOS5410 SoC
ARM: EXYNOS: Support secondary CPU boot of Exynos3250
ARM: EXYNOS: Add Exynos3250 SoC ID
ARM: EXYNOS: Add 5800 SoC support
ARM: EXYNOS: initial board support for exynos5260 SoC
clk: exynos5410: register clocks using common clock framework
ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
ARM: sunxi: allow building without reset controller
Documentation: devicetree: arm: sort enable-method entries
ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
...
This commit is contained in:
Linus Torvalds
@@ -234,6 +234,11 @@ Berlin family (Digital Entertainment)
|
||||
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
|
||||
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
|
||||
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
|
||||
88DE3114, Armada 1500 Pro
|
||||
Design name: BG2-Q
|
||||
Core: Quad Core ARM Cortex-A9, PL310 L2CC
|
||||
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-pro/
|
||||
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500-pro/assets/Marvell_ARMADA_1500_PRO-01_product_brief.pdf
|
||||
88DE????
|
||||
Design name: BG3
|
||||
Core: ARM Cortex-A15, CA15 integrated L2CC
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||||
|
||||
@@ -0,0 +1,18 @@
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STiH407 Overview
|
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================
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
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The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes
|
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and server/connected client application for satellite, cable, terrestrial
|
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and IP-STB markets.
|
||||
|
||||
Features
|
||||
- ARM Cortex-A9 1.5 GHz dual core CPU (28nm)
|
||||
- SATA2, USB 3.0, PCIe, Gbit Ethernet
|
||||
|
||||
Document Author
|
||||
---------------
|
||||
|
||||
Maxime Coquelin <maxime.coquelin@st.com>, (c) 2014 ST Microelectronics
|
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@@ -1,20 +1,21 @@
|
||||
Power Management Service Unit(PMSU)
|
||||
-----------------------------------
|
||||
Available on Marvell SOCs: Armada 370 and Armada XP
|
||||
Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-370-xp-pmsu"
|
||||
- compatible: should be one of:
|
||||
- "marvell,armada-370-pmsu" for Armada 370 or Armada XP
|
||||
- "marvell,armada-380-pmsu" for Armada 38x
|
||||
- "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now
|
||||
deprecated and will be removed
|
||||
|
||||
- reg: Should contain PMSU registers location and length. First pair
|
||||
for the per-CPU SW Reset Control registers, second pair for the
|
||||
Power Management Service Unit.
|
||||
- reg: Should contain PMSU registers location and length.
|
||||
|
||||
Example:
|
||||
|
||||
armada-370-xp-pmsu@d0022000 {
|
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compatible = "marvell,armada-370-xp-pmsu";
|
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reg = <0xd0022100 0x430>,
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<0xd0020800 0x20>;
|
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armada-370-xp-pmsu@22000 {
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compatible = "marvell,armada-370-pmsu";
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reg = <0x22000 0x1000>;
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||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,14 @@
|
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Marvell Armada CPU reset controller
|
||||
===================================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,armada-370-cpu-reset".
|
||||
|
||||
- reg: should be register base and length as documented in the
|
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datasheet for the CPU reset registers
|
||||
|
||||
cpurst: cpurst@20800 {
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||||
compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x20>;
|
||||
};
|
||||
@@ -0,0 +1,12 @@
|
||||
Axxia AXM55xx device tree bindings
|
||||
|
||||
Boards using the AXM55xx SoC need to have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
- compatible = "lsi,axm5516"
|
||||
|
||||
Boards:
|
||||
|
||||
LSI AXM5516 Validation board (Amarillo)
|
||||
compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
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||||
@@ -1,16 +1,33 @@
|
||||
Coherency fabric
|
||||
----------------
|
||||
Available on Marvell SOCs: Armada 370 and Armada XP
|
||||
Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,coherency-fabric"
|
||||
- compatible: the possible values are:
|
||||
|
||||
* "marvell,coherency-fabric", to be used for the coherency fabric of
|
||||
the Armada 370 and Armada XP.
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||||
|
||||
* "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
|
||||
fabric.
|
||||
|
||||
* "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
|
||||
fabric.
|
||||
|
||||
- reg: Should contain coherency fabric registers location and
|
||||
length. First pair for the coherency fabric registers, second pair
|
||||
for the per-CPU fabric registers registers.
|
||||
length.
|
||||
|
||||
Example:
|
||||
* For "marvell,coherency-fabric", the first pair for the coherency
|
||||
fabric registers, second pair for the per-CPU fabric registers.
|
||||
|
||||
* For "marvell,armada-375-coherency-fabric", only one pair is needed
|
||||
for the per-CPU fabric registers.
|
||||
|
||||
* For "marvell,armada-380-coherency-fabric", only one pair is needed
|
||||
for the per-CPU fabric registers.
|
||||
|
||||
Examples:
|
||||
|
||||
coherency-fabric@d0020200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
@@ -19,3 +36,8 @@ coherency-fabric@d0020200 {
|
||||
|
||||
};
|
||||
|
||||
coherency-fabric@21810 {
|
||||
compatible = "marvell,armada-375-coherency-fabric";
|
||||
reg = <0x21810 0x1c>;
|
||||
};
|
||||
|
||||
|
||||
@@ -178,13 +178,19 @@ nodes to be present and contain the properties described below.
|
||||
Usage and definition depend on ARM architecture version.
|
||||
# On ARM v8 64-bit this property is required and must
|
||||
be one of:
|
||||
"spin-table"
|
||||
"psci"
|
||||
"spin-table"
|
||||
# On ARM 32-bit systems this property is optional and
|
||||
can be one of:
|
||||
"allwinner,sun6i-a31"
|
||||
"arm,psci"
|
||||
"marvell,armada-375-smp"
|
||||
"marvell,armada-380-smp"
|
||||
"marvell,armada-xp-smp"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
"rockchip,rk3066-smp"
|
||||
|
||||
- cpu-release-addr
|
||||
Usage: required for systems that have an "enable-method"
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
Samsung Exynos SYSRAM for SMP bringup:
|
||||
------------------------------------
|
||||
|
||||
Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
|
||||
of the secondary cores. Once the core gets powered up it executes the
|
||||
code that is residing at some specific location of the SYSRAM.
|
||||
|
||||
Therefore reserved section sub-nodes have to be added to the mmio-sram
|
||||
declaration. These nodes are of two types depending upon secure or
|
||||
non-secure execution environment.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : depending upon boot mode, should be
|
||||
"samsung,exynos4210-sysram" : for Secure SYSRAM
|
||||
"samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sysram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sysram@02020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02020000 0x54000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x02020000 0x54000>;
|
||||
|
||||
smp-sysram@0 {
|
||||
compatible = "samsung,exynos4210-sysram";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
smp-sysram@53000 {
|
||||
compatible = "samsung,exynos4210-sysram-ns";
|
||||
reg = <0x53000 0x1000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,15 @@
|
||||
ST STi Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the ST STiH415 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih415";
|
||||
|
||||
Boards with the ST STiH416 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih416";
|
||||
|
||||
Boards with the ST STiH407 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih407";
|
||||
|
||||
@@ -6,6 +6,16 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
This node contains the slow clock definitions.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-osc":
|
||||
at91 slow oscillator
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-rc-osc":
|
||||
at91 internal slow RC oscillator
|
||||
|
||||
"atmel,at91rm9200-pmc" or
|
||||
"atmel,at91sam9g45-pmc" or
|
||||
"atmel,at91sam9n12-pmc" or
|
||||
@@ -15,8 +25,18 @@ Required properties:
|
||||
All at91 specific clocks (clocks defined below) must be child
|
||||
node of the PMC node.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow" (under sckc node)
|
||||
or
|
||||
"atmel,at91sam9260-clk-slow" (under pmc node):
|
||||
at91 slow clk
|
||||
|
||||
"atmel,at91rm9200-clk-main-osc"
|
||||
"atmel,at91sam9x5-clk-main-rc-osc"
|
||||
at91 main clk sources
|
||||
|
||||
"atmel,at91sam9x5-clk-main"
|
||||
"atmel,at91rm9200-clk-main":
|
||||
at91 main oscillator
|
||||
at91 main clock
|
||||
|
||||
"atmel,at91rm9200-clk-master" or
|
||||
"atmel,at91sam9x5-clk-master":
|
||||
@@ -54,6 +74,63 @@ Required properties:
|
||||
"atmel,at91sam9x5-clk-utmi":
|
||||
at91 utmi clock
|
||||
|
||||
Required properties for SCKC node:
|
||||
- reg : defines the IO memory reserved for the SCKC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
|
||||
|
||||
For example:
|
||||
sckc: sckc@fffffe50 {
|
||||
compatible = "atmel,sama5d3-pmc";
|
||||
reg = <0xfffffe50 0x4>
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
/* put at91 slow clocks here */
|
||||
};
|
||||
|
||||
|
||||
Required properties for internal slow RC oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for slow oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91rm9200-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_xtal>;
|
||||
};
|
||||
|
||||
Required properties for slow clock:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the slow clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
clk32k: slck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
|
||||
Required properties for PMC node:
|
||||
- reg : defines the IO memory reserved for the PMC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
@@ -85,24 +162,57 @@ For example:
|
||||
/* put at91 clocks here */
|
||||
};
|
||||
|
||||
Required properties for main clock internal RC oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
main_rc_osc: main_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for main clock oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
|
||||
on XIN.
|
||||
|
||||
clock signal is directly provided on XIN pin.
|
||||
|
||||
For example:
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
Required properties for main clock:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks (optional if clock-frequency is provided) : shall be the slow clock
|
||||
phandle. This clock is used to calculate the main clock rate if
|
||||
"clock-frequency" is not provided.
|
||||
- clock-frequency : the main oscillator frequency.Prefer the use of
|
||||
"clock-frequency" over automatic clock rate calculation.
|
||||
- clocks : shall encode the main clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
compatible = "atmel,at91sam9x5-clk-main";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&ck32k>;
|
||||
clock-frequency = <18432000>;
|
||||
clocks = <&main_rc_osc &main_osc>;
|
||||
};
|
||||
|
||||
Required properties for master clock:
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
* Samsung Exynos3250 Clock Controller
|
||||
|
||||
The Exynos3250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos3250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos3250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
cmu: clock-controller@10030000 {
|
||||
compatible = "samsung,exynos3250-cmu";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13800000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
@@ -0,0 +1,190 @@
|
||||
* Samsung Exynos5260 Clock Controller
|
||||
|
||||
Exynos5260 has 13 clock controllers which are instantiated
|
||||
independently from the device-tree. These clock controllers
|
||||
generate and supply clocks to various hardware blocks within
|
||||
the SoC.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use
|
||||
this identifier to specify the clock which they consume. All
|
||||
available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5260-clk.h header and can be used in
|
||||
device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It
|
||||
is expected that they are defined using standard clock bindings
|
||||
with following clock-output-names:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
- "xrtcxti" - input clock from XRTCXTI
|
||||
- "ioclk_pcm_extclk" - pcm external operation clock
|
||||
- "ioclk_spdif_extclk" - spdif external operation clock
|
||||
- "ioclk_i2s_cdclk" - i2s0 codec clock
|
||||
|
||||
Phy clocks:
|
||||
|
||||
There are several clocks which are generated by specific PHYs.
|
||||
These clocks are fed into the clock controller and then routed to
|
||||
the hardware blocks. These clocks are defined as fixed clocks in the
|
||||
driver with following names:
|
||||
|
||||
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
|
||||
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
|
||||
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
|
||||
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
|
||||
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
|
||||
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
|
||||
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
|
||||
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
|
||||
- "phyclk_dptx_phy_clk_div2"
|
||||
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
|
||||
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
|
||||
- "phyclk_usbhost20_phy_freeclk"
|
||||
- "phyclk_usbhost20_phy_clk48mohci"
|
||||
- "phyclk_usbdrd30_udrd30_pipe_pclk"
|
||||
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
|
||||
|
||||
Required Properties for Clock Controller:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
1) "samsung,exynos5260-clock-top"
|
||||
2) "samsung,exynos5260-clock-peri"
|
||||
3) "samsung,exynos5260-clock-egl"
|
||||
4) "samsung,exynos5260-clock-kfc"
|
||||
5) "samsung,exynos5260-clock-g2d"
|
||||
6) "samsung,exynos5260-clock-mif"
|
||||
7) "samsung,exynos5260-clock-mfc"
|
||||
8) "samsung,exynos5260-clock-g3d"
|
||||
9) "samsung,exynos5260-clock-fsys"
|
||||
10) "samsung,exynos5260-clock-aud"
|
||||
11) "samsung,exynos5260-clock-isp"
|
||||
12) "samsung,exynos5260-clock-gscl"
|
||||
13) "samsung,exynos5260-clock-disp"
|
||||
|
||||
- reg: physical base address of the controller and the length of
|
||||
memory mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of clock identifiers which are fed as the input to
|
||||
the given clock controller. Please refer the next section to find
|
||||
the input clocks for a given controller.
|
||||
|
||||
- clock-names: list of names of clocks which are fed as the input
|
||||
to the given clock controller.
|
||||
|
||||
Input clocks for top clock controller:
|
||||
- fin_pll
|
||||
- dout_mem_pll
|
||||
- dout_bus_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for peri clock controller:
|
||||
- fin_pll
|
||||
- ioclk_pcm_extclk
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_spdif_extclk
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- dout_aclk_peri_66
|
||||
- dout_sclk_peri_uart0
|
||||
- dout_sclk_peri_uart1
|
||||
- dout_sclk_peri_uart2
|
||||
- dout_sclk_peri_spi0_b
|
||||
- dout_sclk_peri_spi1_b
|
||||
- dout_sclk_peri_spi2_b
|
||||
- dout_aclk_peri_aud
|
||||
- dout_sclk_peri_spi0_b
|
||||
|
||||
Input clocks for egl clock controller:
|
||||
- fin_pll
|
||||
- dout_bus_pll
|
||||
|
||||
Input clocks for kfc clock controller:
|
||||
- fin_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for g2d clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_g2d_333
|
||||
|
||||
Input clocks for mif clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for mfc clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_mfc_333
|
||||
|
||||
Input clocks for g3d clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for fsys clock controller:
|
||||
- fin_pll
|
||||
- phyclk_usbhost20_phy_phyclock
|
||||
- phyclk_usbhost20_phy_freeclk
|
||||
- phyclk_usbhost20_phy_clk48mohci
|
||||
- phyclk_usbdrd30_udrd30_pipe_pclk
|
||||
- phyclk_usbdrd30_udrd30_phyclock
|
||||
- dout_aclk_fsys_200
|
||||
|
||||
Input clocks for aud clock controller:
|
||||
- fin_pll
|
||||
- fout_aud_pll
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_pcm_extclk
|
||||
|
||||
Input clocks for isp clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_isp1_266
|
||||
- dout_aclk_isp1_400
|
||||
- mout_aclk_isp1_266
|
||||
|
||||
Input clocks for gscl clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_gscl_400
|
||||
- dout_aclk_gscl_333
|
||||
|
||||
Input clocks for disp clock controller:
|
||||
- fin_pll
|
||||
- phyclk_dptx_phy_ch3_txd_clk
|
||||
- phyclk_dptx_phy_ch2_txd_clk
|
||||
- phyclk_dptx_phy_ch1_txd_clk
|
||||
- phyclk_dptx_phy_ch0_txd_clk
|
||||
- phyclk_hdmi_phy_tmds_clko
|
||||
- phyclk_hdmi_phy_ref_clko
|
||||
- phyclk_hdmi_phy_pixel_clko
|
||||
- phyclk_hdmi_link_o_tmds_clkhi
|
||||
- phyclk_mipi_dphy_4l_m_txbyte_clkhs
|
||||
- phyclk_dptx_phy_o_ref_clk_24m
|
||||
- phyclk_dptx_phy_clk_div2
|
||||
- phyclk_mipi_dphy_4l_m_rxclkesc0
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- ioclk_spdif_extclk
|
||||
- dout_aclk_peri_aud
|
||||
- dout_aclk_disp_222
|
||||
- dout_sclk_disp_pixel
|
||||
- dout_aclk_disp_333
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock_mfc: clock-controller@11090000 {
|
||||
compatible = "samsung,exynos5260-clock-mfc";
|
||||
clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
|
||||
clock-names = "fin_pll", "dout_aclk_mfc_333";
|
||||
reg = <0x11090000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the
|
||||
peri clock controller. Refer to the standard clock bindings for
|
||||
information about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 146 0>;
|
||||
clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
* Samsung Exynos5410 Clock Controller
|
||||
|
||||
The Exynos5410 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5410 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,exynos5410-clock"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clock:
|
||||
|
||||
There is clock that is generated outside the SoC. It
|
||||
is expected that it is defined using standard clock bindings
|
||||
with following clock-output-name:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5410-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
@@ -1,12 +1,13 @@
|
||||
* Samsung Exynos5420 Clock Controller
|
||||
|
||||
The Exynos5420 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5420 SoC.
|
||||
controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
|
||||
- "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
@@ -139,6 +139,9 @@ clocks and IDs.
|
||||
uart5_ipg 124
|
||||
reserved 125
|
||||
wdt_ipg 126
|
||||
cko_div 127
|
||||
cko_sel 128
|
||||
cko 129
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@@ -98,7 +98,12 @@ clocks and IDs.
|
||||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
spll_gate 86
|
||||
mshc_div 87
|
||||
rtic_ipg_gate 88
|
||||
mshc_ipg_gate 89
|
||||
rtic_ahb_gate 90
|
||||
mshc_baud_gate 91
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@@ -220,6 +220,7 @@ clocks and IDs.
|
||||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
esai_ahb 208
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
* Clock bindings for Freescale i.MX6 SoloX
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sx-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
|
||||
for the full list of i.MX6 SoloX clock IDs.
|
||||
@@ -19,7 +19,7 @@ to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/samsung,s3c2410-clock.h header and can be used in device
|
||||
dt-bindings/clock/s3c2410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
Axxia Restart Driver
|
||||
|
||||
This driver can do reset of the Axxia SoC. It uses the registers in the syscon
|
||||
block to initiate a chip reset.
|
||||
|
||||
Required Properties:
|
||||
-compatible: "lsi,axm55xx-reset"
|
||||
-syscon: phandle to the syscon node.
|
||||
|
||||
Example:
|
||||
|
||||
syscon: syscon@2010030000 {
|
||||
compatible = "lsi,axxia-syscon", "syscon";
|
||||
reg = <0x20 0x10030000 0 0x2000>;
|
||||
};
|
||||
|
||||
reset: reset@2010031000 {
|
||||
compatible = "lsi,axm55xx-reset";
|
||||
syscon = <&syscon>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user