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Staging: Add octeon-ethernet driver files.

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The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui
ports present on the Cavium OCTEON family of SOCs.  These SOCs are
multi-core mips64 processors with existing support over in arch/mips.

The driver files can be categorized into three basic groups:

1) Register definitions, these are named cvmx-*-defs.h

2) Main driver code, these have names that don't start cvmx-.

3) Interface specific functions and other utility code, names starting
with cvmx-

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
2009-05-05 17:35:21 -07:00
committed by Ralf Baechle
parent 38295fb2a0
commit 80ff0fd3ab
76 changed files with 26149 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/staging/Kconfig
+2
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@@ -117,5 +117,7 @@ source "drivers/staging/serqt_usb/Kconfig"
source "drivers/gpu/drm/radeon/Kconfig"
source "drivers/staging/octeon/Kconfig"
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING
drivers/staging/Makefile
+1
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@@ -40,3 +40,4 @@ obj-$(CONFIG_PLAN9AUTH) += p9auth/
obj-$(CONFIG_HECI) += heci/
obj-$(CONFIG_LINE6_USB) += line6/
obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/
drivers/staging/octeon/Kconfig
+12
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@@ -0,0 +1,12 @@
config OCTEON_ETHERNET
tristate "Cavium Networks Octeon Ethernet support"
depends on CPU_CAVIUM_OCTEON
select MII
help
This driver supports the builtin ethernet ports on Cavium
Networks' products in the Octeon family. This driver supports the
CN3XXX and CN5XXX Octeon processors.
To compile this driver as a module, choose M here. The module
will be called octeon-ethernet.
drivers/staging/octeon/Makefile
+30
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@@ -0,0 +1,30 @@
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 2005-2009 Cavium Networks
#
#
# Makefile for Cavium OCTEON on-board ethernet driver
#
obj-${CONFIG_OCTEON_ETHERNET} := octeon-ethernet.o
octeon-ethernet-objs := ethernet.o
octeon-ethernet-objs += ethernet-common.o
octeon-ethernet-objs += ethernet-mdio.o
octeon-ethernet-objs += ethernet-mem.o
octeon-ethernet-objs += ethernet-proc.o
octeon-ethernet-objs += ethernet-rgmii.o
octeon-ethernet-objs += ethernet-rx.o
octeon-ethernet-objs += ethernet-sgmii.o
octeon-ethernet-objs += ethernet-spi.o
octeon-ethernet-objs += ethernet-tx.o
octeon-ethernet-objs += ethernet-xaui.o
octeon-ethernet-objs += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
drivers/staging/octeon/cvmx-address.h
+274
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@@ -0,0 +1,274 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2009 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* Typedefs and defines for working with Octeon physical addresses.
*
*/
#ifndef __CVMX_ADDRESS_H__
#define __CVMX_ADDRESS_H__
#if 0
typedef enum {
CVMX_MIPS_SPACE_XKSEG = 3LL,
CVMX_MIPS_SPACE_XKPHYS = 2LL,
CVMX_MIPS_SPACE_XSSEG = 1LL,
CVMX_MIPS_SPACE_XUSEG = 0LL
} cvmx_mips_space_t;
#endif
typedef enum {
CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
} cvmx_mips_xkseg_space_t;
/* decodes <14:13> of a kseg3 window address */
typedef enum {
CVMX_ADD_WIN_SCR = 0L,
/* see cvmx_add_win_dma_dec_t for further decode */
CVMX_ADD_WIN_DMA = 1L,
CVMX_ADD_WIN_UNUSED = 2L,
CVMX_ADD_WIN_UNUSED2 = 3L
} cvmx_add_win_dec_t;
/* decode within DMA space */
typedef enum {
/*
* Add store data to the write buffer entry, allocating it if
* necessary.
*/
CVMX_ADD_WIN_DMA_ADD = 0L,
/* send out the write buffer entry to DRAM */
CVMX_ADD_WIN_DMA_SENDMEM = 1L,
/* store data must be normal DRAM memory space address in this case */
/* send out the write buffer entry as an IOBDMA command */
CVMX_ADD_WIN_DMA_SENDDMA = 2L,
/* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
/* send out the write buffer entry as an IO write */
CVMX_ADD_WIN_DMA_SENDIO = 3L,
/* store data must be normal IO space address in this case */
/* send out a single-tick command on the NCB bus */
CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
/* no write buffer data needed/used */
} cvmx_add_win_dma_dec_t;
/*
* Physical Address Decode
*
* Octeon-I HW never interprets this X (<39:36> reserved
* for future expansion), software should set to 0.
*
* - 0x0 XXX0 0000 0000 to DRAM Cached
* - 0x0 XXX0 0FFF FFFF
*
* - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
* - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
*
* - 0x0 XXX0 2000 0000 to DRAM Cached
* - 0x0 XXXF FFFF FFFF
*
* - 0x1 00X0 0000 0000 to Boot Bus Uncached
* - 0x1 00XF FFFF FFFF
*
* - 0x1 01X0 0000 0000 to Other NCB Uncached
* - 0x1 FFXF FFFF FFFF devices
*
* Decode of all Octeon addresses
*/
typedef union {
uint64_t u64;
/* mapped or unmapped virtual address */
struct {
uint64_t R:2;
uint64_t offset:62;
} sva;
/* mapped USEG virtual addresses (typically) */
struct {
uint64_t zeroes:33;
uint64_t offset:31;
} suseg;
/* mapped or unmapped virtual address */
struct {
uint64_t ones:33;
uint64_t sp:2;
uint64_t offset:29;
} sxkseg;
/*
* physical address accessed through xkphys unmapped virtual
* address.
*/
struct {
uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
uint64_t cca:3; /* ignored by octeon */
uint64_t mbz:10;
uint64_t pa:49; /* physical address */
} sxkphys;
/* physical address */
struct {
uint64_t mbz:15;
/* if set, the address is uncached and resides on MCB bus */
uint64_t is_io:1;
/*
* the hardware ignores this field when is_io==0, else
* device ID.
*/
uint64_t did:8;
/* the hardware ignores <39:36> in Octeon I */
uint64_t unaddr:4;
uint64_t offset:36;
} sphys;
/* physical mem address */
struct {
/* techically, <47:40> are dont-cares */
uint64_t zeroes:24;
/* the hardware ignores <39:36> in Octeon I */
uint64_t unaddr:4;
uint64_t offset:36;
} smem;
/* physical IO address */
struct {
uint64_t mem_region:2;
uint64_t mbz:13;
/* 1 in this case */
uint64_t is_io:1;
/*
* The hardware ignores this field when is_io==0, else
* device ID.
*/
uint64_t did:8;
/* the hardware ignores <39:36> in Octeon I */
uint64_t unaddr:4;
uint64_t offset:36;
} sio;
/*
* Scratchpad virtual address - accessed through a window at
* the end of kseg3
*/
struct {
uint64_t ones:49;
/* CVMX_ADD_WIN_SCR (0) in this case */
cvmx_add_win_dec_t csrdec:2;
uint64_t addr:13;
} sscr;
/* there should only be stores to IOBDMA space, no loads */
/*
* IOBDMA virtual address - accessed through a window at the
* end of kseg3
*/
struct {
uint64_t ones:49;
uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */
uint64_t unused2:3;
uint64_t type:3;
uint64_t addr:7;
} sdma;
struct {
uint64_t didspace:24;
uint64_t unused:40;
} sfilldidspace;
} cvmx_addr_t;
/* These macros for used by 32 bit applications */
#define CVMX_MIPS32_SPACE_KSEG0 1l
#define CVMX_ADD_SEG32(segment, add) \
(((int32_t)segment << 31) | (int32_t)(add))
/*
* Currently all IOs are performed using XKPHYS addressing. Linux uses
* the CvmMemCtl register to enable XKPHYS addressing to IO space from
* user mode. Future OSes may need to change the upper bits of IO
* addresses. The following define controls the upper two bits for all
* IO addresses generated by the simple executive library.
*/
#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
/* These macros simplify the process of creating common IO addresses */
#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
#ifndef CVMX_ADD_IO_SEG
#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
#endif
#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
/* from include/ncb_rsl_id.v */
#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
#define CVMX_OCT_DID_GMX0 1ULL
#define CVMX_OCT_DID_GMX1 2ULL
#define CVMX_OCT_DID_PCI 3ULL
#define CVMX_OCT_DID_KEY 4ULL
#define CVMX_OCT_DID_FPA 5ULL
#define CVMX_OCT_DID_DFA 6ULL
#define CVMX_OCT_DID_ZIP 7ULL
#define CVMX_OCT_DID_RNG 8ULL
#define CVMX_OCT_DID_IPD 9ULL
#define CVMX_OCT_DID_PKT 10ULL
#define CVMX_OCT_DID_TIM 11ULL
#define CVMX_OCT_DID_TAG 12ULL
/* the rest are not on the IO bus */
#define CVMX_OCT_DID_L2C 16ULL
#define CVMX_OCT_DID_LMC 17ULL
#define CVMX_OCT_DID_SPX0 18ULL
#define CVMX_OCT_DID_SPX1 19ULL
#define CVMX_OCT_DID_PIP 20ULL
#define CVMX_OCT_DID_ASX0 22ULL
#define CVMX_OCT_DID_ASX1 23ULL
#define CVMX_OCT_DID_IOB 30ULL
#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
#endif /* __CVMX_ADDRESS_H__ */
drivers/staging/octeon/cvmx-asxx-defs.h
+475
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@@ -0,0 +1,475 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_ASXX_DEFS_H__
#define __CVMX_ASXX_DEFS_H__
#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_INT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_INT_REG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
#define CVMX_ASXX_PRT_LOOP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_BYPASS(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_COMP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RLD_SETTING(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_PRT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_MSK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_RX_WOL_SIG(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_COMP_BYP(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
#define CVMX_ASXX_TX_PRT_EN(block_id) \
CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
union cvmx_asxx_gmii_rx_clk_set {
uint64_t u64;
struct cvmx_asxx_gmii_rx_clk_set_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
};
union cvmx_asxx_gmii_rx_dat_set {
uint64_t u64;
struct cvmx_asxx_gmii_rx_dat_set_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
};
union cvmx_asxx_int_en {
uint64_t u64;
struct cvmx_asxx_int_en_s {
uint64_t reserved_12_63:52;
uint64_t txpsh:4;
uint64_t txpop:4;
uint64_t ovrflw:4;
} s;
struct cvmx_asxx_int_en_cn30xx {
uint64_t reserved_11_63:53;
uint64_t txpsh:3;
uint64_t reserved_7_7:1;
uint64_t txpop:3;
uint64_t reserved_3_3:1;
uint64_t ovrflw:3;
} cn30xx;
struct cvmx_asxx_int_en_cn30xx cn31xx;
struct cvmx_asxx_int_en_s cn38xx;
struct cvmx_asxx_int_en_s cn38xxp2;
struct cvmx_asxx_int_en_cn30xx cn50xx;
struct cvmx_asxx_int_en_s cn58xx;
struct cvmx_asxx_int_en_s cn58xxp1;
};
union cvmx_asxx_int_reg {
uint64_t u64;
struct cvmx_asxx_int_reg_s {
uint64_t reserved_12_63:52;
uint64_t txpsh:4;
uint64_t txpop:4;
uint64_t ovrflw:4;
} s;
struct cvmx_asxx_int_reg_cn30xx {
uint64_t reserved_11_63:53;
uint64_t txpsh:3;
uint64_t reserved_7_7:1;
uint64_t txpop:3;
uint64_t reserved_3_3:1;
uint64_t ovrflw:3;
} cn30xx;
struct cvmx_asxx_int_reg_cn30xx cn31xx;
struct cvmx_asxx_int_reg_s cn38xx;
struct cvmx_asxx_int_reg_s cn38xxp2;
struct cvmx_asxx_int_reg_cn30xx cn50xx;
struct cvmx_asxx_int_reg_s cn58xx;
struct cvmx_asxx_int_reg_s cn58xxp1;
};
union cvmx_asxx_mii_rx_dat_set {
uint64_t u64;
struct cvmx_asxx_mii_rx_dat_set_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
};
union cvmx_asxx_prt_loop {
uint64_t u64;
struct cvmx_asxx_prt_loop_s {
uint64_t reserved_8_63:56;
uint64_t ext_loop:4;
uint64_t int_loop:4;
} s;
struct cvmx_asxx_prt_loop_cn30xx {
uint64_t reserved_7_63:57;
uint64_t ext_loop:3;
uint64_t reserved_3_3:1;
uint64_t int_loop:3;
} cn30xx;
struct cvmx_asxx_prt_loop_cn30xx cn31xx;
struct cvmx_asxx_prt_loop_s cn38xx;
struct cvmx_asxx_prt_loop_s cn38xxp2;
struct cvmx_asxx_prt_loop_cn30xx cn50xx;
struct cvmx_asxx_prt_loop_s cn58xx;
struct cvmx_asxx_prt_loop_s cn58xxp1;
};
union cvmx_asxx_rld_bypass {
uint64_t u64;
struct cvmx_asxx_rld_bypass_s {
uint64_t reserved_1_63:63;
uint64_t bypass:1;
} s;
struct cvmx_asxx_rld_bypass_s cn38xx;
struct cvmx_asxx_rld_bypass_s cn38xxp2;
struct cvmx_asxx_rld_bypass_s cn58xx;
struct cvmx_asxx_rld_bypass_s cn58xxp1;
};
union cvmx_asxx_rld_bypass_setting {
uint64_t u64;
struct cvmx_asxx_rld_bypass_setting_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_rld_bypass_setting_s cn38xx;
struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
struct cvmx_asxx_rld_bypass_setting_s cn58xx;
struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
};
union cvmx_asxx_rld_comp {
uint64_t u64;
struct cvmx_asxx_rld_comp_s {
uint64_t reserved_9_63:55;
uint64_t pctl:5;
uint64_t nctl:4;
} s;
struct cvmx_asxx_rld_comp_cn38xx {
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
} cn38xx;
struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
struct cvmx_asxx_rld_comp_s cn58xx;
struct cvmx_asxx_rld_comp_s cn58xxp1;
};
union cvmx_asxx_rld_data_drv {
uint64_t u64;
struct cvmx_asxx_rld_data_drv_s {
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
} s;
struct cvmx_asxx_rld_data_drv_s cn38xx;
struct cvmx_asxx_rld_data_drv_s cn38xxp2;
struct cvmx_asxx_rld_data_drv_s cn58xx;
struct cvmx_asxx_rld_data_drv_s cn58xxp1;
};
union cvmx_asxx_rld_fcram_mode {
uint64_t u64;
struct cvmx_asxx_rld_fcram_mode_s {
uint64_t reserved_1_63:63;
uint64_t mode:1;
} s;
struct cvmx_asxx_rld_fcram_mode_s cn38xx;
struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
};
union cvmx_asxx_rld_nctl_strong {
uint64_t u64;
struct cvmx_asxx_rld_nctl_strong_s {
uint64_t reserved_5_63:59;
uint64_t nctl:5;
} s;
struct cvmx_asxx_rld_nctl_strong_s cn38xx;
struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
struct cvmx_asxx_rld_nctl_strong_s cn58xx;
struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
};
union cvmx_asxx_rld_nctl_weak {
uint64_t u64;
struct cvmx_asxx_rld_nctl_weak_s {
uint64_t reserved_5_63:59;
uint64_t nctl:5;
} s;
struct cvmx_asxx_rld_nctl_weak_s cn38xx;
struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
struct cvmx_asxx_rld_nctl_weak_s cn58xx;
struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
};
union cvmx_asxx_rld_pctl_strong {
uint64_t u64;
struct cvmx_asxx_rld_pctl_strong_s {
uint64_t reserved_5_63:59;
uint64_t pctl:5;
} s;
struct cvmx_asxx_rld_pctl_strong_s cn38xx;
struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
struct cvmx_asxx_rld_pctl_strong_s cn58xx;
struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
};
union cvmx_asxx_rld_pctl_weak {
uint64_t u64;
struct cvmx_asxx_rld_pctl_weak_s {
uint64_t reserved_5_63:59;
uint64_t pctl:5;
} s;
struct cvmx_asxx_rld_pctl_weak_s cn38xx;
struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
struct cvmx_asxx_rld_pctl_weak_s cn58xx;
struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
};
union cvmx_asxx_rld_setting {
uint64_t u64;
struct cvmx_asxx_rld_setting_s {
uint64_t reserved_13_63:51;
uint64_t dfaset:5;
uint64_t dfalag:1;
uint64_t dfalead:1;
uint64_t dfalock:1;
uint64_t setting:5;
} s;
struct cvmx_asxx_rld_setting_cn38xx {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} cn38xx;
struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
struct cvmx_asxx_rld_setting_s cn58xx;
struct cvmx_asxx_rld_setting_s cn58xxp1;
};
union cvmx_asxx_rx_clk_setx {
uint64_t u64;
struct cvmx_asxx_rx_clk_setx_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_rx_clk_setx_s cn30xx;
struct cvmx_asxx_rx_clk_setx_s cn31xx;
struct cvmx_asxx_rx_clk_setx_s cn38xx;
struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
struct cvmx_asxx_rx_clk_setx_s cn50xx;
struct cvmx_asxx_rx_clk_setx_s cn58xx;
struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
};
union cvmx_asxx_rx_prt_en {
uint64_t u64;
struct cvmx_asxx_rx_prt_en_s {
uint64_t reserved_4_63:60;
uint64_t prt_en:4;
} s;
struct cvmx_asxx_rx_prt_en_cn30xx {
uint64_t reserved_3_63:61;
uint64_t prt_en:3;
} cn30xx;
struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_rx_prt_en_s cn38xx;
struct cvmx_asxx_rx_prt_en_s cn38xxp2;
struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
struct cvmx_asxx_rx_prt_en_s cn58xx;
struct cvmx_asxx_rx_prt_en_s cn58xxp1;
};
union cvmx_asxx_rx_wol {
uint64_t u64;
struct cvmx_asxx_rx_wol_s {
uint64_t reserved_2_63:62;
uint64_t status:1;
uint64_t enable:1;
} s;
struct cvmx_asxx_rx_wol_s cn38xx;
struct cvmx_asxx_rx_wol_s cn38xxp2;
};
union cvmx_asxx_rx_wol_msk {
uint64_t u64;
struct cvmx_asxx_rx_wol_msk_s {
uint64_t msk:64;
} s;
struct cvmx_asxx_rx_wol_msk_s cn38xx;
struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
};
union cvmx_asxx_rx_wol_powok {
uint64_t u64;
struct cvmx_asxx_rx_wol_powok_s {
uint64_t reserved_1_63:63;
uint64_t powerok:1;
} s;
struct cvmx_asxx_rx_wol_powok_s cn38xx;
struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
};
union cvmx_asxx_rx_wol_sig {
uint64_t u64;
struct cvmx_asxx_rx_wol_sig_s {
uint64_t reserved_32_63:32;
uint64_t sig:32;
} s;
struct cvmx_asxx_rx_wol_sig_s cn38xx;
struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
};
union cvmx_asxx_tx_clk_setx {
uint64_t u64;
struct cvmx_asxx_tx_clk_setx_s {
uint64_t reserved_5_63:59;
uint64_t setting:5;
} s;
struct cvmx_asxx_tx_clk_setx_s cn30xx;
struct cvmx_asxx_tx_clk_setx_s cn31xx;
struct cvmx_asxx_tx_clk_setx_s cn38xx;
struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
struct cvmx_asxx_tx_clk_setx_s cn50xx;
struct cvmx_asxx_tx_clk_setx_s cn58xx;
struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
};
union cvmx_asxx_tx_comp_byp {
uint64_t u64;
struct cvmx_asxx_tx_comp_byp_s {
uint64_t reserved_0_63:64;
} s;
struct cvmx_asxx_tx_comp_byp_cn30xx {
uint64_t reserved_9_63:55;
uint64_t bypass:1;
uint64_t pctl:4;
uint64_t nctl:4;
} cn30xx;
struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
struct cvmx_asxx_tx_comp_byp_cn38xx {
uint64_t reserved_8_63:56;
uint64_t pctl:4;
uint64_t nctl:4;
} cn38xx;
struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
struct cvmx_asxx_tx_comp_byp_cn50xx {
uint64_t reserved_17_63:47;
uint64_t bypass:1;
uint64_t reserved_13_15:3;
uint64_t pctl:5;
uint64_t reserved_5_7:3;
uint64_t nctl:5;
} cn50xx;
struct cvmx_asxx_tx_comp_byp_cn58xx {
uint64_t reserved_13_63:51;
uint64_t pctl:5;
uint64_t reserved_5_7:3;
uint64_t nctl:5;
} cn58xx;
struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
};
union cvmx_asxx_tx_hi_waterx {
uint64_t u64;
struct cvmx_asxx_tx_hi_waterx_s {
uint64_t reserved_4_63:60;
uint64_t mark:4;
} s;
struct cvmx_asxx_tx_hi_waterx_cn30xx {
uint64_t reserved_3_63:61;
uint64_t mark:3;
} cn30xx;
struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
struct cvmx_asxx_tx_hi_waterx_s cn38xx;
struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
struct cvmx_asxx_tx_hi_waterx_s cn58xx;
struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
};
union cvmx_asxx_tx_prt_en {
uint64_t u64;
struct cvmx_asxx_tx_prt_en_s {
uint64_t reserved_4_63:60;
uint64_t prt_en:4;
} s;
struct cvmx_asxx_tx_prt_en_cn30xx {
uint64_t reserved_3_63:61;
uint64_t prt_en:3;
} cn30xx;
struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
struct cvmx_asxx_tx_prt_en_s cn38xx;
struct cvmx_asxx_tx_prt_en_s cn38xxp2;
struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
struct cvmx_asxx_tx_prt_en_s cn58xx;
struct cvmx_asxx_tx_prt_en_s cn58xxp1;
};
#endif
drivers/staging/octeon/cvmx-cmd-queue.c
+306
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@@ -0,0 +1,306 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* Support functions for managing command queues used for
* various hardware blocks.
*/
#include <linux/kernel.h>
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include "cvmx-fpa.h"
#include "cvmx-cmd-queue.h"
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include "cvmx-pko-defs.h"
/**
* This application uses this pointer to access the global queue
* state. It points to a bootmem named block.
*/
__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
/**
* Initialize the Global queue state pointer.
*
* Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
*/
static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
{
char *alloc_name = "cvmx_cmd_queues";
#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
extern uint64_t octeon_reserve32_memory;
#endif
if (likely(__cvmx_cmd_queue_state_ptr))
return CVMX_CMD_QUEUE_SUCCESS;
#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
if (octeon_reserve32_memory)
__cvmx_cmd_queue_state_ptr =
cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
octeon_reserve32_memory,
octeon_reserve32_memory +
(CONFIG_CAVIUM_RESERVE32 <<
20) - 1, 128, alloc_name);
else
#endif
__cvmx_cmd_queue_state_ptr =
cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr),
128,
alloc_name);
if (__cvmx_cmd_queue_state_ptr)
memset(__cvmx_cmd_queue_state_ptr, 0,
sizeof(*__cvmx_cmd_queue_state_ptr));
else {
struct cvmx_bootmem_named_block_desc *block_desc =
cvmx_bootmem_find_named_block(alloc_name);
if (block_desc)
__cvmx_cmd_queue_state_ptr =
cvmx_phys_to_ptr(block_desc->base_addr);
else {
cvmx_dprintf
("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n",
alloc_name);
return CVMX_CMD_QUEUE_NO_MEMORY;
}
}
return CVMX_CMD_QUEUE_SUCCESS;
}
/**
* Initialize a command queue for use. The initial FPA buffer is
* allocated and the hardware unit is configured to point to the
* new command queue.
*
* @queue_id: Hardware command queue to initialize.
* @max_depth: Maximum outstanding commands that can be queued.
* @fpa_pool: FPA pool the command queues should come from.
* @pool_size: Size of each buffer in the FPA pool (bytes)
*
* Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
*/
cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
int max_depth, int fpa_pool,
int pool_size)
{
__cvmx_cmd_queue_state_t *qstate;
cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr();
if (result != CVMX_CMD_QUEUE_SUCCESS)
return result;
qstate = __cvmx_cmd_queue_get_state(queue_id);
if (qstate == NULL)
return CVMX_CMD_QUEUE_INVALID_PARAM;
/*
* We artificially limit max_depth to 1<<20 words. It is an
* arbitrary limit.
*/
if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) {
if ((max_depth < 0) || (max_depth > 1 << 20))
return CVMX_CMD_QUEUE_INVALID_PARAM;
} else if (max_depth != 0)
return CVMX_CMD_QUEUE_INVALID_PARAM;
if ((fpa_pool < 0) || (fpa_pool > 7))
return CVMX_CMD_QUEUE_INVALID_PARAM;
if ((pool_size < 128) || (pool_size > 65536))
return CVMX_CMD_QUEUE_INVALID_PARAM;
/* See if someone else has already initialized the queue */
if (qstate->base_ptr_div128) {
if (max_depth != (int)qstate->max_depth) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
"Queue already initalized with different "
"max_depth (%d).\n",
(int)qstate->max_depth);
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
if (fpa_pool != qstate->fpa_pool) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
"Queue already initalized with different "
"FPA pool (%u).\n",
qstate->fpa_pool);
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
if ((pool_size >> 3) - 1 != qstate->pool_size_m1) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
"Queue already initalized with different "
"FPA pool size (%u).\n",
(qstate->pool_size_m1 + 1) << 3);
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
CVMX_SYNCWS;
return CVMX_CMD_QUEUE_ALREADY_SETUP;
} else {
union cvmx_fpa_ctl_status status;
void *buffer;
status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
if (!status.s.enb) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
"FPA is not enabled.\n");
return CVMX_CMD_QUEUE_NO_MEMORY;
}
buffer = cvmx_fpa_alloc(fpa_pool);
if (buffer == NULL) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
"Unable to allocate initial buffer.\n");
return CVMX_CMD_QUEUE_NO_MEMORY;
}
memset(qstate, 0, sizeof(*qstate));
qstate->max_depth = max_depth;
qstate->fpa_pool = fpa_pool;
qstate->pool_size_m1 = (pool_size >> 3) - 1;
qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128;
/*
* We zeroed the now serving field so we need to also
* zero the ticket.
*/
__cvmx_cmd_queue_state_ptr->
ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0;
CVMX_SYNCWS;
return CVMX_CMD_QUEUE_SUCCESS;
}
}
/**
* Shutdown a queue a free it's command buffers to the FPA. The
* hardware connected to the queue must be stopped before this
* function is called.
*
* @queue_id: Queue to shutdown
*
* Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
*/
cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id)
{
__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
if (qptr == NULL) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to "
"get queue information.\n");
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
if (cvmx_cmd_queue_length(queue_id) > 0) {
cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still "
"has data in it.\n");
return CVMX_CMD_QUEUE_FULL;
}
__cvmx_cmd_queue_lock(queue_id, qptr);
if (qptr->base_ptr_div128) {
cvmx_fpa_free(cvmx_phys_to_ptr
((uint64_t) qptr->base_ptr_div128 << 7),
qptr->fpa_pool, 0);
qptr->base_ptr_div128 = 0;
}
__cvmx_cmd_queue_unlock(qptr);
return CVMX_CMD_QUEUE_SUCCESS;
}
/**
* Return the number of command words pending in the queue. This
* function may be relatively slow for some hardware units.
*
* @queue_id: Hardware command queue to query
*
* Returns Number of outstanding commands
*/
int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
{
if (CVMX_ENABLE_PARAMETER_CHECKING) {
if (__cvmx_cmd_queue_get_state(queue_id) == NULL)
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
/*
* The cast is here so gcc with check that all values in the
* cvmx_cmd_queue_id_t enumeration are here.
*/
switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) {
case CVMX_CMD_QUEUE_PKO_BASE:
/*
* FIXME: Need atomic lock on
* CVMX_PKO_REG_READ_IDX. Right now we are normally
* called with the queue lock, so that is a SLIGHT
* amount of protection.
*/
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff);
if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
union cvmx_pko_mem_debug9 debug9;
debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
return debug9.cn38xx.doorbell;
} else {
union cvmx_pko_mem_debug8 debug8;
debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
return debug8.cn58xx.doorbell;
}
case CVMX_CMD_QUEUE_ZIP:
case CVMX_CMD_QUEUE_DFA:
case CVMX_CMD_QUEUE_RAID:
/* FIXME: Implement other lengths */
return 0;
case CVMX_CMD_QUEUE_DMA_BASE:
{
union cvmx_npei_dmax_counts dmax_counts;
dmax_counts.u64 =
cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS
(queue_id & 0x7));
return dmax_counts.s.dbell;
}
case CVMX_CMD_QUEUE_END:
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
return CVMX_CMD_QUEUE_INVALID_PARAM;
}
/**
* Return the command buffer to be written to. The purpose of this
* function is to allow CVMX routine access t othe low level buffer
* for initial hardware setup. User applications should not call this
* function directly.
*
* @queue_id: Command queue to query
*
* Returns Command buffer or NULL on failure
*/
void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id)
{
__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
if (qptr && qptr->base_ptr_div128)
return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7);
else
return NULL;
}
drivers/staging/octeon/cvmx-cmd-queue.h
+617
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File diff suppressed because it is too large Load Diff
drivers/staging/octeon/cvmx-config.h
+169
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@@ -0,0 +1,169 @@
#ifndef __CVMX_CONFIG_H__
#define __CVMX_CONFIG_H__
/************************* Config Specific Defines ************************/
#define CVMX_LLM_NUM_PORTS 1
#define CVMX_NULL_POINTER_PROTECT 1
#define CVMX_ENABLE_DEBUG_PRINTS 1
/* PKO queues per port for interface 0 (ports 0-15) */
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
/* PKO queues per port for interface 1 (ports 16-31) */
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
/* Limit on the number of PKO ports enabled for interface 0 */
#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
/* Limit on the number of PKO ports enabled for interface 1 */
#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
/* PKO queues per port for PCI (ports 32-35) */
#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
/* PKO queues per port for Loop devices (ports 36-39) */
#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
/************************* FPA allocation *********************************/
/* Pool sizes in bytes, must be multiple of a cache line */
#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
/* Pools in use */
/* Packet buffers */
#define CVMX_FPA_PACKET_POOL (0)
#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
/* Work queue entrys */
#define CVMX_FPA_WQE_POOL (1)
#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
/* PKO queue command buffers */
#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
/************************* FAU allocation ********************************/
/* The fetch and add registers are allocated here. They are arranged
* in order of descending size so that all alignment constraints are
* automatically met. The enums are linked so that the following enum
* continues allocating where the previous one left off, so the
* numbering within each enum always starts with zero. The macros
* take care of the address increment size, so the values entered
* always increase by 1. FAU registers are accessed with byte
* addresses.
*/
#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
typedef enum {
CVMX_FAU_REG_64_START = 0,
CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0),
} cvmx_fau_reg_64_t;
#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
typedef enum {
CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
} cvmx_fau_reg_32_t;
#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
typedef enum {
CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
} cvmx_fau_reg_16_t;
#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
typedef enum {
CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
} cvmx_fau_reg_8_t;
/*
* The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
* available FAU address that is not allocated in cvmx-config.h. This
* is 64 bit aligned.
*/
#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
#define CVMX_FAU_REG_END (2048)
/********************** scratch memory allocation *************************/
/* Scratchpad memory allocation. Note that these are byte memory
* addresses. Some uses of scratchpad (IOBDMA for example) require
* the use of 8-byte aligned addresses, so proper alignment needs to
* be taken into account.
*/
/* Generic scratch iobdma area */
#define CVMX_SCR_SCRATCH (0)
/* First location available after cvmx-config.h allocated region. */
#define CVMX_SCR_REG_AVAIL_BASE (8)
/*
* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
* before the beginning of the packet. If necessary, override the
* default here. See the IPD section of the hardware manual for MBUFF
* SKIP details.
*/
#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
/*
* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
* in each chained packet element. If necessary, override the default
* here.
*/
#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
/*
* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
* enabled for all input ports. This controls if IPD sends
* backpressure to all ports if Octeon's FPA pools don't have enough
* packet or work queue entries. Even when this is off, it is still
* possible to get backpressure from individual hardware ports. When
* configuring backpressure, also check
* CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
* the default here.
*/
#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
/*
* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
* function. Once it is enabled the hardware starts accepting
* packets. You might want to skip the IPD enable if configuration
* changes are need from the default helper setup. If necessary,
* override the default here.
*/
#define CVMX_HELPER_ENABLE_IPD 0
/*
* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
* to incoming packets.
*/
#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
#define CVMX_ENABLE_PARAMETER_CHECKING 0
/*
* The following select which fields are used by the PIP to generate
* the tag on INPUT
* 0: don't include
* 1: include
*/
#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
/* Select skip mode for input ports */
#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
/*
* Force backpressure to be disabled. This overrides all other
* backpressure configuration.
*/
#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
#endif /* __CVMX_CONFIG_H__ */
drivers/staging/octeon/cvmx-dbg-defs.h
+72
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/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_DBG_DEFS_H__
#define __CVMX_DBG_DEFS_H__
#define CVMX_DBG_DATA \
CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
union cvmx_dbg_data {
uint64_t u64;
struct cvmx_dbg_data_s {
uint64_t reserved_23_63:41;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
} s;
struct cvmx_dbg_data_cn30xx {
uint64_t reserved_31_63:33;
uint64_t pll_mul:3;
uint64_t reserved_23_27:5;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
} cn30xx;
struct cvmx_dbg_data_cn30xx cn31xx;
struct cvmx_dbg_data_cn38xx {
uint64_t reserved_29_63:35;
uint64_t d_mul:4;
uint64_t dclk_mul2:1;
uint64_t cclk_div2:1;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
} cn38xx;
struct cvmx_dbg_data_cn38xx cn38xxp2;
struct cvmx_dbg_data_cn30xx cn50xx;
struct cvmx_dbg_data_cn58xx {
uint64_t reserved_29_63:35;
uint64_t rem:6;
uint64_t c_mul:5;
uint64_t dsel_ext:1;
uint64_t data:17;
} cn58xx;
struct cvmx_dbg_data_cn58xx cn58xxp1;
};
#endif
drivers/staging/octeon/cvmx-fau.h
+597
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drivers/staging/octeon/cvmx-fpa-defs.h
+403
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@@ -0,0 +1,403 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_FPA_DEFS_H__
#define __CVMX_FPA_DEFS_H__
#define CVMX_FPA_BIST_STATUS \
CVMX_ADD_IO_SEG(0x00011800280000E8ull)
#define CVMX_FPA_CTL_STATUS \
CVMX_ADD_IO_SEG(0x0001180028000050ull)
#define CVMX_FPA_FPF0_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000000ull)
#define CVMX_FPA_FPF0_SIZE \
CVMX_ADD_IO_SEG(0x0001180028000058ull)
#define CVMX_FPA_FPF1_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000008ull)
#define CVMX_FPA_FPF2_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000010ull)
#define CVMX_FPA_FPF3_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000018ull)
#define CVMX_FPA_FPF4_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000020ull)
#define CVMX_FPA_FPF5_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000028ull)
#define CVMX_FPA_FPF6_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000030ull)
#define CVMX_FPA_FPF7_MARKS \
CVMX_ADD_IO_SEG(0x0001180028000038ull)
#define CVMX_FPA_FPFX_MARKS(offset) \
CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
#define CVMX_FPA_FPFX_SIZE(offset) \
CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
#define CVMX_FPA_INT_ENB \
CVMX_ADD_IO_SEG(0x0001180028000048ull)
#define CVMX_FPA_INT_SUM \
CVMX_ADD_IO_SEG(0x0001180028000040ull)
#define CVMX_FPA_QUE0_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x00011800280000F0ull)
#define CVMX_FPA_QUE1_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x00011800280000F8ull)
#define CVMX_FPA_QUE2_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000100ull)
#define CVMX_FPA_QUE3_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000108ull)
#define CVMX_FPA_QUE4_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000110ull)
#define CVMX_FPA_QUE5_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000118ull)
#define CVMX_FPA_QUE6_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000120ull)
#define CVMX_FPA_QUE7_PAGE_INDEX \
CVMX_ADD_IO_SEG(0x0001180028000128ull)
#define CVMX_FPA_QUEX_AVAILABLE(offset) \
CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
#define CVMX_FPA_QUE_ACT \
CVMX_ADD_IO_SEG(0x0001180028000138ull)
#define CVMX_FPA_QUE_EXP \
CVMX_ADD_IO_SEG(0x0001180028000130ull)
#define CVMX_FPA_WART_CTL \
CVMX_ADD_IO_SEG(0x00011800280000D8ull)
#define CVMX_FPA_WART_STATUS \
CVMX_ADD_IO_SEG(0x00011800280000E0ull)
union cvmx_fpa_bist_status {
uint64_t u64;
struct cvmx_fpa_bist_status_s {
uint64_t reserved_5_63:59;
uint64_t frd:1;
uint64_t fpf0:1;
uint64_t fpf1:1;
uint64_t ffr:1;
uint64_t fdr:1;
} s;
struct cvmx_fpa_bist_status_s cn30xx;
struct cvmx_fpa_bist_status_s cn31xx;
struct cvmx_fpa_bist_status_s cn38xx;
struct cvmx_fpa_bist_status_s cn38xxp2;
struct cvmx_fpa_bist_status_s cn50xx;
struct cvmx_fpa_bist_status_s cn52xx;
struct cvmx_fpa_bist_status_s cn52xxp1;
struct cvmx_fpa_bist_status_s cn56xx;
struct cvmx_fpa_bist_status_s cn56xxp1;
struct cvmx_fpa_bist_status_s cn58xx;
struct cvmx_fpa_bist_status_s cn58xxp1;
};
union cvmx_fpa_ctl_status {
uint64_t u64;
struct cvmx_fpa_ctl_status_s {
uint64_t reserved_18_63:46;
uint64_t reset:1;
uint64_t use_ldt:1;
uint64_t use_stt:1;
uint64_t enb:1;
uint64_t mem1_err:7;
uint64_t mem0_err:7;
} s;
struct cvmx_fpa_ctl_status_s cn30xx;
struct cvmx_fpa_ctl_status_s cn31xx;
struct cvmx_fpa_ctl_status_s cn38xx;
struct cvmx_fpa_ctl_status_s cn38xxp2;
struct cvmx_fpa_ctl_status_s cn50xx;
struct cvmx_fpa_ctl_status_s cn52xx;
struct cvmx_fpa_ctl_status_s cn52xxp1;
struct cvmx_fpa_ctl_status_s cn56xx;
struct cvmx_fpa_ctl_status_s cn56xxp1;
struct cvmx_fpa_ctl_status_s cn58xx;
struct cvmx_fpa_ctl_status_s cn58xxp1;
};
union cvmx_fpa_fpfx_marks {
uint64_t u64;
struct cvmx_fpa_fpfx_marks_s {
uint64_t reserved_22_63:42;
uint64_t fpf_wr:11;
uint64_t fpf_rd:11;
} s;
struct cvmx_fpa_fpfx_marks_s cn38xx;
struct cvmx_fpa_fpfx_marks_s cn38xxp2;
struct cvmx_fpa_fpfx_marks_s cn56xx;
struct cvmx_fpa_fpfx_marks_s cn56xxp1;
struct cvmx_fpa_fpfx_marks_s cn58xx;
struct cvmx_fpa_fpfx_marks_s cn58xxp1;
};
union cvmx_fpa_fpfx_size {
uint64_t u64;
struct cvmx_fpa_fpfx_size_s {
uint64_t reserved_11_63:53;
uint64_t fpf_siz:11;
} s;
struct cvmx_fpa_fpfx_size_s cn38xx;
struct cvmx_fpa_fpfx_size_s cn38xxp2;
struct cvmx_fpa_fpfx_size_s cn56xx;
struct cvmx_fpa_fpfx_size_s cn56xxp1;
struct cvmx_fpa_fpfx_size_s cn58xx;
struct cvmx_fpa_fpfx_size_s cn58xxp1;
};
union cvmx_fpa_fpf0_marks {
uint64_t u64;
struct cvmx_fpa_fpf0_marks_s {
uint64_t reserved_24_63:40;
uint64_t fpf_wr:12;
uint64_t fpf_rd:12;
} s;
struct cvmx_fpa_fpf0_marks_s cn38xx;
struct cvmx_fpa_fpf0_marks_s cn38xxp2;
struct cvmx_fpa_fpf0_marks_s cn56xx;
struct cvmx_fpa_fpf0_marks_s cn56xxp1;
struct cvmx_fpa_fpf0_marks_s cn58xx;
struct cvmx_fpa_fpf0_marks_s cn58xxp1;
};
union cvmx_fpa_fpf0_size {
uint64_t u64;
struct cvmx_fpa_fpf0_size_s {
uint64_t reserved_12_63:52;
uint64_t fpf_siz:12;
} s;
struct cvmx_fpa_fpf0_size_s cn38xx;
struct cvmx_fpa_fpf0_size_s cn38xxp2;
struct cvmx_fpa_fpf0_size_s cn56xx;
struct cvmx_fpa_fpf0_size_s cn56xxp1;
struct cvmx_fpa_fpf0_size_s cn58xx;
struct cvmx_fpa_fpf0_size_s cn58xxp1;
};
union cvmx_fpa_int_enb {
uint64_t u64;
struct cvmx_fpa_int_enb_s {
uint64_t reserved_28_63:36;
uint64_t q7_perr:1;
uint64_t q7_coff:1;
uint64_t q7_und:1;
uint64_t q6_perr:1;
uint64_t q6_coff:1;
uint64_t q6_und:1;
uint64_t q5_perr:1;
uint64_t q5_coff:1;
uint64_t q5_und:1;
uint64_t q4_perr:1;
uint64_t q4_coff:1;
uint64_t q4_und:1;
uint64_t q3_perr:1;
uint64_t q3_coff:1;
uint64_t q3_und:1;
uint64_t q2_perr:1;
uint64_t q2_coff:1;
uint64_t q2_und:1;
uint64_t q1_perr:1;
uint64_t q1_coff:1;
uint64_t q1_und:1;
uint64_t q0_perr:1;
uint64_t q0_coff:1;
uint64_t q0_und:1;
uint64_t fed1_dbe:1;
uint64_t fed1_sbe:1;
uint64_t fed0_dbe:1;
uint64_t fed0_sbe:1;
} s;
struct cvmx_fpa_int_enb_s cn30xx;
struct cvmx_fpa_int_enb_s cn31xx;
struct cvmx_fpa_int_enb_s cn38xx;
struct cvmx_fpa_int_enb_s cn38xxp2;
struct cvmx_fpa_int_enb_s cn50xx;
struct cvmx_fpa_int_enb_s cn52xx;
struct cvmx_fpa_int_enb_s cn52xxp1;
struct cvmx_fpa_int_enb_s cn56xx;
struct cvmx_fpa_int_enb_s cn56xxp1;
struct cvmx_fpa_int_enb_s cn58xx;
struct cvmx_fpa_int_enb_s cn58xxp1;
};
union cvmx_fpa_int_sum {
uint64_t u64;
struct cvmx_fpa_int_sum_s {
uint64_t reserved_28_63:36;
uint64_t q7_perr:1;
uint64_t q7_coff:1;
uint64_t q7_und:1;
uint64_t q6_perr:1;
uint64_t q6_coff:1;
uint64_t q6_und:1;
uint64_t q5_perr:1;
uint64_t q5_coff:1;
uint64_t q5_und:1;
uint64_t q4_perr:1;
uint64_t q4_coff:1;
uint64_t q4_und:1;
uint64_t q3_perr:1;
uint64_t q3_coff:1;
uint64_t q3_und:1;
uint64_t q2_perr:1;
uint64_t q2_coff:1;
uint64_t q2_und:1;
uint64_t q1_perr:1;
uint64_t q1_coff:1;
uint64_t q1_und:1;
uint64_t q0_perr:1;
uint64_t q0_coff:1;
uint64_t q0_und:1;
uint64_t fed1_dbe:1;
uint64_t fed1_sbe:1;
uint64_t fed0_dbe:1;
uint64_t fed0_sbe:1;
} s;
struct cvmx_fpa_int_sum_s cn30xx;
struct cvmx_fpa_int_sum_s cn31xx;
struct cvmx_fpa_int_sum_s cn38xx;
struct cvmx_fpa_int_sum_s cn38xxp2;
struct cvmx_fpa_int_sum_s cn50xx;
struct cvmx_fpa_int_sum_s cn52xx;
struct cvmx_fpa_int_sum_s cn52xxp1;
struct cvmx_fpa_int_sum_s cn56xx;
struct cvmx_fpa_int_sum_s cn56xxp1;
struct cvmx_fpa_int_sum_s cn58xx;
struct cvmx_fpa_int_sum_s cn58xxp1;
};
union cvmx_fpa_quex_available {
uint64_t u64;
struct cvmx_fpa_quex_available_s {
uint64_t reserved_29_63:35;
uint64_t que_siz:29;
} s;
struct cvmx_fpa_quex_available_s cn30xx;
struct cvmx_fpa_quex_available_s cn31xx;
struct cvmx_fpa_quex_available_s cn38xx;
struct cvmx_fpa_quex_available_s cn38xxp2;
struct cvmx_fpa_quex_available_s cn50xx;
struct cvmx_fpa_quex_available_s cn52xx;
struct cvmx_fpa_quex_available_s cn52xxp1;
struct cvmx_fpa_quex_available_s cn56xx;
struct cvmx_fpa_quex_available_s cn56xxp1;
struct cvmx_fpa_quex_available_s cn58xx;
struct cvmx_fpa_quex_available_s cn58xxp1;
};
union cvmx_fpa_quex_page_index {
uint64_t u64;
struct cvmx_fpa_quex_page_index_s {
uint64_t reserved_25_63:39;
uint64_t pg_num:25;
} s;
struct cvmx_fpa_quex_page_index_s cn30xx;
struct cvmx_fpa_quex_page_index_s cn31xx;
struct cvmx_fpa_quex_page_index_s cn38xx;
struct cvmx_fpa_quex_page_index_s cn38xxp2;
struct cvmx_fpa_quex_page_index_s cn50xx;
struct cvmx_fpa_quex_page_index_s cn52xx;
struct cvmx_fpa_quex_page_index_s cn52xxp1;
struct cvmx_fpa_quex_page_index_s cn56xx;
struct cvmx_fpa_quex_page_index_s cn56xxp1;
struct cvmx_fpa_quex_page_index_s cn58xx;
struct cvmx_fpa_quex_page_index_s cn58xxp1;
};
union cvmx_fpa_que_act {
uint64_t u64;
struct cvmx_fpa_que_act_s {
uint64_t reserved_29_63:35;
uint64_t act_que:3;
uint64_t act_indx:26;
} s;
struct cvmx_fpa_que_act_s cn30xx;
struct cvmx_fpa_que_act_s cn31xx;
struct cvmx_fpa_que_act_s cn38xx;
struct cvmx_fpa_que_act_s cn38xxp2;
struct cvmx_fpa_que_act_s cn50xx;
struct cvmx_fpa_que_act_s cn52xx;
struct cvmx_fpa_que_act_s cn52xxp1;
struct cvmx_fpa_que_act_s cn56xx;
struct cvmx_fpa_que_act_s cn56xxp1;
struct cvmx_fpa_que_act_s cn58xx;
struct cvmx_fpa_que_act_s cn58xxp1;
};
union cvmx_fpa_que_exp {
uint64_t u64;
struct cvmx_fpa_que_exp_s {
uint64_t reserved_29_63:35;
uint64_t exp_que:3;
uint64_t exp_indx:26;
} s;
struct cvmx_fpa_que_exp_s cn30xx;
struct cvmx_fpa_que_exp_s cn31xx;
struct cvmx_fpa_que_exp_s cn38xx;
struct cvmx_fpa_que_exp_s cn38xxp2;
struct cvmx_fpa_que_exp_s cn50xx;
struct cvmx_fpa_que_exp_s cn52xx;
struct cvmx_fpa_que_exp_s cn52xxp1;
struct cvmx_fpa_que_exp_s cn56xx;
struct cvmx_fpa_que_exp_s cn56xxp1;
struct cvmx_fpa_que_exp_s cn58xx;
struct cvmx_fpa_que_exp_s cn58xxp1;
};
union cvmx_fpa_wart_ctl {
uint64_t u64;
struct cvmx_fpa_wart_ctl_s {
uint64_t reserved_16_63:48;
uint64_t ctl:16;
} s;
struct cvmx_fpa_wart_ctl_s cn30xx;
struct cvmx_fpa_wart_ctl_s cn31xx;
struct cvmx_fpa_wart_ctl_s cn38xx;
struct cvmx_fpa_wart_ctl_s cn38xxp2;
struct cvmx_fpa_wart_ctl_s cn50xx;
struct cvmx_fpa_wart_ctl_s cn52xx;
struct cvmx_fpa_wart_ctl_s cn52xxp1;
struct cvmx_fpa_wart_ctl_s cn56xx;
struct cvmx_fpa_wart_ctl_s cn56xxp1;
struct cvmx_fpa_wart_ctl_s cn58xx;
struct cvmx_fpa_wart_ctl_s cn58xxp1;
};
union cvmx_fpa_wart_status {
uint64_t u64;
struct cvmx_fpa_wart_status_s {
uint64_t reserved_32_63:32;
uint64_t status:32;
} s;
struct cvmx_fpa_wart_status_s cn30xx;
struct cvmx_fpa_wart_status_s cn31xx;
struct cvmx_fpa_wart_status_s cn38xx;
struct cvmx_fpa_wart_status_s cn38xxp2;
struct cvmx_fpa_wart_status_s cn50xx;
struct cvmx_fpa_wart_status_s cn52xx;
struct cvmx_fpa_wart_status_s cn52xxp1;
struct cvmx_fpa_wart_status_s cn56xx;
struct cvmx_fpa_wart_status_s cn56xxp1;
struct cvmx_fpa_wart_status_s cn58xx;
struct cvmx_fpa_wart_status_s cn58xxp1;
};
#endif
drivers/staging/octeon/cvmx-fpa.c
+183
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@@ -0,0 +1,183 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* @file
*
* Support library for the hardware Free Pool Allocator.
*
*
*/
#include "cvmx-config.h"
#include "cvmx.h"
#include "cvmx-fpa.h"
#include "cvmx-ipd.h"
/**
* Current state of all the pools. Use access functions
* instead of using it directly.
*/
CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
/**
* Setup a FPA pool to control a new block of memory. The
* buffer pointer must be a physical address.
*
* @pool: Pool to initialize
* 0 <= pool < 8
* @name: Constant character string to name this pool.
* String is not copied.
* @buffer: Pointer to the block of memory to use. This must be
* accessable by all processors and external hardware.
* @block_size: Size for each block controlled by the FPA
* @num_blocks: Number of blocks
*
* Returns 0 on Success,
* -1 on failure
*/
int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
uint64_t block_size, uint64_t num_blocks)
{
char *ptr;
if (!buffer) {
cvmx_dprintf
("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
return -1;
}
if (pool >= CVMX_FPA_NUM_POOLS) {
cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
return -1;
}
if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) {
cvmx_dprintf
("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
return -1;
}
if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) {
cvmx_dprintf
("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
return -1;
}
cvmx_fpa_pool_info[pool].name = name;
cvmx_fpa_pool_info[pool].size = block_size;
cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
cvmx_fpa_pool_info[pool].base = buffer;
ptr = (char *)buffer;
while (num_blocks--) {
cvmx_fpa_free(ptr, pool, 0);
ptr += block_size;
}
return 0;
}
/**
* Shutdown a Memory pool and validate that it had all of
* the buffers originally placed in it.
*
* @pool: Pool to shutdown
* Returns Zero on success
* - Positive is count of missing buffers
* - Negative is too many buffers or corrupted pointers
*/
uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
{
uint64_t errors = 0;
uint64_t count = 0;
uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
uint64_t finish =
base +
cvmx_fpa_pool_info[pool].size *
cvmx_fpa_pool_info[pool].starting_element_count;
void *ptr;
uint64_t address;
count = 0;
do {
ptr = cvmx_fpa_alloc(pool);
if (ptr)
address = cvmx_ptr_to_phys(ptr);
else
address = 0;
if (address) {
if ((address >= base) && (address < finish) &&
(((address -
base) % cvmx_fpa_pool_info[pool].size) == 0)) {
count++;
} else {
cvmx_dprintf
("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
(unsigned long long)address,
cvmx_fpa_pool_info[pool].name, (int)pool);
errors++;
}
}
} while (address);
#ifdef CVMX_ENABLE_PKO_FUNCTIONS
if (pool == 0)
cvmx_ipd_free_ptr();
#endif
if (errors) {
cvmx_dprintf
("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
cvmx_fpa_pool_info[pool].name, (int)pool,
(unsigned long long)base, (unsigned long long)finish,
(unsigned long long)cvmx_fpa_pool_info[pool].size);
return -errors;
} else
return 0;
}
uint64_t cvmx_fpa_get_block_size(uint64_t pool)
{
switch (pool) {
case 0:
return CVMX_FPA_POOL_0_SIZE;
case 1:
return CVMX_FPA_POOL_1_SIZE;
case 2:
return CVMX_FPA_POOL_2_SIZE;
case 3:
return CVMX_FPA_POOL_3_SIZE;
case 4:
return CVMX_FPA_POOL_4_SIZE;
case 5:
return CVMX_FPA_POOL_5_SIZE;
case 6:
return CVMX_FPA_POOL_6_SIZE;
case 7:
return CVMX_FPA_POOL_7_SIZE;
default:
return 0;
}
}
drivers/staging/octeon/cvmx-fpa.h
+299
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@@ -0,0 +1,299 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* @file
*
* Interface to the hardware Free Pool Allocator.
*
*
*/
#ifndef __CVMX_FPA_H__
#define __CVMX_FPA_H__
#include "cvmx-address.h"
#include "cvmx-fpa-defs.h"
#define CVMX_FPA_NUM_POOLS 8
#define CVMX_FPA_MIN_BLOCK_SIZE 128
#define CVMX_FPA_ALIGNMENT 128
/**
* Structure describing the data format used for stores to the FPA.
*/
typedef union {
uint64_t u64;
struct {
/*
* the (64-bit word) location in scratchpad to write
* to (if len != 0)
*/
uint64_t scraddr:8;
/* the number of words in the response (0 => no response) */
uint64_t len:8;
/* the ID of the device on the non-coherent bus */
uint64_t did:8;
/*
* the address that will appear in the first tick on
* the NCB bus.
*/
uint64_t addr:40;
} s;
} cvmx_fpa_iobdma_data_t;
/**
* Structure describing the current state of a FPA pool.
*/
typedef struct {
/* Name it was created under */
const char *name;
/* Size of each block */
uint64_t size;
/* The base memory address of whole block */
void *base;
/* The number of elements in the pool at creation */
uint64_t starting_element_count;
} cvmx_fpa_pool_info_t;
/**
* Current state of all the pools. Use access functions
* instead of using it directly.
*/
extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
/* CSR typedefs have been moved to cvmx-csr-*.h */
/**
* Return the name of the pool
*
* @pool: Pool to get the name of
* Returns The name
*/
static inline const char *cvmx_fpa_get_name(uint64_t pool)
{
return cvmx_fpa_pool_info[pool].name;
}
/**
* Return the base of the pool
*
* @pool: Pool to get the base of
* Returns The base
*/
static inline void *cvmx_fpa_get_base(uint64_t pool)
{
return cvmx_fpa_pool_info[pool].base;
}
/**
* Check if a pointer belongs to an FPA pool. Return non-zero
* if the supplied pointer is inside the memory controlled by
* an FPA pool.
*
* @pool: Pool to check
* @ptr: Pointer to check
* Returns Non-zero if pointer is in the pool. Zero if not
*/
static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
{
return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
((char *)ptr <
((char *)(cvmx_fpa_pool_info[pool].base)) +
cvmx_fpa_pool_info[pool].size *
cvmx_fpa_pool_info[pool].starting_element_count));
}
/**
* Enable the FPA for use. Must be performed after any CSR
* configuration but before any other FPA functions.
*/
static inline void cvmx_fpa_enable(void)
{
union cvmx_fpa_ctl_status status;
status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
if (status.s.enb) {
cvmx_dprintf
("Warning: Enabling FPA when FPA already enabled.\n");
}
/*
* Do runtime check as we allow pass1 compiled code to run on
* pass2 chips.
*/
if (cvmx_octeon_is_pass1()) {
union cvmx_fpa_fpfx_marks marks;
int i;
for (i = 1; i < 8; i++) {
marks.u64 =
cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
marks.s.fpf_wr = 0xe0;
cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
marks.u64);
}
/* Enforce a 10 cycle delay between config and enable */
cvmx_wait(10);
}
/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
status.u64 = 0;
status.s.enb = 1;
cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
}
/**
* Get a new block from the FPA
*
* @pool: Pool to get the block from
* Returns Pointer to the block or NULL on failure
*/
static inline void *cvmx_fpa_alloc(uint64_t pool)
{
uint64_t address =
cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
if (address)
return cvmx_phys_to_ptr(address);
else
return NULL;
}
/**
* Asynchronously get a new block from the FPA
*
* @scr_addr: Local scratch address to put response in. This is a byte address,
* but must be 8 byte aligned.
* @pool: Pool to get the block from
*/
static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
{
cvmx_fpa_iobdma_data_t data;
/*
* Hardware only uses 64 bit alligned locations, so convert
* from byte address to 64-bit index
*/
data.s.scraddr = scr_addr >> 3;
data.s.len = 1;
data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
data.s.addr = 0;
cvmx_send_single(data.u64);
}
/**
* Free a block allocated with a FPA pool. Does NOT provide memory
* ordering in cases where the memory block was modified by the core.
*
* @ptr: Block to free
* @pool: Pool to put it in
* @num_cache_lines:
* Cache lines to invalidate
*/
static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
uint64_t num_cache_lines)
{
cvmx_addr_t newptr;
newptr.u64 = cvmx_ptr_to_phys(ptr);
newptr.sfilldidspace.didspace =
CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
/* Prevent GCC from reordering around free */
barrier();
/* value written is number of cache lines not written back */
cvmx_write_io(newptr.u64, num_cache_lines);
}
/**
* Free a block allocated with a FPA pool. Provides required memory
* ordering in cases where memory block was modified by core.
*
* @ptr: Block to free
* @pool: Pool to put it in
* @num_cache_lines:
* Cache lines to invalidate
*/
static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
uint64_t num_cache_lines)
{
cvmx_addr_t newptr;
newptr.u64 = cvmx_ptr_to_phys(ptr);
newptr.sfilldidspace.didspace =
CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
/*
* Make sure that any previous writes to memory go out before
* we free this buffer. This also serves as a barrier to
* prevent GCC from reordering operations to after the
* free.
*/
CVMX_SYNCWS;
/* value written is number of cache lines not written back */
cvmx_write_io(newptr.u64, num_cache_lines);
}
/**
* Setup a FPA pool to control a new block of memory.
* This can only be called once per pool. Make sure proper
* locking enforces this.
*
* @pool: Pool to initialize
* 0 <= pool < 8
* @name: Constant character string to name this pool.
* String is not copied.
* @buffer: Pointer to the block of memory to use. This must be
* accessable by all processors and external hardware.
* @block_size: Size for each block controlled by the FPA
* @num_blocks: Number of blocks
*
* Returns 0 on Success,
* -1 on failure
*/
extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
uint64_t block_size, uint64_t num_blocks);
/**
* Shutdown a Memory pool and validate that it had all of
* the buffers originally placed in it. This should only be
* called by one processor after all hardware has finished
* using the pool.
*
* @pool: Pool to shutdown
* Returns Zero on success
* - Positive is count of missing buffers
* - Negative is too many buffers or corrupted pointers
*/
extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
/**
* Get the size of blocks controlled by the pool
* This is resolved to a constant at compile time.
*
* @pool: Pool to access
* Returns Size of the block in bytes
*/
uint64_t cvmx_fpa_get_block_size(uint64_t pool);
#endif /* __CVM_FPA_H__ */
drivers/staging/octeon/cvmx-gmxx-defs.h
+2529
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File diff suppressed because it is too large Load Diff
drivers/staging/octeon/cvmx-helper-board.c
+706
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File diff suppressed because it is too large Load Diff
drivers/staging/octeon/cvmx-helper-board.h
+180
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@@ -0,0 +1,180 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
*
* Helper functions to abstract board specific data about
* network ports from the rest of the cvmx-helper files.
*
*/
#ifndef __CVMX_HELPER_BOARD_H__
#define __CVMX_HELPER_BOARD_H__
#include "cvmx-helper.h"
typedef enum {
USB_CLOCK_TYPE_REF_12,
USB_CLOCK_TYPE_REF_24,
USB_CLOCK_TYPE_REF_48,
USB_CLOCK_TYPE_CRYSTAL_12,
} cvmx_helper_board_usb_clock_types_t;
typedef enum {
set_phy_link_flags_autoneg = 0x1,
set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
set_phy_link_flags_flow_control_enable = 0x1 << 1,
set_phy_link_flags_flow_control_disable = 0x2 << 1,
set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */
} cvmx_helper_board_set_phy_link_flags_types_t;
/**
* cvmx_override_board_link_get(int ipd_port) is a function
* pointer. It is meant to allow customization of the process of
* talking to a PHY to determine link speed. It is called every
* time a PHY must be polled for link status. Users should set
* this pointer to a function before calling any cvmx-helper
* operations.
*/
extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
/**
* Return the MII PHY address associated with the given IPD
* port. A result of -1 means there isn't a MII capable PHY
* connected to this port. On chips supporting multiple MII
* busses the bus number is encoded in bits <15:8>.
*
* This function must be modifed for every new Octeon board.
* Internally it uses switch statements based on the cvmx_sysinfo
* data to determine board types and revisions. It relys on the
* fact that every Octeon board receives a unique board type
* enumeration from the bootloader.
*
* @ipd_port: Octeon IPD port to get the MII address for.
*
* Returns MII PHY address and bus number or -1.
*/
extern int cvmx_helper_board_get_mii_address(int ipd_port);
/**
* This function as a board specific method of changing the PHY
* speed, duplex, and autonegotiation. This programs the PHY and
* not Octeon. This can be used to force Octeon's links to
* specific settings.
*
* @phy_addr: The address of the PHY to program
* @link_flags:
* Flags to control autonegotiation. Bit 0 is autonegotiation
* enable/disable to maintain backware compatability.
* @link_info: Link speed to program. If the speed is zero and autonegotiation
* is enabled, all possible negotiation speeds are advertised.
*
* Returns Zero on success, negative on failure
*/
int cvmx_helper_board_link_set_phy(int phy_addr,
cvmx_helper_board_set_phy_link_flags_types_t
link_flags,
cvmx_helper_link_info_t link_info);
/**
* This function is the board specific method of determining an
* ethernet ports link speed. Most Octeon boards have Marvell PHYs
* and are handled by the fall through case. This function must be
* updated for boards that don't have the normal Marvell PHYs.
*
* This function must be modifed for every new Octeon board.
* Internally it uses switch statements based on the cvmx_sysinfo
* data to determine board types and revisions. It relys on the
* fact that every Octeon board receives a unique board type
* enumeration from the bootloader.
*
* @ipd_port: IPD input port associated with the port we want to get link
* status for.
*
* Returns The ports link status. If the link isn't fully resolved, this must
* return zero.
*/
extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
/**
* This function is called by cvmx_helper_interface_probe() after it
* determines the number of ports Octeon can support on a specific
* interface. This function is the per board location to override
* this value. It is called with the number of ports Octeon might
* support and should return the number of actual ports on the
* board.
*
* This function must be modifed for every new Octeon board.
* Internally it uses switch statements based on the cvmx_sysinfo
* data to determine board types and revisions. It relys on the
* fact that every Octeon board receives a unique board type
* enumeration from the bootloader.
*
* @interface: Interface to probe
* @supported_ports:
* Number of ports Octeon supports.
*
* Returns Number of ports the actual board supports. Many times this will
* simple be "support_ports".
*/
extern int __cvmx_helper_board_interface_probe(int interface,
int supported_ports);
/**
* Enable packet input/output from the hardware. This function is
* called after by cvmx_helper_packet_hardware_enable() to
* perform board specific initialization. For most boards
* nothing is needed.
*
* @interface: Interface to enable
*
* Returns Zero on success, negative on failure
*/
extern int __cvmx_helper_board_hardware_enable(int interface);
/**
* Gets the clock type used for the USB block based on board type.
* Used by the USB code for auto configuration of clock type.
*
* Returns USB clock type enumeration
*/
cvmx_helper_board_usb_clock_types_t
__cvmx_helper_board_usb_get_clock_type(void);
/**
* Adjusts the number of available USB ports on Octeon based on board
* specifics.
*
* @supported_ports: expected number of ports based on chip type;
*
*
* Returns number of available usb ports, based on board specifics.
* Return value is supported_ports if function does not
* override.
*/
int __cvmx_helper_board_usb_get_num_ports(int supported_ports);
#endif /* __CVMX_HELPER_BOARD_H__ */
drivers/staging/octeon/cvmx-helper-fpa.c
+243
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@@ -0,0 +1,243 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* @file
*
* Helper functions for FPA setup.
*
*/
#include "executive-config.h"
#include "cvmx-config.h"
#include "cvmx.h"
#include "cvmx-bootmem.h"
#include "cvmx-fpa.h"
#include "cvmx-helper-fpa.h"
/**
* Allocate memory for and initialize a single FPA pool.
*
* @pool: Pool to initialize
* @buffer_size: Size of buffers to allocate in bytes
* @buffers: Number of buffers to put in the pool. Zero is allowed
* @name: String name of the pool for debugging purposes
* Returns Zero on success, non-zero on failure
*/
static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
uint64_t buffers, const char *name)
{
uint64_t current_num;
void *memory;
uint64_t align = CVMX_CACHE_LINE_SIZE;
/*
* Align the allocation so that power of 2 size buffers are
* naturally aligned.
*/
while (align < buffer_size)
align = align << 1;
if (buffers == 0)
return 0;
current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
if (current_num) {
cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. "
"Skipping setup.\n",
pool, name, (unsigned long long)current_num);
return 0;
}
memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
if (memory == NULL) {
cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n",
pool, name);
return -1;
}
cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
return 0;
}
/**
* Allocate memory and initialize the FPA pools using memory
* from cvmx-bootmem. Specifying zero for the number of
* buffers will cause that FPA pool to not be setup. This is
* useful if you aren't using some of the hardware and want
* to save memory. Use cvmx_helper_initialize_fpa instead of
* this function directly.
*
* @pip_pool: Should always be CVMX_FPA_PACKET_POOL
* @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE
* @pip_buffers:
* Number of packet buffers.
* @wqe_pool: Should always be CVMX_FPA_WQE_POOL
* @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE
* @wqe_entries:
* Number of work queue entries
* @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
* @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
* @pko_buffers:
* PKO Command buffers. You should at minimum have two per
* each PKO queue.
* @tim_pool: Should always be CVMX_FPA_TIMER_POOL
* @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE
* @tim_buffers:
* TIM ring buffer command queues. At least two per timer bucket
* is recommened.
* @dfa_pool: Should always be CVMX_FPA_DFA_POOL
* @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE
* @dfa_buffers:
* DFA command buffer. A relatively small (32 for example)
* number should work.
* Returns Zero on success, non-zero if out of memory
*/
static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size,
int pip_buffers, int wqe_pool,
int wqe_size, int wqe_entries,
int pko_pool, int pko_size,
int pko_buffers, int tim_pool,
int tim_size, int tim_buffers,
int dfa_pool, int dfa_size,
int dfa_buffers)
{
int status;
cvmx_fpa_enable();
if ((pip_buffers > 0) && (pip_buffers <= 64))
cvmx_dprintf
("Warning: %d packet buffers may not be enough for hardware"
" prefetch. 65 or more is recommended.\n", pip_buffers);
if (pip_pool >= 0) {
status =
__cvmx_helper_initialize_fpa_pool(pip_pool, pip_size,
pip_buffers,
"Packet Buffers");
if (status)
return status;
}
if (wqe_pool >= 0) {
status =
__cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size,
wqe_entries,
"Work Queue Entries");
if (status)
return status;
}
if (pko_pool >= 0) {
status =
__cvmx_helper_initialize_fpa_pool(pko_pool, pko_size,
pko_buffers,
"PKO Command Buffers");
if (status)
return status;
}
if (tim_pool >= 0) {
status =
__cvmx_helper_initialize_fpa_pool(tim_pool, tim_size,
tim_buffers,
"TIM Command Buffers");
if (status)
return status;
}
if (dfa_pool >= 0) {
status =
__cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size,
dfa_buffers,
"DFA Command Buffers");
if (status)
return status;
}
return 0;
}
/**
* Allocate memory and initialize the FPA pools using memory
* from cvmx-bootmem. Sizes of each element in the pools is
* controlled by the cvmx-config.h header file. Specifying
* zero for any parameter will cause that FPA pool to not be
* setup. This is useful if you aren't using some of the
* hardware and want to save memory.
*
* @packet_buffers:
* Number of packet buffers to allocate
* @work_queue_entries:
* Number of work queue entries
* @pko_buffers:
* PKO Command buffers. You should at minimum have two per
* each PKO queue.
* @tim_buffers:
* TIM ring buffer command queues. At least two per timer bucket
* is recommened.
* @dfa_buffers:
* DFA command buffer. A relatively small (32 for example)
* number should work.
* Returns Zero on success, non-zero if out of memory
*/
int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
int pko_buffers, int tim_buffers,
int dfa_buffers)
{
#ifndef CVMX_FPA_PACKET_POOL
#define CVMX_FPA_PACKET_POOL -1
#define CVMX_FPA_PACKET_POOL_SIZE 0
#endif
#ifndef CVMX_FPA_WQE_POOL
#define CVMX_FPA_WQE_POOL -1
#define CVMX_FPA_WQE_POOL_SIZE 0
#endif
#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
#endif
#ifndef CVMX_FPA_TIMER_POOL
#define CVMX_FPA_TIMER_POOL -1
#define CVMX_FPA_TIMER_POOL_SIZE 0
#endif
#ifndef CVMX_FPA_DFA_POOL
#define CVMX_FPA_DFA_POOL -1
#define CVMX_FPA_DFA_POOL_SIZE 0
#endif
return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL,
CVMX_FPA_PACKET_POOL_SIZE,
packet_buffers, CVMX_FPA_WQE_POOL,
CVMX_FPA_WQE_POOL_SIZE,
work_queue_entries,
CVMX_FPA_OUTPUT_BUFFER_POOL,
CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
pko_buffers, CVMX_FPA_TIMER_POOL,
CVMX_FPA_TIMER_POOL_SIZE,
tim_buffers, CVMX_FPA_DFA_POOL,
CVMX_FPA_DFA_POOL_SIZE,
dfa_buffers);
}
drivers/staging/octeon/cvmx-helper-fpa.h
+64
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@@ -0,0 +1,64 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* @file
*
* Helper functions for FPA setup.
*
*/
#ifndef __CVMX_HELPER_H_FPA__
#define __CVMX_HELPER_H_FPA__
/**
* Allocate memory and initialize the FPA pools using memory
* from cvmx-bootmem. Sizes of each element in the pools is
* controlled by the cvmx-config.h header file. Specifying
* zero for any parameter will cause that FPA pool to not be
* setup. This is useful if you aren't using some of the
* hardware and want to save memory.
*
* @packet_buffers:
* Number of packet buffers to allocate
* @work_queue_entries:
* Number of work queue entries
* @pko_buffers:
* PKO Command buffers. You should at minimum have two per
* each PKO queue.
* @tim_buffers:
* TIM ring buffer command queues. At least two per timer bucket
* is recommened.
* @dfa_buffers:
* DFA command buffer. A relatively small (32 for example)
* number should work.
* Returns Zero on success, non-zero if out of memory
*/
extern int cvmx_helper_initialize_fpa(int packet_buffers,
int work_queue_entries, int pko_buffers,
int tim_buffers, int dfa_buffers);
#endif /* __CVMX_HELPER_H__ */
drivers/staging/octeon/cvmx-helper-loop.c
+85
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@@ -0,0 +1,85 @@
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* Functions for LOOP initialization, configuration,
* and monitoring.
*/
#include <asm/octeon/octeon.h>
#include "cvmx-config.h"
#include "cvmx-helper.h"
#include "cvmx-pip-defs.h"
/**
* Probe a LOOP interface and determine the number of ports
* connected to it. The LOOP interface should still be down
* after this call.
*
* @interface: Interface to probe
*
* Returns Number of ports on the interface. Zero to disable.
*/
int __cvmx_helper_loop_probe(int interface)
{
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
int num_ports = 4;
int port;
/* We need to disable length checking so packet < 64 bytes and jumbo
frames don't get errors */
for (port = 0; port < num_ports; port++) {
union cvmx_pip_prt_cfgx port_cfg;
int ipd_port = cvmx_helper_get_ipd_port(interface, port);
port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
port_cfg.s.maxerr_en = 0;
port_cfg.s.minerr_en = 0;
cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
}
/* Disable FCS stripping for loopback ports */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit2 = 0;
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
return num_ports;
}
/**
* Bringup and enable a LOOP interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
*
* @interface: Interface to bring up
*
* Returns Zero on success, negative on failure
*/
int __cvmx_helper_loop_enable(int interface)
{
/* Do nothing. */
return 0;
}

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