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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"The whole series has been sitting in -next for quite a while with no
complaints. The last change to the series was before the weekend the
removal of an SPI patch which Grant - even though previously acked by
himself - appeared to raise objections. So I removed it until the
situation is clarified. Other than that all the patches have the acks
from their respective maintainers, all MIPS and x86 defconfigs are
building fine and I'm not aware of any problems introduced by this
series.
Among the key features for this patch series is a sizable patchset for
Lantiq which among other things introduces support for Lantiq's
flagship product, the FALCON SOC. It also means that the opensource
developers behind this patchset have overtaken Lantiq's competing
inhouse development team that was working behind closed doors.
Less noteworthy the ath79 patchset which adds support for a few more
chip variants, cleanups and fixes. Finally the usual dose of tweaking
of generic code."
Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where
printk spelling fixes clashed with file move and eventual removal of the
printk.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)
MIPS: lantiq: remove orphaned code
MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.
MIPS: lantiq: implement support for FALCON soc
MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc
MTD: MIPS: lantiq: implement OF support
watchdog: MIPS: lantiq: implement OF support and minor fixes
SERIAL: MIPS: lantiq: implement OF support
GPIO: MIPS: lantiq: convert gpio-stp-xway to OF
GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio
GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder
MIPS: pci: convert lantiq driver to OF
MIPS: lantiq: convert dma to platform driver
MIPS: lantiq: implement support for clkdev api
MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()
OF: MIPS: lantiq: implement irq_domain support
OF: MIPS: lantiq: implement OF support
MIPS: lantiq: drop mips_machine support
OF: PCI: const usage needed by MIPS
MIPS: Cavium: Remove smp_reserve_lock.
MIPS: Move cache setup to setup_arch().
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,38 @@
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Lantiq SoC External Bus memory mapped GPIO controller
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By attaching hardware latches to the EBU it is possible to create output
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only gpios. This driver configures a special memory address, which when
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written to outputs 16 bit to the latches.
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The node describing the memory mapped GPIOs needs to be a child of the node
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describing the "lantiq,localbus".
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Required properties:
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- compatible : Should be "lantiq,gpio-mm-lantiq"
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- reg : Address and length of the register set for the device
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify optional parameters (currently
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unused).
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- gpio-controller : Marks the device node as a gpio controller.
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Optional properties:
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- lantiq,shadow : The default value that we shall assume as already set on the
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shift register cascade.
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Example:
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
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1 0 0x4000000 0x4000010>; /* addsel1 */
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compatible = "lantiq,localbus", "simple-bus";
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gpio_mm0: gpio@4000000 {
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compatible = "lantiq,gpio-mm";
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reg = <1 0x0 0x10>;
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gpio-controller;
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#gpio-cells = <2>;
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lantiq,shadow = <0x77f>
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};
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}
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@@ -0,0 +1,42 @@
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Lantiq SoC Serial To Parallel (STP) GPIO controller
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The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
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peripheral controller used to drive external shift register cascades. At most
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3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
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to drive the 2 LSBs of the cascade automatically.
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Required properties:
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- compatible : Should be "lantiq,gpio-stp-xway"
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- reg : Address and length of the register set for the device
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify optional parameters (currently
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unused).
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- gpio-controller : Marks the device node as a gpio controller.
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Optional properties:
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- lantiq,shadow : The default value that we shall assume as already set on the
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shift register cascade.
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- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
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in the shift register cascade.
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- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
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property can enable this feature.
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- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
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- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
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- lantiq,rising : use rising instead of falling edge for the shift register
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Example:
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gpio1: stp@E100BB0 {
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compatible = "lantiq,gpio-stp-xway";
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reg = <0xE100BB0 0x40>;
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#gpio-cells = <2>;
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gpio-controller;
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lantiq,shadow = <0xffff>;
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lantiq,groups = <0x7>;
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lantiq,dsl = <0x3>;
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lantiq,phy1 = <0x7>;
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lantiq,phy2 = <0x7>;
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/* lantiq,rising; */
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};
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+9
-6
@@ -233,8 +233,9 @@ config LANTIQ
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select ARCH_REQUIRE_GPIOLIB
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select SWAP_IO_SPACE
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select BOOT_RAW
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select HAVE_CLK
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select MIPS_MACHINE
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select HAVE_MACH_CLKDEV
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select CLKDEV_LOOKUP
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select USE_OF
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config LASAT
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bool "LASAT Networks platforms"
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@@ -1783,10 +1784,12 @@ endchoice
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config FORCE_MAX_ZONEORDER
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int "Maximum zone order"
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range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
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default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
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range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
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default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
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range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB
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default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB
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range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB
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default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB
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range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB
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default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB
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range 11 64
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default "11"
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help
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@@ -22,6 +22,7 @@
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/leds.h>
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+24
-1
@@ -26,6 +26,18 @@ config ATH79_MACH_AP81
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Say 'Y' here if you want your kernel to support the
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||||
Atheros AP81 reference board.
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config ATH79_MACH_DB120
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bool "Atheros DB120 reference board"
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select SOC_AR934X
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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select ATH79_DEV_USB
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select ATH79_DEV_WMAC
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help
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Say 'Y' here if you want your kernel to support the
|
||||
Atheros DB120 reference board.
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config ATH79_MACH_PB44
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bool "Atheros PB44 reference board"
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select SOC_AR71XX
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@@ -52,12 +64,14 @@ endmenu
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config SOC_AR71XX
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select USB_ARCH_HAS_EHCI
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select USB_ARCH_HAS_OHCI
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select HW_HAS_PCI
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def_bool n
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|
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config SOC_AR724X
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select USB_ARCH_HAS_EHCI
|
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select USB_ARCH_HAS_OHCI
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select HW_HAS_PCI
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select PCI_AR724X if PCI
|
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def_bool n
|
||||
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config SOC_AR913X
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@@ -68,6 +82,15 @@ config SOC_AR933X
|
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select USB_ARCH_HAS_EHCI
|
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def_bool n
|
||||
|
||||
config SOC_AR934X
|
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select USB_ARCH_HAS_EHCI
|
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select HW_HAS_PCI
|
||||
select PCI_AR724X if PCI
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def_bool n
|
||||
|
||||
config PCI_AR724X
|
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def_bool n
|
||||
|
||||
config ATH79_DEV_GPIO_BUTTONS
|
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def_bool n
|
||||
|
||||
@@ -81,7 +104,7 @@ config ATH79_DEV_USB
|
||||
def_bool n
|
||||
|
||||
config ATH79_DEV_WMAC
|
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depends on (SOC_AR913X || SOC_AR933X)
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depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
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def_bool n
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|
||||
endif
|
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|
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@@ -11,6 +11,7 @@
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obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
|
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|
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_PCI) += pci.o
|
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|
||||
#
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# Devices
|
||||
@@ -27,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
|
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#
|
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obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
|
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obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
|
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obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
|
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obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
|
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obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
|
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|
||||
@@ -1,8 +1,11 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X/AR913X common routines
|
||||
*
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(void)
|
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ath79_uart_clk.rate = ath79_ref_clk.rate;
|
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}
|
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|
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static void __init ar934x_clocks_init(void)
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{
|
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
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u32 cpu_pll, ddr_pll;
|
||||
u32 bootstrap;
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|
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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ath79_ref_clk.rate = 40 * 1000 * 1000;
|
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else
|
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ath79_ref_clk.rate = 25 * 1000 * 1000;
|
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|
||||
pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
|
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out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
||||
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
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AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
|
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nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
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AR934X_PLL_CPU_CONFIG_NINT_MASK;
|
||||
frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
|
||||
|
||||
cpu_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
|
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cpu_pll /= (1 << out_div);
|
||||
|
||||
pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
|
||||
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
||||
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
||||
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
||||
AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
|
||||
nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
||||
AR934X_PLL_DDR_CONFIG_NINT_MASK;
|
||||
frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
||||
AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
|
||||
|
||||
ddr_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
|
||||
ddr_pll /= (1 << out_div);
|
||||
|
||||
clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
|
||||
|
||||
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||
}
|
||||
|
||||
void __init ath79_clocks_init(void)
|
||||
{
|
||||
if (soc_is_ar71xx())
|
||||
@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
|
||||
ar913x_clocks_init();
|
||||
else if (soc_is_ar933x())
|
||||
ar933x_clocks_init();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_clocks_init();
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
||||
@@ -1,9 +1,12 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X/AR913X common routines
|
||||
*
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask)
|
||||
reg = AR913X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar933x())
|
||||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
BUG();
|
||||
|
||||
@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask)
|
||||
reg = AR913X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar933x())
|
||||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
||||
@@ -89,7 +89,8 @@ void __init ath79_register_uart(void)
|
||||
|
||||
if (soc_is_ar71xx() ||
|
||||
soc_is_ar724x() ||
|
||||
soc_is_ar913x()) {
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar934x()) {
|
||||
ath79_uart_data[0].uartclk = clk_get_rate(clk);
|
||||
platform_device_register(&ath79_uart_device);
|
||||
} else if (soc_is_ar933x()) {
|
||||
|
||||
@@ -25,12 +25,10 @@ void __init ath79_register_gpio_keys_polled(int id,
|
||||
struct gpio_keys_button *p;
|
||||
int err;
|
||||
|
||||
p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
|
||||
p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
|
||||
if (!p)
|
||||
return;
|
||||
|
||||
memcpy(p, buttons, nbuttons * sizeof(*p));
|
||||
|
||||
pdev = platform_device_alloc("gpio-keys-polled", id);
|
||||
if (!pdev)
|
||||
goto err_free_buttons;
|
||||
|
||||
@@ -24,12 +24,10 @@ void __init ath79_register_leds_gpio(int id,
|
||||
struct gpio_led *p;
|
||||
int err;
|
||||
|
||||
p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
|
||||
p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
|
||||
if (!p)
|
||||
return;
|
||||
|
||||
memcpy(p, leds, num_leds * sizeof(*p));
|
||||
|
||||
pdev = platform_device_alloc("leds-gpio", id);
|
||||
if (!pdev)
|
||||
goto err_free_leds;
|
||||
|
||||
@@ -1,9 +1,12 @@
|
||||
/*
|
||||
* Atheros AR913X/AR933X SoC built-in WMAC device support
|
||||
*
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resources[] = {
|
||||
/* .start and .end fields are filled dynamically */
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = ATH79_CPU_IRQ_IP2,
|
||||
.end = ATH79_CPU_IRQ_IP2,
|
||||
/* .start and .end fields are filled dynamically */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(void)
|
||||
|
||||
ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||
}
|
||||
|
||||
|
||||
@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(void)
|
||||
|
||||
ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||
|
||||
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
|
||||
@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(void)
|
||||
ath79_wmac_data.external_reset = ar933x_wmac_reset;
|
||||
}
|
||||
|
||||
static void ar934x_wmac_setup(void)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
ath79_wmac_device.name = "ar934x_wmac";
|
||||
|
||||
ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||
ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||
|
||||
t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||
if (t & AR934X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_wmac_data.is_clk_25mhz = false;
|
||||
else
|
||||
ath79_wmac_data.is_clk_25mhz = true;
|
||||
}
|
||||
|
||||
void __init ath79_register_wmac(u8 *cal_data)
|
||||
{
|
||||
if (soc_is_ar913x())
|
||||
ar913x_wmac_setup();
|
||||
else if (soc_is_ar933x())
|
||||
ar933x_wmac_setup();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_wmac_setup();
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
||||
@@ -71,6 +71,9 @@ static void prom_putchar_init(void)
|
||||
case REV_ID_MAJOR_AR7241:
|
||||
case REV_ID_MAJOR_AR7242:
|
||||
case REV_ID_MAJOR_AR913X:
|
||||
case REV_ID_MAJOR_AR9341:
|
||||
case REV_ID_MAJOR_AR9342:
|
||||
case REV_ID_MAJOR_AR9344:
|
||||
_prom_putchar = prom_putchar_ar71xx;
|
||||
break;
|
||||
|
||||
|
||||
+46
-1
@@ -1,9 +1,12 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X/AR913X GPIO API support
|
||||
*
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(struct gpio_chip *chip,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
void __iomem *base = ath79_gpio_base;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||
|
||||
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
|
||||
base + AR71XX_GPIO_REG_OE);
|
||||
|
||||
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
void __iomem *base = ath79_gpio_base;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||
|
||||
if (value)
|
||||
__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
|
||||
else
|
||||
__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
|
||||
|
||||
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
|
||||
base + AR71XX_GPIO_REG_OE);
|
||||
|
||||
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct gpio_chip ath79_gpio_chip = {
|
||||
.label = "ath79",
|
||||
.get = ath79_gpio_get_value,
|
||||
@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
|
||||
ath79_gpio_count = AR913X_GPIO_COUNT;
|
||||
else if (soc_is_ar933x())
|
||||
ath79_gpio_count = AR933X_GPIO_COUNT;
|
||||
else if (soc_is_ar934x())
|
||||
ath79_gpio_count = AR934X_GPIO_COUNT;
|
||||
else
|
||||
BUG();
|
||||
|
||||
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
||||
if (soc_is_ar934x()) {
|
||||
ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
||||
ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
||||
}
|
||||
|
||||
err = gpiochip_add(&ath79_gpio_chip);
|
||||
if (err)
|
||||
|
||||
+125
-22
@@ -1,10 +1,11 @@
|
||||
/*
|
||||
* Atheros AR71xx/AR724x/AR913x specific interrupt handling
|
||||
*
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15 BSP
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
@@ -23,8 +24,8 @@
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include "common.h"
|
||||
|
||||
static unsigned int ath79_ip2_flush_reg;
|
||||
static unsigned int ath79_ip3_flush_reg;
|
||||
static void (*ath79_ip2_handler)(void);
|
||||
static void (*ath79_ip3_handler)(void);
|
||||
|
||||
static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(void)
|
||||
|
||||
if (soc_is_ar71xx() || soc_is_ar913x())
|
||||
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
|
||||
else if (soc_is_ar724x() || soc_is_ar933x())
|
||||
else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
|
||||
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||
else
|
||||
BUG();
|
||||
@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(void)
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
|
||||
}
|
||||
|
||||
static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 status;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
|
||||
|
||||
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
|
||||
generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||
} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
|
||||
generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
static void ar934x_ip2_irq_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ATH79_IP2_IRQ_BASE;
|
||||
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
||||
irq_set_chip_and_handler(i, &dummy_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long pending;
|
||||
@@ -152,10 +186,8 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(ATH79_CPU_IRQ_TIMER);
|
||||
|
||||
else if (pending & STATUSF_IP2) {
|
||||
ath79_ddr_wb_flush(ath79_ip2_flush_reg);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
else if (pending & STATUSF_IP2)
|
||||
ath79_ip2_handler();
|
||||
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(ATH79_CPU_IRQ_GE0);
|
||||
@@ -163,10 +195,8 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(ATH79_CPU_IRQ_GE1);
|
||||
|
||||
else if (pending & STATUSF_IP3) {
|
||||
ath79_ddr_wb_flush(ath79_ip3_flush_reg);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
else if (pending & STATUSF_IP3)
|
||||
ath79_ip3_handler();
|
||||
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(ATH79_CPU_IRQ_MISC);
|
||||
@@ -175,24 +205,97 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
/*
|
||||
* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
|
||||
* these devices typically allocate coherent DMA memory, however the
|
||||
* DMA controller may still have some unsynchronized data in the FIFO.
|
||||
* Issue a flush in the handlers to ensure that the driver sees
|
||||
* the update.
|
||||
*/
|
||||
static void ar71xx_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar724x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar913x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar933x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar934x_ip2_handler(void)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar71xx_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
|
||||
static void ar724x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
|
||||
static void ar913x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
|
||||
static void ar933x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
|
||||
static void ar934x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
if (soc_is_ar71xx()) {
|
||||
ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
|
||||
ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
|
||||
ath79_ip2_handler = ar71xx_ip2_handler;
|
||||
ath79_ip3_handler = ar71xx_ip3_handler;
|
||||
} else if (soc_is_ar724x()) {
|
||||
ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
|
||||
ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
|
||||
ath79_ip2_handler = ar724x_ip2_handler;
|
||||
ath79_ip3_handler = ar724x_ip3_handler;
|
||||
} else if (soc_is_ar913x()) {
|
||||
ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
|
||||
ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
|
||||
ath79_ip2_handler = ar913x_ip2_handler;
|
||||
ath79_ip3_handler = ar913x_ip3_handler;
|
||||
} else if (soc_is_ar933x()) {
|
||||
ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
|
||||
ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
|
||||
} else
|
||||
ath79_ip2_handler = ar933x_ip2_handler;
|
||||
ath79_ip3_handler = ar933x_ip3_handler;
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_ip2_handler = ar934x_ip2_handler;
|
||||
ath79_ip3_handler = ar934x_ip3_handler;
|
||||
} else {
|
||||
BUG();
|
||||
}
|
||||
|
||||
cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
|
||||
mips_cpu_irq_init();
|
||||
ath79_misc_irq_init();
|
||||
|
||||
if (soc_is_ar934x())
|
||||
ar934x_ip2_irq_init();
|
||||
}
|
||||
|
||||
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Atheros DB120 reference board support
|
||||
*
|
||||
* Copyright (c) 2011 Qualcomm Atheros
|
||||
* Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ath9k_platform.h>
|
||||
|
||||
#include "machtypes.h"
|
||||
#include "dev-gpio-buttons.h"
|
||||
#include "dev-leds-gpio.h"
|
||||
#include "dev-spi.h"
|
||||
#include "dev-wmac.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define DB120_GPIO_LED_WLAN_5G 12
|
||||
#define DB120_GPIO_LED_WLAN_2G 13
|
||||
#define DB120_GPIO_LED_STATUS 14
|
||||
#define DB120_GPIO_LED_WPS 15
|
||||
|
||||
#define DB120_GPIO_BTN_WPS 16
|
||||
|
||||
#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
|
||||
#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
|
||||
|
||||
#define DB120_WMAC_CALDATA_OFFSET 0x1000
|
||||
#define DB120_PCIE_CALDATA_OFFSET 0x5000
|
||||
|
||||
static struct gpio_led db120_leds_gpio[] __initdata = {
|
||||
{
|
||||
.name = "db120:green:status",
|
||||
.gpio = DB120_GPIO_LED_STATUS,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "db120:green:wps",
|
||||
.gpio = DB120_GPIO_LED_WPS,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "db120:green:wlan-5g",
|
||||
.gpio = DB120_GPIO_LED_WLAN_5G,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "db120:green:wlan-2g",
|
||||
.gpio = DB120_GPIO_LED_WLAN_2G,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_button db120_gpio_keys[] __initdata = {
|
||||
{
|
||||
.desc = "WPS button",
|
||||
.type = EV_KEY,
|
||||
.code = KEY_WPS_BUTTON,
|
||||
.debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
|
||||
.gpio = DB120_GPIO_BTN_WPS,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct spi_board_info db120_spi_info[] = {
|
||||
{
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.max_speed_hz = 25000000,
|
||||
.modalias = "s25sl064a",
|
||||
}
|
||||
};
|
||||
|
||||
static struct ath79_spi_platform_data db120_spi_data = {
|
||||
.bus_num = 0,
|
||||
.num_chipselect = 1,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct ath9k_platform_data db120_ath9k_data;
|
||||
|
||||
static int db120_pci_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
switch (PCI_SLOT(dev->devfn)) {
|
||||
case 0:
|
||||
dev->dev.platform_data = &db120_ath9k_data;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init db120_pci_init(u8 *eeprom)
|
||||
{
|
||||
memcpy(db120_ath9k_data.eeprom_data, eeprom,
|
||||
sizeof(db120_ath9k_data.eeprom_data));
|
||||
|
||||
ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
|
||||
ath79_register_pci();
|
||||
}
|
||||
#else
|
||||
static inline void db120_pci_init(void) {}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
static void __init db120_setup(void)
|
||||
{
|
||||
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||
|
||||
ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
|
||||
db120_leds_gpio);
|
||||
ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
|
||||
ARRAY_SIZE(db120_gpio_keys),
|
||||
db120_gpio_keys);
|
||||
ath79_register_spi(&db120_spi_data, db120_spi_info,
|
||||
ARRAY_SIZE(db120_spi_info));
|
||||
ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
|
||||
db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
|
||||
}
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
|
||||
db120_setup);
|
||||
@@ -19,6 +19,7 @@
|
||||
#include "dev-leds-gpio.h"
|
||||
#include "dev-spi.h"
|
||||
#include "dev-usb.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define PB44_GPIO_I2C_SCL 0
|
||||
#define PB44_GPIO_I2C_SDA 1
|
||||
@@ -114,6 +115,7 @@ static void __init pb44_init(void)
|
||||
ath79_register_spi(&pb44_spi_data, pb44_spi_info,
|
||||
ARRAY_SIZE(pb44_spi_info));
|
||||
ath79_register_usb();
|
||||
ath79_register_pci();
|
||||
}
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
|
||||
|
||||
@@ -12,16 +12,15 @@
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#include <linux/ath9k_platform.h>
|
||||
#include <asm/mach-ath79/pci-ath724x.h>
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#include <asm/mach-ath79/irq.h>
|
||||
|
||||
#include "machtypes.h"
|
||||
#include "dev-gpio-buttons.h"
|
||||
#include "dev-leds-gpio.h"
|
||||
#include "dev-spi.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define UBNT_XM_GPIO_LED_L1 0
|
||||
#define UBNT_XM_GPIO_LED_L2 1
|
||||
@@ -33,7 +32,6 @@
|
||||
#define UBNT_XM_KEYS_POLL_INTERVAL 20
|
||||
#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
|
||||
|
||||
#define UBNT_XM_PCI_IRQ 48
|
||||
#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
|
||||
|
||||
static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
|
||||
@@ -84,12 +82,27 @@ static struct ath79_spi_platform_data ubnt_xm_spi_data = {
|
||||
#ifdef CONFIG_PCI
|
||||
static struct ath9k_platform_data ubnt_xm_eeprom_data;
|
||||
|
||||
static struct ath724x_pci_data ubnt_xm_pci_data[] = {
|
||||
{
|
||||
.irq = UBNT_XM_PCI_IRQ,
|
||||
.pdata = &ubnt_xm_eeprom_data,
|
||||
},
|
||||
};
|
||||
static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
switch (PCI_SLOT(dev->devfn)) {
|
||||
case 0:
|
||||
dev->dev.platform_data = &ubnt_xm_eeprom_data;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ubnt_xm_pci_init(void)
|
||||
{
|
||||
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||
sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||
|
||||
ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
|
||||
ath79_register_pci();
|
||||
}
|
||||
#else
|
||||
static inline void ubnt_xm_pci_init(void) {}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
static void __init ubnt_xm_init(void)
|
||||
@@ -104,13 +117,7 @@ static void __init ubnt_xm_init(void)
|
||||
ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
|
||||
ARRAY_SIZE(ubnt_xm_spi_info));
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
|
||||
sizeof(ubnt_xm_eeprom_data.eeprom_data));
|
||||
|
||||
ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
ubnt_xm_pci_init();
|
||||
}
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_UBNT_XM,
|
||||
|
||||
@@ -18,6 +18,7 @@ enum ath79_mach_type {
|
||||
ATH79_MACH_GENERIC = 0,
|
||||
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||
ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||
ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
|
||||
};
|
||||
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X specific PCI setup code
|
||||
*
|
||||
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* Parts of this file are based on Atheros' 2.6.15 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/irq.h>
|
||||
#include <asm/mach-ath79/pci.h>
|
||||
#include "pci.h"
|
||||
|
||||
static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
|
||||
static unsigned ath79_pci_nr_irqs __initdata;
|
||||
|
||||
static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
|
||||
{
|
||||
.slot = 17,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(0),
|
||||
}, {
|
||||
.slot = 18,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(1),
|
||||
}, {
|
||||
.slot = 19,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(2),
|
||||
}
|
||||
};
|
||||
|
||||
static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
|
||||
{
|
||||
.slot = 0,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(0),
|
||||
}
|
||||
};
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||
{
|
||||
int irq = -1;
|
||||
int i;
|
||||
|
||||
if (ath79_pci_nr_irqs == 0 ||
|
||||
ath79_pci_irq_map == NULL) {
|
||||
if (soc_is_ar71xx()) {
|
||||
ath79_pci_irq_map = ar71xx_pci_irq_map;
|
||||
ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
|
||||
} else if (soc_is_ar724x() ||
|
||||
soc_is_ar9342() ||
|
||||
soc_is_ar9344()) {
|
||||
ath79_pci_irq_map = ar724x_pci_irq_map;
|
||||
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
|
||||
} else {
|
||||
pr_crit("pci %s: invalid irq map\n",
|
||||
pci_name((struct pci_dev *) dev));
|
||||
return irq;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ath79_pci_nr_irqs; i++) {
|
||||
const struct ath79_pci_irq *entry;
|
||||
|
||||
entry = &ath79_pci_irq_map[i];
|
||||
if (entry->slot == slot && entry->pin == pin) {
|
||||
irq = entry->irq;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (irq < 0)
|
||||
pr_crit("pci %s: no irq found for pin %u\n",
|
||||
pci_name((struct pci_dev *) dev), pin);
|
||||
else
|
||||
pr_info("pci %s: using irq %d for pin %u\n",
|
||||
pci_name((struct pci_dev *) dev), irq, pin);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
if (ath79_pci_plat_dev_init)
|
||||
return ath79_pci_plat_dev_init(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init ath79_pci_set_irq_map(unsigned nr_irqs,
|
||||
const struct ath79_pci_irq *map)
|
||||
{
|
||||
ath79_pci_nr_irqs = nr_irqs;
|
||||
ath79_pci_irq_map = map;
|
||||
}
|
||||
|
||||
void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
|
||||
{
|
||||
ath79_pci_plat_dev_init = func;
|
||||
}
|
||||
|
||||
int __init ath79_register_pci(void)
|
||||
{
|
||||
if (soc_is_ar71xx())
|
||||
return ar71xx_pcibios_init();
|
||||
|
||||
if (soc_is_ar724x())
|
||||
return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
|
||||
|
||||
if (soc_is_ar9342() || soc_is_ar9344()) {
|
||||
u32 bootstrap;
|
||||
|
||||
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
|
||||
return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user