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Merge tag 'regmap-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown: "A few fixes plus a few features, the most generally useful thing being the register paging support which can be used by quite a few devices: - Support for wake IRQs in regmap-irq - Support for register paging - Support for explicitly specified endianness, mostly for MMIO." * tag 'regmap-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: regmap: Fix incorrect arguments to kzalloc() call regmap: Add hook for printk logging for debugging during early init regmap: Fix work_buf switching for page update during virtual range access. regmap: Add support for register indirect addressing. regmap: Move lock out from internal function _regmap_update_bits(). regmap: mmio: Staticize regmap_mmio_gen_context() regmap: Remove warning on stubbed dev_get_regmap() regmap: Implement support for wake IRQs regmap: Don't try to map non-existant IRQs regmap: Constify regmap_irq_chip regmap: mmio: request native endian formatting regmap: allow busses to request formatting with specific endianness
This commit is contained in:
@@ -95,6 +95,9 @@ struct regmap {
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/* if set, converts bulk rw to single rw */
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bool use_single_rw;
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struct rb_root range_tree;
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void *selector_work_buf; /* Scratch buffer used for selector */
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};
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struct regcache_ops {
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@@ -115,6 +118,20 @@ bool regmap_precious(struct regmap *map, unsigned int reg);
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int _regmap_write(struct regmap *map, unsigned int reg,
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unsigned int val);
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struct regmap_range_node {
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struct rb_node node;
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unsigned int range_min;
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unsigned int range_max;
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unsigned int selector_reg;
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unsigned int selector_mask;
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int selector_shift;
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unsigned int window_start;
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unsigned int window_len;
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};
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#ifdef CONFIG_DEBUG_FS
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extern void regmap_debugfs_initcall(void);
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extern void regmap_debugfs_init(struct regmap *map, const char *name);
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@@ -24,14 +24,18 @@ struct regmap_irq_chip_data {
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struct mutex lock;
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struct regmap *map;
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struct regmap_irq_chip *chip;
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const struct regmap_irq_chip *chip;
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int irq_base;
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struct irq_domain *domain;
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int irq;
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int wake_count;
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unsigned int *status_buf;
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unsigned int *mask_buf;
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unsigned int *mask_buf_def;
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unsigned int *wake_buf;
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unsigned int irq_reg_stride;
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};
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@@ -71,6 +75,16 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
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d->chip->mask_base + (i * map->reg_stride));
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}
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/* If we've changed our wakeup count propagate it to the parent */
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if (d->wake_count < 0)
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for (i = d->wake_count; i < 0; i++)
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irq_set_irq_wake(d->irq, 0);
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else if (d->wake_count > 0)
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for (i = 0; i < d->wake_count; i++)
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irq_set_irq_wake(d->irq, 1);
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d->wake_count = 0;
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mutex_unlock(&d->lock);
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}
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@@ -92,18 +106,41 @@ static void regmap_irq_disable(struct irq_data *data)
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d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
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}
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static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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struct regmap *map = d->map;
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const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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if (!d->chip->wake_base)
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return -EINVAL;
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if (on) {
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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&= ~irq_data->mask;
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d->wake_count++;
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} else {
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d->wake_buf[irq_data->reg_offset / map->reg_stride]
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|= irq_data->mask;
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d->wake_count--;
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}
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return 0;
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}
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static struct irq_chip regmap_irq_chip = {
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.name = "regmap",
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.irq_bus_lock = regmap_irq_lock,
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.irq_bus_sync_unlock = regmap_irq_sync_unlock,
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.irq_disable = regmap_irq_disable,
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.irq_enable = regmap_irq_enable,
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.irq_set_wake = regmap_irq_set_wake,
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};
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static irqreturn_t regmap_irq_thread(int irq, void *d)
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{
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struct regmap_irq_chip_data *data = d;
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struct regmap_irq_chip *chip = data->chip;
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const struct regmap_irq_chip *chip = data->chip;
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struct regmap *map = data->map;
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int ret, i;
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bool handled = false;
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@@ -195,7 +232,7 @@ static struct irq_domain_ops regmap_domain_ops = {
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* register values used by the IRQ controller over suspend and resume.
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*/
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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int irq_base, const struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data)
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{
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struct regmap_irq_chip_data *d;
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@@ -240,6 +277,14 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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if (!d->mask_buf_def)
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goto err_alloc;
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if (chip->wake_base) {
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d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
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GFP_KERNEL);
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if (!d->wake_buf)
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goto err_alloc;
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}
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d->irq = irq;
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d->map = map;
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d->chip = chip;
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d->irq_base = irq_base;
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@@ -294,6 +339,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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err_domain:
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/* Should really dispose of the domain but... */
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err_alloc:
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kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_buf);
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@@ -315,6 +361,7 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
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free_irq(irq, d);
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/* We should unmap the domain but... */
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kfree(d->wake_buf);
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kfree(d->mask_buf_def);
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kfree(d->mask_buf);
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kfree(d->status_buf);
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@@ -346,6 +393,10 @@ EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
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*/
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int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
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{
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/* Handle holes in the IRQ list */
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if (!data->chip->irqs[irq].mask)
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return -EINVAL;
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return irq_create_mapping(data->domain, irq);
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}
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EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
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@@ -37,7 +37,7 @@ static int regmap_mmio_gather_write(void *context,
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BUG_ON(reg_size != 4);
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offset = be32_to_cpup(reg);
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offset = *(u32 *)reg;
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while (val_size) {
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switch (ctx->val_bytes) {
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@@ -45,14 +45,14 @@ static int regmap_mmio_gather_write(void *context,
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writeb(*(u8 *)val, ctx->regs + offset);
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break;
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case 2:
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writew(be16_to_cpup(val), ctx->regs + offset);
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writew(*(u16 *)val, ctx->regs + offset);
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break;
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case 4:
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writel(be32_to_cpup(val), ctx->regs + offset);
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writel(*(u32 *)val, ctx->regs + offset);
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break;
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#ifdef CONFIG_64BIT
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case 8:
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writeq(be64_to_cpup(val), ctx->regs + offset);
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writeq(*(u64 *)val, ctx->regs + offset);
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break;
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#endif
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default:
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@@ -83,7 +83,7 @@ static int regmap_mmio_read(void *context,
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BUG_ON(reg_size != 4);
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offset = be32_to_cpup(reg);
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offset = *(u32 *)reg;
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while (val_size) {
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switch (ctx->val_bytes) {
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@@ -91,14 +91,14 @@ static int regmap_mmio_read(void *context,
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*(u8 *)val = readb(ctx->regs + offset);
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break;
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case 2:
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*(u16 *)val = cpu_to_be16(readw(ctx->regs + offset));
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*(u16 *)val = readw(ctx->regs + offset);
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break;
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case 4:
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*(u32 *)val = cpu_to_be32(readl(ctx->regs + offset));
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*(u32 *)val = readl(ctx->regs + offset);
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break;
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#ifdef CONFIG_64BIT
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case 8:
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*(u64 *)val = cpu_to_be32(readq(ctx->regs + offset));
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*(u64 *)val = readq(ctx->regs + offset);
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break;
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#endif
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default:
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@@ -124,9 +124,11 @@ static struct regmap_bus regmap_mmio = {
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.gather_write = regmap_mmio_gather_write,
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.read = regmap_mmio_read,
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.free_context = regmap_mmio_free_context,
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.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
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.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
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};
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struct regmap_mmio_context *regmap_mmio_gen_context(void __iomem *regs,
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static struct regmap_mmio_context *regmap_mmio_gen_context(void __iomem *regs,
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const struct regmap_config *config)
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{
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struct regmap_mmio_context *ctx;
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@@ -162,7 +164,15 @@ struct regmap_mmio_context *regmap_mmio_gen_context(void __iomem *regs,
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if (config->reg_stride < min_stride)
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return ERR_PTR(-EINVAL);
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ctx = kzalloc(GFP_KERNEL, sizeof(*ctx));
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switch (config->reg_format_endian) {
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case REGMAP_ENDIAN_DEFAULT:
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case REGMAP_ENDIAN_NATIVE:
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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+320
-24
File diff suppressed because it is too large
Load Diff
+67
-2
@@ -14,12 +14,14 @@
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*/
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#include <linux/list.h>
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#include <linux/rbtree.h>
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struct module;
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struct device;
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struct i2c_client;
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struct spi_device;
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struct regmap;
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struct regmap_range_cfg;
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/* An enum of all the supported cache types */
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enum regcache_type {
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@@ -43,6 +45,14 @@ struct reg_default {
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#ifdef CONFIG_REGMAP
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enum regmap_endian {
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/* Unspecified -> 0 -> Backwards compatible default */
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REGMAP_ENDIAN_DEFAULT = 0,
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REGMAP_ENDIAN_BIG,
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REGMAP_ENDIAN_LITTLE,
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REGMAP_ENDIAN_NATIVE,
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};
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/**
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* Configuration for the register map of a device.
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*
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@@ -84,6 +94,15 @@ struct reg_default {
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* @reg_defaults_raw: Power on reset values for registers (for use with
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* register cache support).
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* @num_reg_defaults_raw: Number of elements in reg_defaults_raw.
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* @reg_format_endian: Endianness for formatted register addresses. If this is
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* DEFAULT, the @reg_format_endian_default value from the
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* regmap bus is used.
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* @val_format_endian: Endianness for formatted register values. If this is
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* DEFAULT, the @reg_format_endian_default value from the
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* regmap bus is used.
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*
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* @ranges: Array of configuration entries for virtual address ranges.
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* @num_ranges: Number of range configuration entries.
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*/
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struct regmap_config {
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const char *name;
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@@ -109,6 +128,43 @@ struct regmap_config {
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u8 write_flag_mask;
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bool use_single_rw;
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enum regmap_endian reg_format_endian;
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enum regmap_endian val_format_endian;
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const struct regmap_range_cfg *ranges;
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unsigned int n_ranges;
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};
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/**
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* Configuration for indirectly accessed or paged registers.
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* Registers, mapped to this virtual range, are accessed in two steps:
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* 1. page selector register update;
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* 2. access through data window registers.
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*
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* @range_min: Address of the lowest register address in virtual range.
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* @range_max: Address of the highest register in virtual range.
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*
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* @page_sel_reg: Register with selector field.
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* @page_sel_mask: Bit shift for selector value.
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* @page_sel_shift: Bit mask for selector value.
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*
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* @window_start: Address of first (lowest) register in data window.
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* @window_len: Number of registers in data window.
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*/
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struct regmap_range_cfg {
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/* Registers of virtual address range */
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unsigned int range_min;
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unsigned int range_max;
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/* Page selector for indirect addressing */
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unsigned int selector_reg;
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unsigned int selector_mask;
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int selector_shift;
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/* Data window (per each page) */
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unsigned int window_start;
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unsigned int window_len;
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};
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typedef int (*regmap_hw_write)(void *context, const void *data,
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@@ -133,6 +189,12 @@ typedef void (*regmap_hw_free_context)(void *context);
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* data.
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* @read_flag_mask: Mask to be set in the top byte of the register when doing
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* a read.
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* @reg_format_endian_default: Default endianness for formatted register
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* addresses. Used when the regmap_config specifies DEFAULT. If this is
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* DEFAULT, BIG is assumed.
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* @val_format_endian_default: Default endianness for formatted register
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* values. Used when the regmap_config specifies DEFAULT. If this is
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* DEFAULT, BIG is assumed.
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*/
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struct regmap_bus {
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bool fast_io;
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@@ -141,6 +203,8 @@ struct regmap_bus {
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regmap_hw_read read;
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regmap_hw_free_context free_context;
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u8 read_flag_mask;
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enum regmap_endian reg_format_endian_default;
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enum regmap_endian val_format_endian_default;
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};
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struct regmap *regmap_init(struct device *dev,
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@@ -219,6 +283,7 @@ struct regmap_irq {
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* @status_base: Base status register address.
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* @mask_base: Base mask register address.
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* @ack_base: Base ack address. If zero then the chip is clear on read.
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* @wake_base: Base address for wake enables. If zero unsupported.
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* @irq_reg_stride: Stride to use for chips where registers are not contiguous.
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*
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* @num_regs: Number of registers in each control bank.
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@@ -232,6 +297,7 @@ struct regmap_irq_chip {
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unsigned int status_base;
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unsigned int mask_base;
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unsigned int ack_base;
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unsigned int wake_base;
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unsigned int irq_reg_stride;
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int num_regs;
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@@ -243,7 +309,7 @@ struct regmap_irq_chip {
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struct regmap_irq_chip_data;
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int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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int irq_base, struct regmap_irq_chip *chip,
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int irq_base, const struct regmap_irq_chip *chip,
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struct regmap_irq_chip_data **data);
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void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
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int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data);
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@@ -361,7 +427,6 @@ static inline int regmap_register_patch(struct regmap *map,
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static inline struct regmap *dev_get_regmap(struct device *dev,
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const char *name)
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{
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WARN_ONCE(1, "regmap API is disabled");
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return NULL;
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}
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