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[PATCH] ehea: IBM eHEA Ethernet Device Driver
Hi Jeff, I fixed the __iomem issue and tested the driver with sparse. Looks good so far. Thanks for your effort. Jan-Bernd Themann Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com> drivers/net/Kconfig | 9 drivers/net/Makefile | 1 drivers/net/ehea/Makefile | 6 drivers/net/ehea/ehea.h | 447 ++++++ drivers/net/ehea/ehea_ethtool.c | 294 ++++ drivers/net/ehea/ehea_hcall.h | 51 drivers/net/ehea/ehea_hw.h | 287 ++++ drivers/net/ehea/ehea_main.c | 2654 ++++++++++++++++++++++++++++++++++++++++ drivers/net/ehea/ehea_phyp.c | 705 ++++++++++ drivers/net/ehea/ehea_phyp.h | 455 ++++++ drivers/net/ehea/ehea_qmr.c | 582 ++++++++ drivers/net/ehea/ehea_qmr.h | 358 +++++ 12 files changed, 5849 insertions(+) Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Jan-Bernd Themann
committed by
Jeff Garzik
Jeff Garzik
parent
7de745e562
commit
7a29108322
@@ -2360,6 +2360,15 @@ config CHELSIO_T1
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To compile this driver as a module, choose M here: the module
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will be called cxgb.
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config EHEA
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tristate "eHEA Ethernet support"
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depends on IBMEBUS
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---help---
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This driver supports the IBM pSeries eHEA ethernet adapter.
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To compile the driver as a module, choose M here. The module
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will be called ehea.
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config IXGB
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tristate "Intel(R) PRO/10GbE support"
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depends on PCI
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@@ -6,6 +6,7 @@ obj-$(CONFIG_E1000) += e1000/
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obj-$(CONFIG_IBM_EMAC) += ibm_emac/
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obj-$(CONFIG_IXGB) += ixgb/
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obj-$(CONFIG_CHELSIO_T1) += chelsio/
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obj-$(CONFIG_EHEA) += ehea/
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obj-$(CONFIG_BONDING) += bonding/
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obj-$(CONFIG_GIANFAR) += gianfar_driver.o
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@@ -0,0 +1,6 @@
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#
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# Makefile for the eHEA ethernet device driver for IBM eServer System p
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#
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ehea-y = ehea_main.o ehea_phyp.o ehea_qmr.o ehea_ethtool.o ehea_phyp.o
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obj-$(CONFIG_EHEA) += ehea.o
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@@ -0,0 +1,447 @@
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/*
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* linux/drivers/net/ehea/ehea.h
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*
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* eHEA ethernet device driver for IBM eServer System p
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*
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* (C) Copyright IBM Corp. 2006
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*
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* Authors:
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* Christoph Raisch <raisch@de.ibm.com>
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* Jan-Bernd Themann <themann@de.ibm.com>
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* Thomas Klein <tklein@de.ibm.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __EHEA_H__
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#define __EHEA_H__
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#include <linux/module.h>
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#include <linux/ethtool.h>
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#include <linux/vmalloc.h>
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#include <linux/if_vlan.h>
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#include <asm/ibmebus.h>
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#include <asm/abs_addr.h>
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#include <asm/io.h>
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#define DRV_NAME "ehea"
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#define DRV_VERSION "EHEA_0027"
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#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
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| NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
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#define EHEA_MAX_ENTRIES_RQ1 32767
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#define EHEA_MAX_ENTRIES_RQ2 16383
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#define EHEA_MAX_ENTRIES_RQ3 16383
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#define EHEA_MAX_ENTRIES_SQ 32767
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#define EHEA_MIN_ENTRIES_QP 127
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#define EHEA_NUM_TX_QP 1
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#ifdef EHEA_SMALL_QUEUES
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#define EHEA_MAX_CQE_COUNT 1023
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#define EHEA_DEF_ENTRIES_SQ 1023
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#define EHEA_DEF_ENTRIES_RQ1 4095
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#define EHEA_DEF_ENTRIES_RQ2 1023
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#define EHEA_DEF_ENTRIES_RQ3 1023
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#else
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#define EHEA_MAX_CQE_COUNT 32000
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#define EHEA_DEF_ENTRIES_SQ 16000
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#define EHEA_DEF_ENTRIES_RQ1 32080
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#define EHEA_DEF_ENTRIES_RQ2 4020
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#define EHEA_DEF_ENTRIES_RQ3 4020
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#endif
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#define EHEA_MAX_ENTRIES_EQ 20
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#define EHEA_SG_SQ 2
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#define EHEA_SG_RQ1 1
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#define EHEA_SG_RQ2 0
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#define EHEA_SG_RQ3 0
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#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
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#define EHEA_RQ2_PKT_SIZE 1522
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#define EHEA_L_PKT_SIZE 256 /* low latency */
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#define EHEA_POLL_MAX_RWQE 1000
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/* Send completion signaling */
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#define EHEA_SIG_IV_LONG 1
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/* Protection Domain Identifier */
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#define EHEA_PD_ID 0xaabcdeff
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#define EHEA_RQ2_THRESHOLD 1
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#define EHEA_RQ3_THRESHOLD 9 /* use RQ3 threshold of 1522 bytes */
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#define EHEA_SPEED_10G 10000
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#define EHEA_SPEED_1G 1000
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#define EHEA_SPEED_100M 100
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#define EHEA_SPEED_10M 10
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#define EHEA_SPEED_AUTONEG 0
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/* Broadcast/Multicast registration types */
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#define EHEA_BCMC_SCOPE_ALL 0x08
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#define EHEA_BCMC_SCOPE_SINGLE 0x00
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#define EHEA_BCMC_MULTICAST 0x04
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#define EHEA_BCMC_BROADCAST 0x00
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#define EHEA_BCMC_UNTAGGED 0x02
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#define EHEA_BCMC_TAGGED 0x00
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#define EHEA_BCMC_VLANID_ALL 0x01
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#define EHEA_BCMC_VLANID_SINGLE 0x00
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/* Use this define to kmallocate pHYP control blocks */
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#define H_CB_ALIGNMENT 4096
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#define EHEA_CACHE_LINE 128
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/* Memory Regions */
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#define EHEA_MR_MAX_TX_PAGES 20
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#define EHEA_MR_TX_DATA_PN 3
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#define EHEA_MR_ACC_CTRL 0x00800000
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#define EHEA_RWQES_PER_MR_RQ2 10
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#define EHEA_RWQES_PER_MR_RQ3 10
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#define EHEA_WATCH_DOG_TIMEOUT 10*HZ
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/* utility functions */
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#define ehea_info(fmt, args...) \
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printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args)
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#define ehea_error(fmt, args...) \
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printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args)
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#ifdef DEBUG
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#define ehea_debug(fmt, args...) \
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printk(KERN_DEBUG DRV_NAME ": " fmt, ## args)
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#else
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#define ehea_debug(fmt, args...) do {} while (0)
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#endif
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void ehea_dump(void *adr, int len, char *msg);
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#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
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#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
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#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
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#define EHEA_BMASK_MASK(mask) \
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(0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
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#define EHEA_BMASK_SET(mask, value) \
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((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
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#define EHEA_BMASK_GET(mask, value) \
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(EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
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/*
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* Generic ehea page
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*/
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struct ehea_page {
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u8 entries[PAGE_SIZE];
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};
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/*
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* Generic queue in linux kernel virtual memory
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*/
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struct hw_queue {
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u64 current_q_offset; /* current queue entry */
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struct ehea_page **queue_pages; /* array of pages belonging to queue */
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u32 qe_size; /* queue entry size */
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u32 queue_length; /* queue length allocated in bytes */
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u32 pagesize;
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u32 toggle_state; /* toggle flag - per page */
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u32 reserved; /* 64 bit alignment */
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};
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/*
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* For pSeries this is a 64bit memory address where
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* I/O memory is mapped into CPU address space
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*/
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struct h_epa {
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void __iomem *addr;
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};
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struct h_epa_user {
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u64 addr;
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};
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struct h_epas {
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struct h_epa kernel; /* kernel space accessible resource,
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set to 0 if unused */
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struct h_epa_user user; /* user space accessible resource
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set to 0 if unused */
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};
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struct ehea_qp;
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struct ehea_cq;
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struct ehea_eq;
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struct ehea_port;
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struct ehea_av;
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/*
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* Queue attributes passed to ehea_create_qp()
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*/
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struct ehea_qp_init_attr {
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/* input parameter */
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u32 qp_token; /* queue token */
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u8 low_lat_rq1;
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u8 signalingtype; /* cqe generation flag */
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u8 rq_count; /* num of receive queues */
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u8 eqe_gen; /* eqe generation flag */
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u16 max_nr_send_wqes; /* max number of send wqes */
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u16 max_nr_rwqes_rq1; /* max number of receive wqes */
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u16 max_nr_rwqes_rq2;
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u16 max_nr_rwqes_rq3;
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u8 wqe_size_enc_sq;
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u8 wqe_size_enc_rq1;
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u8 wqe_size_enc_rq2;
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u8 wqe_size_enc_rq3;
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u8 swqe_imm_data_len; /* immediate data length for swqes */
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u16 port_nr;
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u16 rq2_threshold;
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u16 rq3_threshold;
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u64 send_cq_handle;
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u64 recv_cq_handle;
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u64 aff_eq_handle;
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/* output parameter */
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u32 qp_nr;
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u16 act_nr_send_wqes;
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u16 act_nr_rwqes_rq1;
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u16 act_nr_rwqes_rq2;
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u16 act_nr_rwqes_rq3;
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u8 act_wqe_size_enc_sq;
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u8 act_wqe_size_enc_rq1;
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u8 act_wqe_size_enc_rq2;
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u8 act_wqe_size_enc_rq3;
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u32 nr_sq_pages;
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u32 nr_rq1_pages;
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u32 nr_rq2_pages;
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u32 nr_rq3_pages;
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u32 liobn_sq;
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u32 liobn_rq1;
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u32 liobn_rq2;
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u32 liobn_rq3;
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};
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/*
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* Event Queue attributes, passed as paramter
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*/
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struct ehea_eq_attr {
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u32 type;
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u32 max_nr_of_eqes;
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u8 eqe_gen; /* generate eqe flag */
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u64 eq_handle;
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u32 act_nr_of_eqes;
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u32 nr_pages;
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u32 ist1; /* Interrupt service token */
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u32 ist2;
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u32 ist3;
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u32 ist4;
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};
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/*
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* Event Queue
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*/
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struct ehea_eq {
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struct ehea_adapter *adapter;
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struct hw_queue hw_queue;
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u64 fw_handle;
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struct h_epas epas;
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spinlock_t spinlock;
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struct ehea_eq_attr attr;
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};
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/*
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* HEA Queues
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*/
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struct ehea_qp {
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struct ehea_adapter *adapter;
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u64 fw_handle; /* QP handle for firmware calls */
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struct hw_queue hw_squeue;
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struct hw_queue hw_rqueue1;
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struct hw_queue hw_rqueue2;
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struct hw_queue hw_rqueue3;
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struct h_epas epas;
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struct ehea_qp_init_attr init_attr;
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};
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/*
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* Completion Queue attributes
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*/
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struct ehea_cq_attr {
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/* input parameter */
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u32 max_nr_of_cqes;
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u32 cq_token;
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u64 eq_handle;
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/* output parameter */
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u32 act_nr_of_cqes;
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u32 nr_pages;
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};
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/*
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* Completion Queue
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*/
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struct ehea_cq {
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struct ehea_adapter *adapter;
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u64 fw_handle;
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struct hw_queue hw_queue;
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struct h_epas epas;
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struct ehea_cq_attr attr;
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};
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/*
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* Memory Region
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*/
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struct ehea_mr {
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u64 handle;
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u64 vaddr;
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u32 lkey;
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};
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/*
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* Port state information
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*/
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struct port_state {
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int poll_max_processed;
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int poll_receive_errors;
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int ehea_poll;
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int queue_stopped;
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int min_swqe_avail;
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u64 sqc_stop_sum;
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int pkt_send;
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int pkt_xmit;
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int send_tasklet;
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int nwqe;
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};
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#define EHEA_IRQ_NAME_SIZE 20
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/*
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* Queue SKB Array
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*/
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struct ehea_q_skb_arr {
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struct sk_buff **arr; /* skb array for queue */
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int len; /* array length */
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int index; /* array index */
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int os_skbs; /* rq2/rq3 only: outstanding skbs */
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};
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/*
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* Port resources
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*/
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struct ehea_port_res {
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struct ehea_mr send_mr; /* send memory region */
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struct ehea_mr recv_mr; /* receive memory region */
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spinlock_t xmit_lock;
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struct ehea_port *port;
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char int_recv_name[EHEA_IRQ_NAME_SIZE];
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char int_send_name[EHEA_IRQ_NAME_SIZE];
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struct ehea_qp *qp;
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struct ehea_cq *send_cq;
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struct ehea_cq *recv_cq;
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struct ehea_eq *send_eq;
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struct ehea_eq *recv_eq;
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spinlock_t send_lock;
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struct ehea_q_skb_arr rq1_skba;
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struct ehea_q_skb_arr rq2_skba;
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struct ehea_q_skb_arr rq3_skba;
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struct ehea_q_skb_arr sq_skba;
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spinlock_t netif_queue;
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int queue_stopped;
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int swqe_refill_th;
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atomic_t swqe_avail;
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int swqe_ll_count;
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int swqe_count;
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u32 swqe_id_counter;
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u64 tx_packets;
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struct tasklet_struct send_comp_task;
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spinlock_t recv_lock;
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struct port_state p_state;
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u64 rx_packets;
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u32 poll_counter;
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};
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struct ehea_adapter {
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u64 handle;
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u8 num_ports;
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struct ehea_port *port[16];
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struct ehea_eq *neq; /* notification event queue */
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struct workqueue_struct *ehea_wq;
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struct tasklet_struct neq_tasklet;
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struct ehea_mr mr;
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u32 pd; /* protection domain */
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u64 max_mc_mac; /* max number of multicast mac addresses */
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};
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struct ehea_mc_list {
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struct list_head list;
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u64 macaddr;
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};
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#define EHEA_PORT_UP 1
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#define EHEA_PORT_DOWN 0
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#define EHEA_MAX_PORT_RES 16
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struct ehea_port {
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struct ehea_adapter *adapter; /* adapter that owns this port */
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struct net_device *netdev;
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struct net_device_stats stats;
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struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
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struct device_node *of_dev_node; /* Open Firmware Device Node */
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struct ehea_mc_list *mc_list; /* Multicast MAC addresses */
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struct vlan_group *vgrp;
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struct ehea_eq *qp_eq;
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struct work_struct reset_task;
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struct semaphore port_lock;
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char int_aff_name[EHEA_IRQ_NAME_SIZE];
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int allmulti; /* Indicates IFF_ALLMULTI state */
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int promisc; /* Indicates IFF_PROMISC state */
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int num_add_tx_qps;
|
||||
int resets;
|
||||
u64 mac_addr;
|
||||
u32 logical_port_id;
|
||||
u32 port_speed;
|
||||
u32 msg_enable;
|
||||
u32 sig_comp_iv;
|
||||
u32 state;
|
||||
u8 full_duplex;
|
||||
u8 autoneg;
|
||||
u8 num_def_qps;
|
||||
};
|
||||
|
||||
struct port_res_cfg {
|
||||
int max_entries_rcq;
|
||||
int max_entries_scq;
|
||||
int max_entries_sq;
|
||||
int max_entries_rq1;
|
||||
int max_entries_rq2;
|
||||
int max_entries_rq3;
|
||||
};
|
||||
|
||||
|
||||
void ehea_set_ethtool_ops(struct net_device *netdev);
|
||||
int ehea_sense_port_attr(struct ehea_port *port);
|
||||
int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
|
||||
|
||||
#endif /* __EHEA_H__ */
|
||||
@@ -0,0 +1,294 @@
|
||||
/*
|
||||
* linux/drivers/net/ehea/ehea_ethtool.c
|
||||
*
|
||||
* eHEA ethernet device driver for IBM eServer System p
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2006
|
||||
*
|
||||
* Authors:
|
||||
* Christoph Raisch <raisch@de.ibm.com>
|
||||
* Jan-Bernd Themann <themann@de.ibm.com>
|
||||
* Thomas Klein <tklein@de.ibm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include "ehea.h"
|
||||
#include "ehea_phyp.h"
|
||||
|
||||
static int ehea_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||
{
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = ehea_sense_port_attr(port);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (netif_carrier_ok(dev)) {
|
||||
switch(port->port_speed) {
|
||||
case EHEA_SPEED_10M: cmd->speed = SPEED_10; break;
|
||||
case EHEA_SPEED_100M: cmd->speed = SPEED_100; break;
|
||||
case EHEA_SPEED_1G: cmd->speed = SPEED_1000; break;
|
||||
case EHEA_SPEED_10G: cmd->speed = SPEED_10000; break;
|
||||
}
|
||||
cmd->duplex = port->full_duplex == 1 ?
|
||||
DUPLEX_FULL : DUPLEX_HALF;
|
||||
} else {
|
||||
cmd->speed = -1;
|
||||
cmd->duplex = -1;
|
||||
}
|
||||
|
||||
cmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_1000baseT_Full
|
||||
| SUPPORTED_100baseT_Full | SUPPORTED_100baseT_Half
|
||||
| SUPPORTED_10baseT_Full | SUPPORTED_10baseT_Half
|
||||
| SUPPORTED_Autoneg | SUPPORTED_FIBRE);
|
||||
|
||||
cmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_Autoneg
|
||||
| ADVERTISED_FIBRE);
|
||||
|
||||
cmd->port = PORT_FIBRE;
|
||||
cmd->autoneg = port->autoneg == 1 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ehea_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||
{
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
int ret = 0;
|
||||
u32 sp;
|
||||
|
||||
if (cmd->autoneg == AUTONEG_ENABLE) {
|
||||
sp = EHEA_SPEED_AUTONEG;
|
||||
goto doit;
|
||||
}
|
||||
|
||||
switch(cmd->speed) {
|
||||
case SPEED_10:
|
||||
if (cmd->duplex == DUPLEX_FULL)
|
||||
sp = H_SPEED_10M_F;
|
||||
else
|
||||
sp = H_SPEED_10M_H;
|
||||
break;
|
||||
|
||||
case SPEED_100:
|
||||
if (cmd->duplex == DUPLEX_FULL)
|
||||
sp = H_SPEED_100M_F;
|
||||
else
|
||||
sp = H_SPEED_100M_H;
|
||||
break;
|
||||
|
||||
case SPEED_1000:
|
||||
if (cmd->duplex == DUPLEX_FULL)
|
||||
sp = H_SPEED_1G_F;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
case SPEED_10000:
|
||||
if (cmd->duplex == DUPLEX_FULL)
|
||||
sp = H_SPEED_10G_F;
|
||||
else
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
goto out;
|
||||
doit:
|
||||
ret = ehea_set_portspeed(port, sp);
|
||||
|
||||
if (!ret)
|
||||
ehea_info("%s: Port speed succesfully set: %dMbps "
|
||||
"%s Duplex",
|
||||
port->netdev->name, port->port_speed,
|
||||
port->full_duplex == 1 ? "Full" : "Half");
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ehea_nway_reset(struct net_device *dev)
|
||||
{
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = ehea_set_portspeed(port, EHEA_SPEED_AUTONEG);
|
||||
|
||||
if (!ret)
|
||||
ehea_info("%s: Port speed succesfully set: %dMbps "
|
||||
"%s Duplex",
|
||||
port->netdev->name, port->port_speed,
|
||||
port->full_duplex == 1 ? "Full" : "Half");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ehea_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strlcpy(info->driver, DRV_NAME, sizeof(info->driver) - 1);
|
||||
strlcpy(info->version, DRV_VERSION, sizeof(info->version) - 1);
|
||||
}
|
||||
|
||||
static u32 ehea_get_msglevel(struct net_device *dev)
|
||||
{
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
return port->msg_enable;
|
||||
}
|
||||
|
||||
static void ehea_set_msglevel(struct net_device *dev, u32 value)
|
||||
{
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
port->msg_enable = value;
|
||||
}
|
||||
|
||||
static u32 ehea_get_rx_csum(struct net_device *dev)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static char ehea_ethtool_stats_keys[][ETH_GSTRING_LEN] = {
|
||||
{"poll_max_processed"},
|
||||
{"queue_stopped"},
|
||||
{"min_swqe_avail"},
|
||||
{"poll_receive_err"},
|
||||
{"pkt_send"},
|
||||
{"pkt_xmit"},
|
||||
{"send_tasklet"},
|
||||
{"ehea_poll"},
|
||||
{"nwqe"},
|
||||
{"swqe_available_0"},
|
||||
{"sig_comp_iv"},
|
||||
{"swqe_refill_th"},
|
||||
{"port resets"},
|
||||
{"rxo"},
|
||||
{"rx64"},
|
||||
{"rx65"},
|
||||
{"rx128"},
|
||||
{"rx256"},
|
||||
{"rx512"},
|
||||
{"rx1024"},
|
||||
{"txo"},
|
||||
{"tx64"},
|
||||
{"tx65"},
|
||||
{"tx128"},
|
||||
{"tx256"},
|
||||
{"tx512"},
|
||||
{"tx1024"},
|
||||
};
|
||||
|
||||
static void ehea_get_strings(struct net_device *dev, u32 stringset, u8 *data)
|
||||
{
|
||||
if (stringset == ETH_SS_STATS) {
|
||||
memcpy(data, &ehea_ethtool_stats_keys,
|
||||
sizeof(ehea_ethtool_stats_keys));
|
||||
}
|
||||
}
|
||||
|
||||
static int ehea_get_stats_count(struct net_device *dev)
|
||||
{
|
||||
return ARRAY_SIZE(ehea_ethtool_stats_keys);
|
||||
}
|
||||
|
||||
static void ehea_get_ethtool_stats(struct net_device *dev,
|
||||
struct ethtool_stats *stats, u64 *data)
|
||||
{
|
||||
u64 hret;
|
||||
int i;
|
||||
struct ehea_port *port = netdev_priv(dev);
|
||||
struct ehea_adapter *adapter = port->adapter;
|
||||
struct ehea_port_res *pr = &port->port_res[0];
|
||||
struct port_state *p_state = &pr->p_state;
|
||||
struct hcp_ehea_port_cb6 *cb6;
|
||||
|
||||
for (i = 0; i < ehea_get_stats_count(dev); i++)
|
||||
data[i] = 0;
|
||||
|
||||
i = 0;
|
||||
|
||||
data[i++] = p_state->poll_max_processed;
|
||||
data[i++] = p_state->queue_stopped;
|
||||
data[i++] = p_state->min_swqe_avail;
|
||||
data[i++] = p_state->poll_receive_errors;
|
||||
data[i++] = p_state->pkt_send;
|
||||
data[i++] = p_state->pkt_xmit;
|
||||
data[i++] = p_state->send_tasklet;
|
||||
data[i++] = p_state->ehea_poll;
|
||||
data[i++] = p_state->nwqe;
|
||||
data[i++] = atomic_read(&port->port_res[0].swqe_avail);
|
||||
data[i++] = port->sig_comp_iv;
|
||||
data[i++] = port->port_res[0].swqe_refill_th;
|
||||
data[i++] = port->resets;
|
||||
|
||||
cb6 = kzalloc(H_CB_ALIGNMENT, GFP_KERNEL);
|
||||
if (!cb6) {
|
||||
ehea_error("no mem for cb6");
|
||||
return;
|
||||
}
|
||||
|
||||
hret = ehea_h_query_ehea_port(adapter->handle, port->logical_port_id,
|
||||
H_PORT_CB6, H_PORT_CB6_ALL, cb6);
|
||||
if (netif_msg_hw(port))
|
||||
ehea_dump(cb6, sizeof(*cb6), "ehea_get_ethtool_stats");
|
||||
|
||||
if (hret == H_SUCCESS) {
|
||||
data[i++] = cb6->rxo;
|
||||
data[i++] = cb6->rx64;
|
||||
data[i++] = cb6->rx65;
|
||||
data[i++] = cb6->rx128;
|
||||
data[i++] = cb6->rx256;
|
||||
data[i++] = cb6->rx512;
|
||||
data[i++] = cb6->rx1024;
|
||||
data[i++] = cb6->txo;
|
||||
data[i++] = cb6->tx64;
|
||||
data[i++] = cb6->tx65;
|
||||
data[i++] = cb6->tx128;
|
||||
data[i++] = cb6->tx256;
|
||||
data[i++] = cb6->tx512;
|
||||
data[i++] = cb6->tx1024;
|
||||
} else
|
||||
ehea_error("query_ehea_port failed");
|
||||
|
||||
kfree(cb6);
|
||||
}
|
||||
|
||||
struct ethtool_ops ehea_ethtool_ops = {
|
||||
.get_settings = ehea_get_settings,
|
||||
.get_drvinfo = ehea_get_drvinfo,
|
||||
.get_msglevel = ehea_get_msglevel,
|
||||
.set_msglevel = ehea_set_msglevel,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_tx_csum = ethtool_op_get_tx_csum,
|
||||
.get_sg = ethtool_op_get_sg,
|
||||
.get_tso = ethtool_op_get_tso,
|
||||
.set_tso = ethtool_op_set_tso,
|
||||
.get_strings = ehea_get_strings,
|
||||
.get_stats_count = ehea_get_stats_count,
|
||||
.get_ethtool_stats = ehea_get_ethtool_stats,
|
||||
.get_rx_csum = ehea_get_rx_csum,
|
||||
.set_settings = ehea_set_settings,
|
||||
.nway_reset = ehea_nway_reset, /* Restart autonegotiation */
|
||||
};
|
||||
|
||||
void ehea_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
SET_ETHTOOL_OPS(netdev, &ehea_ethtool_ops);
|
||||
}
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* linux/drivers/net/ehea/ehea_hcall.h
|
||||
*
|
||||
* eHEA ethernet device driver for IBM eServer System p
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2006
|
||||
*
|
||||
* Authors:
|
||||
* Christoph Raisch <raisch@de.ibm.com>
|
||||
* Jan-Bernd Themann <themann@de.ibm.com>
|
||||
* Thomas Klein <tklein@de.ibm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __EHEA_HCALL_H__
|
||||
#define __EHEA_HCALL_H__
|
||||
|
||||
/**
|
||||
* This file contains HCALL defines that are to be included in the appropriate
|
||||
* kernel files later
|
||||
*/
|
||||
|
||||
#define H_ALLOC_HEA_RESOURCE 0x278
|
||||
#define H_MODIFY_HEA_QP 0x250
|
||||
#define H_QUERY_HEA_QP 0x254
|
||||
#define H_QUERY_HEA 0x258
|
||||
#define H_QUERY_HEA_PORT 0x25C
|
||||
#define H_MODIFY_HEA_PORT 0x260
|
||||
#define H_REG_BCMC 0x264
|
||||
#define H_DEREG_BCMC 0x268
|
||||
#define H_REGISTER_HEA_RPAGES 0x26C
|
||||
#define H_DISABLE_AND_GET_HEA 0x270
|
||||
#define H_GET_HEA_INFO 0x274
|
||||
#define H_ADD_CONN 0x284
|
||||
#define H_DEL_CONN 0x288
|
||||
|
||||
#endif /* __EHEA_HCALL_H__ */
|
||||
@@ -0,0 +1,287 @@
|
||||
/*
|
||||
* linux/drivers/net/ehea/ehea_hw.h
|
||||
*
|
||||
* eHEA ethernet device driver for IBM eServer System p
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2006
|
||||
*
|
||||
* Authors:
|
||||
* Christoph Raisch <raisch@de.ibm.com>
|
||||
* Jan-Bernd Themann <themann@de.ibm.com>
|
||||
* Thomas Klein <tklein@de.ibm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __EHEA_HW_H__
|
||||
#define __EHEA_HW_H__
|
||||
|
||||
#define QPX_SQA_VALUE EHEA_BMASK_IBM(48,63)
|
||||
#define QPX_RQ1A_VALUE EHEA_BMASK_IBM(48,63)
|
||||
#define QPX_RQ2A_VALUE EHEA_BMASK_IBM(48,63)
|
||||
#define QPX_RQ3A_VALUE EHEA_BMASK_IBM(48,63)
|
||||
|
||||
#define QPTEMM_OFFSET(x) offsetof(struct ehea_qptemm, x)
|
||||
|
||||
struct ehea_qptemm {
|
||||
u64 qpx_hcr;
|
||||
u64 qpx_c;
|
||||
u64 qpx_herr;
|
||||
u64 qpx_aer;
|
||||
u64 qpx_sqa;
|
||||
u64 qpx_sqc;
|
||||
u64 qpx_rq1a;
|
||||
u64 qpx_rq1c;
|
||||
u64 qpx_st;
|
||||
u64 qpx_aerr;
|
||||
u64 qpx_tenure;
|
||||
u64 qpx_reserved1[(0x098 - 0x058) / 8];
|
||||
u64 qpx_portp;
|
||||
u64 qpx_reserved2[(0x100 - 0x0A0) / 8];
|
||||
u64 qpx_t;
|
||||
u64 qpx_sqhp;
|
||||
u64 qpx_sqptp;
|
||||
u64 qpx_reserved3[(0x140 - 0x118) / 8];
|
||||
u64 qpx_sqwsize;
|
||||
u64 qpx_reserved4[(0x170 - 0x148) / 8];
|
||||
u64 qpx_sqsize;
|
||||
u64 qpx_reserved5[(0x1B0 - 0x178) / 8];
|
||||
u64 qpx_sigt;
|
||||
u64 qpx_wqecnt;
|
||||
u64 qpx_rq1hp;
|
||||
u64 qpx_rq1ptp;
|
||||
u64 qpx_rq1size;
|
||||
u64 qpx_reserved6[(0x220 - 0x1D8) / 8];
|
||||
u64 qpx_rq1wsize;
|
||||
u64 qpx_reserved7[(0x240 - 0x228) / 8];
|
||||
u64 qpx_pd;
|
||||
u64 qpx_scqn;
|
||||
u64 qpx_rcqn;
|
||||
u64 qpx_aeqn;
|
||||
u64 reserved49;
|
||||
u64 qpx_ram;
|
||||
u64 qpx_reserved8[(0x300 - 0x270) / 8];
|
||||
u64 qpx_rq2a;
|
||||
u64 qpx_rq2c;
|
||||
u64 qpx_rq2hp;
|
||||
u64 qpx_rq2ptp;
|
||||
u64 qpx_rq2size;
|
||||
u64 qpx_rq2wsize;
|
||||
u64 qpx_rq2th;
|
||||
u64 qpx_rq3a;
|
||||
u64 qpx_rq3c;
|
||||
u64 qpx_rq3hp;
|
||||
u64 qpx_rq3ptp;
|
||||
u64 qpx_rq3size;
|
||||
u64 qpx_rq3wsize;
|
||||
u64 qpx_rq3th;
|
||||
u64 qpx_lpn;
|
||||
u64 qpx_reserved9[(0x400 - 0x378) / 8];
|
||||
u64 reserved_ext[(0x500 - 0x400) / 8];
|
||||
u64 reserved2[(0x1000 - 0x500) / 8];
|
||||
};
|
||||
|
||||
#define MRx_HCR_LPARID_VALID EHEA_BMASK_IBM(0, 0)
|
||||
|
||||
#define MRMWMM_OFFSET(x) offsetof(struct ehea_mrmwmm, x)
|
||||
|
||||
struct ehea_mrmwmm {
|
||||
u64 mrx_hcr;
|
||||
u64 mrx_c;
|
||||
u64 mrx_herr;
|
||||
u64 mrx_aer;
|
||||
u64 mrx_pp;
|
||||
u64 reserved1;
|
||||
u64 reserved2;
|
||||
u64 reserved3;
|
||||
u64 reserved4[(0x200 - 0x40) / 8];
|
||||
u64 mrx_ctl[64];
|
||||
};
|
||||
|
||||
#define QPEDMM_OFFSET(x) offsetof(struct ehea_qpedmm, x)
|
||||
|
||||
struct ehea_qpedmm {
|
||||
|
||||
u64 reserved0[(0x400) / 8];
|
||||
u64 qpedx_phh;
|
||||
u64 qpedx_ppsgp;
|
||||
u64 qpedx_ppsgu;
|
||||
u64 qpedx_ppdgp;
|
||||
u64 qpedx_ppdgu;
|
||||
u64 qpedx_aph;
|
||||
u64 qpedx_apsgp;
|
||||
u64 qpedx_apsgu;
|
||||
u64 qpedx_apdgp;
|
||||
u64 qpedx_apdgu;
|
||||
u64 qpedx_apav;
|
||||
u64 qpedx_apsav;
|
||||
u64 qpedx_hcr;
|
||||
u64 reserved1[4];
|
||||
u64 qpedx_rrl0;
|
||||
u64 qpedx_rrrkey0;
|
||||
u64 qpedx_rrva0;
|
||||
u64 reserved2;
|
||||
u64 qpedx_rrl1;
|
||||
u64 qpedx_rrrkey1;
|
||||
u64 qpedx_rrva1;
|
||||
u64 reserved3;
|
||||
u64 qpedx_rrl2;
|
||||
u64 qpedx_rrrkey2;
|
||||
u64 qpedx_rrva2;
|
||||
u64 reserved4;
|
||||
u64 qpedx_rrl3;
|
||||
u64 qpedx_rrrkey3;
|
||||
u64 qpedx_rrva3;
|
||||
};
|
||||
|
||||
#define CQX_FECADDER EHEA_BMASK_IBM(32, 63)
|
||||
#define CQX_FEC_CQE_CNT EHEA_BMASK_IBM(32, 63)
|
||||
#define CQX_N1_GENERATE_COMP_EVENT EHEA_BMASK_IBM(0, 0)
|
||||
#define CQX_EP_EVENT_PENDING EHEA_BMASK_IBM(0, 0)
|
||||
|
||||
#define CQTEMM_OFFSET(x) offsetof(struct ehea_cqtemm, x)
|
||||
|
||||
struct ehea_cqtemm {
|
||||
u64 cqx_hcr;
|
||||
u64 cqx_c;
|
||||
u64 cqx_herr;
|
||||
u64 cqx_aer;
|
||||
u64 cqx_ptp;
|
||||
u64 cqx_tp;
|
||||
u64 cqx_fec;
|
||||
u64 cqx_feca;
|
||||
u64 cqx_ep;
|
||||
u64 cqx_eq;
|
||||
u64 reserved1;
|
||||
u64 cqx_n0;
|
||||
u64 cqx_n1;
|
||||
u64 reserved2[(0x1000 - 0x60) / 8];
|
||||
};
|
||||
|
||||
#define EQTEMM_OFFSET(x) offsetof(struct ehea_eqtemm, x)
|
||||
|
||||
struct ehea_eqtemm {
|
||||
u64 eqx_hcr;
|
||||
u64 eqx_c;
|
||||
u64 eqx_herr;
|
||||
u64 eqx_aer;
|
||||
u64 eqx_ptp;
|
||||
u64 eqx_tp;
|
||||
u64 eqx_ssba;
|
||||
u64 eqx_psba;
|
||||
u64 eqx_cec;
|
||||
u64 eqx_meql;
|
||||
u64 eqx_xisbi;
|
||||
u64 eqx_xisc;
|
||||
u64 eqx_it;
|
||||
};
|
||||
|
||||
static inline u64 epa_load(struct h_epa epa, u32 offset)
|
||||
{
|
||||
return readq((void __iomem *)(epa.addr + offset));
|
||||
}
|
||||
|
||||
static inline void epa_store(struct h_epa epa, u32 offset, u64 value)
|
||||
{
|
||||
writeq(value, (void __iomem *)(epa.addr + offset));
|
||||
epa_load(epa, offset); /* synchronize explicitly to eHEA */
|
||||
}
|
||||
|
||||
static inline void epa_store_acc(struct h_epa epa, u32 offset, u64 value)
|
||||
{
|
||||
writeq(value, (void __iomem *)(epa.addr + offset));
|
||||
}
|
||||
|
||||
#define epa_store_eq(epa, offset, value)\
|
||||
epa_store(epa, EQTEMM_OFFSET(offset), value)
|
||||
#define epa_load_eq(epa, offset)\
|
||||
epa_load(epa, EQTEMM_OFFSET(offset))
|
||||
|
||||
#define epa_store_cq(epa, offset, value)\
|
||||
epa_store(epa, CQTEMM_OFFSET(offset), value)
|
||||
#define epa_load_cq(epa, offset)\
|
||||
epa_load(epa, CQTEMM_OFFSET(offset))
|
||||
|
||||
#define epa_store_qp(epa, offset, value)\
|
||||
epa_store(epa, QPTEMM_OFFSET(offset), value)
|
||||
#define epa_load_qp(epa, offset)\
|
||||
epa_load(epa, QPTEMM_OFFSET(offset))
|
||||
|
||||
#define epa_store_qped(epa, offset, value)\
|
||||
epa_store(epa, QPEDMM_OFFSET(offset), value)
|
||||
#define epa_load_qped(epa, offset)\
|
||||
epa_load(epa, QPEDMM_OFFSET(offset))
|
||||
|
||||
#define epa_store_mrmw(epa, offset, value)\
|
||||
epa_store(epa, MRMWMM_OFFSET(offset), value)
|
||||
#define epa_load_mrmw(epa, offset)\
|
||||
epa_load(epa, MRMWMM_OFFSET(offset))
|
||||
|
||||
#define epa_store_base(epa, offset, value)\
|
||||
epa_store(epa, HCAGR_OFFSET(offset), value)
|
||||
#define epa_load_base(epa, offset)\
|
||||
epa_load(epa, HCAGR_OFFSET(offset))
|
||||
|
||||
static inline void ehea_update_sqa(struct ehea_qp *qp, u16 nr_wqes)
|
||||
{
|
||||
struct h_epa epa = qp->epas.kernel;
|
||||
epa_store_acc(epa, QPTEMM_OFFSET(qpx_sqa),
|
||||
EHEA_BMASK_SET(QPX_SQA_VALUE, nr_wqes));
|
||||
}
|
||||
|
||||
static inline void ehea_update_rq3a(struct ehea_qp *qp, u16 nr_wqes)
|
||||
{
|
||||
struct h_epa epa = qp->epas.kernel;
|
||||
epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq3a),
|
||||
EHEA_BMASK_SET(QPX_RQ1A_VALUE, nr_wqes));
|
||||
}
|
||||
|
||||
static inline void ehea_update_rq2a(struct ehea_qp *qp, u16 nr_wqes)
|
||||
{
|
||||
struct h_epa epa = qp->epas.kernel;
|
||||
epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq2a),
|
||||
EHEA_BMASK_SET(QPX_RQ2A_VALUE, nr_wqes));
|
||||
}
|
||||
|
||||
static inline void ehea_update_rq1a(struct ehea_qp *qp, u16 nr_wqes)
|
||||
{
|
||||
struct h_epa epa = qp->epas.kernel;
|
||||
epa_store_acc(epa, QPTEMM_OFFSET(qpx_rq1a),
|
||||
EHEA_BMASK_SET(QPX_RQ3A_VALUE, nr_wqes));
|
||||
}
|
||||
|
||||
static inline void ehea_update_feca(struct ehea_cq *cq, u32 nr_cqes)
|
||||
{
|
||||
struct h_epa epa = cq->epas.kernel;
|
||||
epa_store_acc(epa, CQTEMM_OFFSET(cqx_feca),
|
||||
EHEA_BMASK_SET(CQX_FECADDER, nr_cqes));
|
||||
}
|
||||
|
||||
static inline void ehea_reset_cq_n1(struct ehea_cq *cq)
|
||||
{
|
||||
struct h_epa epa = cq->epas.kernel;
|
||||
epa_store_cq(epa, cqx_n1,
|
||||
EHEA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, 1));
|
||||
}
|
||||
|
||||
static inline void ehea_reset_cq_ep(struct ehea_cq *my_cq)
|
||||
{
|
||||
struct h_epa epa = my_cq->epas.kernel;
|
||||
epa_store_acc(epa, CQTEMM_OFFSET(cqx_ep),
|
||||
EHEA_BMASK_SET(CQX_EP_EVENT_PENDING, 0));
|
||||
}
|
||||
|
||||
#endif /* __EHEA_HW_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,455 @@
|
||||
/*
|
||||
* linux/drivers/net/ehea/ehea_phyp.h
|
||||
*
|
||||
* eHEA ethernet device driver for IBM eServer System p
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2006
|
||||
*
|
||||
* Authors:
|
||||
* Christoph Raisch <raisch@de.ibm.com>
|
||||
* Jan-Bernd Themann <themann@de.ibm.com>
|
||||
* Thomas Klein <tklein@de.ibm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __EHEA_PHYP_H__
|
||||
#define __EHEA_PHYP_H__
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <asm/hvcall.h>
|
||||
#include "ehea.h"
|
||||
#include "ehea_hw.h"
|
||||
#include "ehea_hcall.h"
|
||||
|
||||
/* Some abbreviations used here:
|
||||
*
|
||||
* hcp_* - structures, variables and functions releated to Hypervisor Calls
|
||||
*/
|
||||
|
||||
static inline u32 get_longbusy_msecs(int long_busy_ret_code)
|
||||
{
|
||||
switch (long_busy_ret_code) {
|
||||
case H_LONG_BUSY_ORDER_1_MSEC:
|
||||
return 1;
|
||||
case H_LONG_BUSY_ORDER_10_MSEC:
|
||||
return 10;
|
||||
case H_LONG_BUSY_ORDER_100_MSEC:
|
||||
return 100;
|
||||
case H_LONG_BUSY_ORDER_1_SEC:
|
||||
return 1000;
|
||||
case H_LONG_BUSY_ORDER_10_SEC:
|
||||
return 10000;
|
||||
case H_LONG_BUSY_ORDER_100_SEC:
|
||||
return 100000;
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Notification Event Queue (NEQ) Entry bit masks */
|
||||
#define NEQE_EVENT_CODE EHEA_BMASK_IBM(2, 7)
|
||||
#define NEQE_PORTNUM EHEA_BMASK_IBM(32, 47)
|
||||
#define NEQE_PORT_UP EHEA_BMASK_IBM(16, 16)
|
||||
#define NEQE_EXTSWITCH_PORT_UP EHEA_BMASK_IBM(17, 17)
|
||||
#define NEQE_EXTSWITCH_PRIMARY EHEA_BMASK_IBM(18, 18)
|
||||
#define NEQE_PLID EHEA_BMASK_IBM(16, 47)
|
||||
|
||||
/* Notification Event Codes */
|
||||
#define EHEA_EC_PORTSTATE_CHG 0x30
|
||||
#define EHEA_EC_ADAPTER_MALFUNC 0x32
|
||||
#define EHEA_EC_PORT_MALFUNC 0x33
|
||||
|
||||
/* Notification Event Log Register (NELR) bit masks */
|
||||
#define NELR_PORT_MALFUNC EHEA_BMASK_IBM(61, 61)
|
||||
#define NELR_ADAPTER_MALFUNC EHEA_BMASK_IBM(62, 62)
|
||||
#define NELR_PORTSTATE_CHG EHEA_BMASK_IBM(63, 63)
|
||||
|
||||
static inline void hcp_epas_ctor(struct h_epas *epas, u64 paddr_kernel,
|
||||
u64 paddr_user)
|
||||
{
|
||||
epas->kernel.addr = ioremap(paddr_kernel, PAGE_SIZE);
|
||||
epas->user.addr = paddr_user;
|
||||
}
|
||||
|
||||
static inline void hcp_epas_dtor(struct h_epas *epas)
|
||||
{
|
||||
if (epas->kernel.addr)
|
||||
iounmap(epas->kernel.addr);
|
||||
|
||||
epas->user.addr = 0;
|
||||
epas->kernel.addr = 0;
|
||||
}
|
||||
|
||||
struct hcp_modify_qp_cb0 {
|
||||
u64 qp_ctl_reg; /* 00 */
|
||||
u32 max_swqe; /* 02 */
|
||||
u32 max_rwqe; /* 03 */
|
||||
u32 port_nb; /* 04 */
|
||||
u32 reserved0; /* 05 */
|
||||
u64 qp_aer; /* 06 */
|
||||
u64 qp_tenure; /* 08 */
|
||||
};
|
||||
|
||||
/* Hcall Query/Modify Queue Pair Control Block 0 Selection Mask Bits */
|
||||
#define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5)
|
||||
#define H_QPCB0_QP_CTL_REG EHEA_BMASK_IBM(0, 0)
|
||||
#define H_QPCB0_MAX_SWQE EHEA_BMASK_IBM(1, 1)
|
||||
#define H_QPCB0_MAX_RWQE EHEA_BMASK_IBM(2, 2)
|
||||
#define H_QPCB0_PORT_NB EHEA_BMASK_IBM(3, 3)
|
||||
#define H_QPCB0_QP_AER EHEA_BMASK_IBM(4, 4)
|
||||
#define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5)
|
||||
|
||||
/* Queue Pair Control Register Status Bits */
|
||||
#define H_QP_CR_ENABLED 0x8000000000000000ULL /* QP enabled */
|
||||
/* QP States: */
|
||||
#define H_QP_CR_STATE_RESET 0x0000010000000000ULL /* Reset */
|
||||
#define H_QP_CR_STATE_INITIALIZED 0x0000020000000000ULL /* Initialized */
|
||||
#define H_QP_CR_STATE_RDY2RCV 0x0000030000000000ULL /* Ready to recv */
|
||||
#define H_QP_CR_STATE_RDY2SND 0x0000050000000000ULL /* Ready to send */
|
||||
#define H_QP_CR_STATE_ERROR 0x0000800000000000ULL /* Error */
|
||||
|
||||
struct hcp_modify_qp_cb1 {
|
||||
u32 qpn; /* 00 */
|
||||
u32 qp_asyn_ev_eq_nb; /* 01 */
|
||||
u64 sq_cq_handle; /* 02 */
|
||||
u64 rq_cq_handle; /* 04 */
|
||||
/* sgel = scatter gather element */
|
||||
u32 sgel_nb_sq; /* 06 */
|
||||
u32 sgel_nb_rq1; /* 07 */
|
||||
u32 sgel_nb_rq2; /* 08 */
|
||||
u32 sgel_nb_rq3; /* 09 */
|
||||
};
|
||||
|
||||
/* Hcall Query/Modify Queue Pair Control Block 1 Selection Mask Bits */
|
||||
#define H_QPCB1_ALL EHEA_BMASK_IBM(0, 7)
|
||||
#define H_QPCB1_QPN EHEA_BMASK_IBM(0, 0)
|
||||
#define H_QPCB1_ASYN_EV_EQ_NB EHEA_BMASK_IBM(1, 1)
|
||||
#define H_QPCB1_SQ_CQ_HANDLE EHEA_BMASK_IBM(2, 2)
|
||||
#define H_QPCB1_RQ_CQ_HANDLE EHEA_BMASK_IBM(3, 3)
|
||||
#define H_QPCB1_SGEL_NB_SQ EHEA_BMASK_IBM(4, 4)
|
||||
#define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5)
|
||||
#define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6)
|
||||
#define H_QPCB1_SGEL_NB_RQ3 EHEA_BMASK_IBM(7, 7)
|
||||
|
||||
struct hcp_query_ehea {
|
||||
u32 cur_num_qps; /* 00 */
|
||||
u32 cur_num_cqs; /* 01 */
|
||||
u32 cur_num_eqs; /* 02 */
|
||||
u32 cur_num_mrs; /* 03 */
|
||||
u32 auth_level; /* 04 */
|
||||
u32 max_num_qps; /* 05 */
|
||||
u32 max_num_cqs; /* 06 */
|
||||
u32 max_num_eqs; /* 07 */
|
||||
u32 max_num_mrs; /* 08 */
|
||||
u32 reserved0; /* 09 */
|
||||
u32 int_clock_freq; /* 10 */
|
||||
u32 max_num_pds; /* 11 */
|
||||
u32 max_num_addr_handles; /* 12 */
|
||||
u32 max_num_cqes; /* 13 */
|
||||
u32 max_num_wqes; /* 14 */
|
||||
u32 max_num_sgel_rq1wqe; /* 15 */
|
||||
u32 max_num_sgel_rq2wqe; /* 16 */
|
||||
u32 max_num_sgel_rq3wqe; /* 17 */
|
||||
u32 mr_page_size; /* 18 */
|
||||
u32 reserved1; /* 19 */
|
||||
u64 max_mr_size; /* 20 */
|
||||
u64 reserved2; /* 22 */
|
||||
u32 num_ports; /* 24 */
|
||||
u32 reserved3; /* 25 */
|
||||
u32 reserved4; /* 26 */
|
||||
u32 reserved5; /* 27 */
|
||||
u64 max_mc_mac; /* 28 */
|
||||
u64 ehea_cap; /* 30 */
|
||||
u32 max_isn_per_eq; /* 32 */
|
||||
u32 max_num_neq; /* 33 */
|
||||
u64 max_num_vlan_ids; /* 34 */
|
||||
u32 max_num_port_group; /* 36 */
|
||||
u32 max_num_phys_port; /* 37 */
|
||||
|
||||
};
|
||||
|
||||
/* Hcall Query/Modify Port Control Block defines */
|
||||
#define H_PORT_CB0 0
|
||||
#define H_PORT_CB1 1
|
||||
#define H_PORT_CB2 2
|
||||
#define H_PORT_CB3 3
|
||||
#define H_PORT_CB4 4
|
||||
#define H_PORT_CB5 5
|
||||
#define H_PORT_CB6 6
|
||||
#define H_PORT_CB7 7
|
||||
|
||||
struct hcp_ehea_port_cb0 {
|
||||
u64 port_mac_addr;
|
||||
u64 port_rc;
|
||||
u64 reserved0;
|
||||
u32 port_op_state;
|
||||
u32 port_speed;
|
||||
u32 ext_swport_op_state;
|
||||
u32 neg_tpf_prpf;
|
||||
u32 num_default_qps;
|
||||
u32 reserved1;
|
||||
u64 default_qpn_arr[16];
|
||||
};
|
||||
|
||||
/* Hcall Query/Modify Port Control Block 0 Selection Mask Bits */
|
||||
#define H_PORT_CB0_ALL EHEA_BMASK_IBM(0, 7) /* Set all bits */
|
||||
#define H_PORT_CB0_MAC EHEA_BMASK_IBM(0, 0) /* MAC address */
|
||||
#define H_PORT_CB0_PRC EHEA_BMASK_IBM(1, 1) /* Port Recv Control */
|
||||
#define H_PORT_CB0_DEFQPNARRAY EHEA_BMASK_IBM(7, 7) /* Default QPN Array */
|
||||
|
||||
/* Hcall Query Port: Returned port speed values */
|
||||
#define H_SPEED_10M_H 1 /* 10 Mbps, Half Duplex */
|
||||
#define H_SPEED_10M_F 2 /* 10 Mbps, Full Duplex */
|
||||
#define H_SPEED_100M_H 3 /* 100 Mbps, Half Duplex */
|
||||
#define H_SPEED_100M_F 4 /* 100 Mbps, Full Duplex */
|
||||
#define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
|
||||
#define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
|
||||
|
||||
/* Port Receive Control Status Bits */
|
||||
#define PXLY_RC_VALID EHEA_BMASK_IBM(49, 49)
|
||||
#define PXLY_RC_VLAN_XTRACT EHEA_BMASK_IBM(50, 50)
|
||||
#define PXLY_RC_TCP_6_TUPLE EHEA_BMASK_IBM(51, 51)
|
||||
#define PXLY_RC_UDP_6_TUPLE EHEA_BMASK_IBM(52, 52)
|
||||
#define PXLY_RC_TCP_3_TUPLE EHEA_BMASK_IBM(53, 53)
|
||||
#define PXLY_RC_TCP_2_TUPLE EHEA_BMASK_IBM(54, 54)
|
||||
#define PXLY_RC_LLC_SNAP EHEA_BMASK_IBM(55, 55)
|
||||
#define PXLY_RC_JUMBO_FRAME EHEA_BMASK_IBM(56, 56)
|
||||
#define PXLY_RC_FRAG_IP_PKT EHEA_BMASK_IBM(57, 57)
|
||||
#define PXLY_RC_TCP_UDP_CHKSUM EHEA_BMASK_IBM(58, 58)
|
||||
#define PXLY_RC_IP_CHKSUM EHEA_BMASK_IBM(59, 59)
|
||||
#define PXLY_RC_MAC_FILTER EHEA_BMASK_IBM(60, 60)
|
||||
#define PXLY_RC_UNTAG_FILTER EHEA_BMASK_IBM(61, 61)
|
||||
#define PXLY_RC_VLAN_TAG_FILTER EHEA_BMASK_IBM(62, 63)
|
||||
|
||||
#define PXLY_RC_VLAN_FILTER 2
|
||||
#define PXLY_RC_VLAN_PERM 0
|
||||
|
||||
|
||||
#define H_PORT_CB1_ALL 0x8000000000000000ULL
|
||||
|
||||
struct hcp_ehea_port_cb1 {
|
||||
u64 vlan_filter[64];
|
||||
};
|
||||
|
||||
#define H_PORT_CB2_ALL 0xFFE0000000000000ULL
|
||||
|
||||
struct hcp_ehea_port_cb2 {
|
||||
u64 rxo;
|
||||
u64 rxucp;
|
||||
u64 rxufd;
|
||||
u64 rxuerr;
|
||||
u64 rxftl;
|
||||
u64 rxmcp;
|
||||
u64 rxbcp;
|
||||
u64 txo;
|
||||
u64 txucp;
|
||||
u64 txmcp;
|
||||
u64 txbcp;
|
||||
};
|
||||
|
||||
struct hcp_ehea_port_cb3 {
|
||||
u64 vlan_bc_filter[64];
|
||||
u64 vlan_mc_filter[64];
|
||||
u64 vlan_un_filter[64];
|
||||
u64 port_mac_hash_array[64];
|
||||
};
|
||||
|
||||
#define H_PORT_CB4_ALL 0xF000000000000000ULL
|
||||
#define H_PORT_CB4_JUMBO 0x1000000000000000ULL
|
||||
#define H_PORT_CB4_SPEED 0x8000000000000000ULL
|
||||
|
||||
struct hcp_ehea_port_cb4 {
|
||||
u32 port_speed;
|
||||
u32 pause_frame;
|
||||
u32 ens_port_op_state;
|
||||
u32 jumbo_frame;
|
||||
u32 ens_port_wrap;
|
||||
};
|
||||
|
||||
/* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */
|
||||
#define H_PORT_CB5_RCU 0x0001000000000000ULL
|
||||
#define PXS_RCU EHEA_BMASK_IBM(61, 63)
|
||||
|
||||
struct hcp_ehea_port_cb5 {
|
||||
u64 prc; /* 00 */
|
||||
u64 uaa; /* 01 */
|
||||
u64 macvc; /* 02 */
|
||||
u64 xpcsc; /* 03 */
|
||||
u64 xpcsp; /* 04 */
|
||||
u64 pcsid; /* 05 */
|
||||
u64 xpcsst; /* 06 */
|
||||
u64 pthlb; /* 07 */
|
||||
u64 pthrb; /* 08 */
|
||||
u64 pqu; /* 09 */
|
||||
u64 pqd; /* 10 */
|
||||
u64 prt; /* 11 */
|
||||
u64 wsth; /* 12 */
|
||||
u64 rcb; /* 13 */
|
||||
u64 rcm; /* 14 */
|
||||
u64 rcu; /* 15 */
|
||||
u64 macc; /* 16 */
|
||||
u64 pc; /* 17 */
|
||||
u64 pst; /* 18 */
|
||||
u64 ducqpn; /* 19 */
|
||||
u64 mcqpn; /* 20 */
|
||||
u64 mma; /* 21 */
|
||||
u64 pmc0h; /* 22 */
|
||||
u64 pmc0l; /* 23 */
|
||||
u64 lbc; /* 24 */
|
||||
};
|
||||
|
||||
#define H_PORT_CB6_ALL 0xFFFFFE7FFFFF8000ULL
|
||||
|
||||
struct hcp_ehea_port_cb6 {
|
||||
u64 rxo; /* 00 */
|
||||
u64 rx64; /* 01 */
|
||||
u64 rx65; /* 02 */
|
||||
u64 rx128; /* 03 */
|
||||
u64 rx256; /* 04 */
|
||||
u64 rx512; /* 05 */
|
||||
u64 rx1024; /* 06 */
|
||||
u64 rxbfcs; /* 07 */
|
||||
u64 rxime; /* 08 */
|
||||
u64 rxrle; /* 09 */
|
||||
u64 rxorle; /* 10 */
|
||||
u64 rxftl; /* 11 */
|
||||
u64 rxjab; /* 12 */
|
||||
u64 rxse; /* 13 */
|
||||
u64 rxce; /* 14 */
|
||||
u64 rxrf; /* 15 */
|
||||
u64 rxfrag; /* 16 */
|
||||
u64 rxuoc; /* 17 */
|
||||
u64 rxcpf; /* 18 */
|
||||
u64 rxsb; /* 19 */
|
||||
u64 rxfd; /* 20 */
|
||||
u64 rxoerr; /* 21 */
|
||||
u64 rxaln; /* 22 */
|
||||
u64 ducqpn; /* 23 */
|
||||
u64 reserved0; /* 24 */
|
||||
u64 rxmcp; /* 25 */
|
||||
u64 rxbcp; /* 26 */
|
||||
u64 txmcp; /* 27 */
|
||||
u64 txbcp; /* 28 */
|
||||
u64 txo; /* 29 */
|
||||
u64 tx64; /* 30 */
|
||||
u64 tx65; /* 31 */
|
||||
u64 tx128; /* 32 */
|
||||
u64 tx256; /* 33 */
|
||||
u64 tx512; /* 34 */
|
||||
u64 tx1024; /* 35 */
|
||||
u64 txbfcs; /* 36 */
|
||||
u64 txcpf; /* 37 */
|
||||
u64 txlf; /* 38 */
|
||||
u64 txrf; /* 39 */
|
||||
u64 txime; /* 40 */
|
||||
u64 txsc; /* 41 */
|
||||
u64 txmc; /* 42 */
|
||||
u64 txsqe; /* 43 */
|
||||
u64 txdef; /* 44 */
|
||||
u64 txlcol; /* 45 */
|
||||
u64 txexcol; /* 46 */
|
||||
u64 txcse; /* 47 */
|
||||
u64 txbor; /* 48 */
|
||||
};
|
||||
|
||||
#define H_PORT_CB7_DUCQPN 0x8000000000000000ULL
|
||||
|
||||
struct hcp_ehea_port_cb7 {
|
||||
u64 def_uc_qpn;
|
||||
};
|
||||
|
||||
u64 ehea_h_query_ehea_qp(const u64 adapter_handle,
|
||||
const u8 qp_category,
|
||||
const u64 qp_handle, const u64 sel_mask,
|
||||
void *cb_addr);
|
||||
|
||||
u64 ehea_h_modify_ehea_qp(const u64 adapter_handle,
|
||||
const u8 cat,
|
||||
const u64 qp_handle,
|
||||
const u64 sel_mask,
|
||||
void *cb_addr,
|
||||
u64 * inv_attr_id,
|
||||
u64 * proc_mask, u16 * out_swr, u16 * out_rwr);
|
||||
|
||||
u64 ehea_h_alloc_resource_eq(const u64 adapter_handle,
|
||||
struct ehea_eq_attr *eq_attr, u64 * eq_handle);
|
||||
|
||||
u64 ehea_h_alloc_resource_cq(const u64 adapter_handle,
|
||||
struct ehea_cq_attr *cq_attr,
|
||||
u64 * cq_handle, struct h_epas *epas);
|
||||
|
||||
u64 ehea_h_alloc_resource_qp(const u64 adapter_handle,
|
||||
struct ehea_qp_init_attr *init_attr,
|
||||
const u32 pd,
|
||||
u64 * qp_handle, struct h_epas *h_epas);
|
||||
|
||||
#define H_REG_RPAGE_PAGE_SIZE EHEA_BMASK_IBM(48,55)
|
||||
#define H_REG_RPAGE_QT EHEA_BMASK_IBM(62,63)
|
||||
|
||||
u64 ehea_h_register_rpage(const u64 adapter_handle,
|
||||
const u8 pagesize,
|
||||
const u8 queue_type,
|
||||
const u64 resource_handle,
|
||||
const u64 log_pageaddr, u64 count);
|
||||
|
||||
#define H_DISABLE_GET_EHEA_WQE_P 1
|
||||
#define H_DISABLE_GET_SQ_WQE_P 2
|
||||
#define H_DISABLE_GET_RQC 3
|
||||
|
||||
u64 ehea_h_disable_and_get_hea(const u64 adapter_handle, const u64 qp_handle);
|
||||
|
||||
u64 ehea_h_free_resource(const u64 adapter_handle, const u64 res_handle);
|
||||
|
||||
u64 ehea_h_alloc_resource_mr(const u64 adapter_handle, const u64 vaddr,
|
||||
const u64 length, const u32 access_ctrl,
|
||||
const u32 pd, u64 * mr_handle, u32 * lkey);
|
||||
|
||||
u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle,
|
||||
const u8 pagesize, const u8 queue_type,
|
||||
const u64 log_pageaddr, const u64 count);
|
||||
|
||||
u64 ehea_h_register_smr(const u64 adapter_handle, const u64 orig_mr_handle,
|
||||
const u64 vaddr_in, const u32 access_ctrl, const u32 pd,
|
||||
struct ehea_mr *mr);
|
||||
|
||||
u64 ehea_h_query_ehea(const u64 adapter_handle, void *cb_addr);
|
||||
|
||||
/* output param R5 */
|
||||
#define H_MEHEAPORT_CAT EHEA_BMASK_IBM(40,47)
|
||||
#define H_MEHEAPORT_PN EHEA_BMASK_IBM(48,63)
|
||||
|
||||
u64 ehea_h_query_ehea_port(const u64 adapter_handle, const u16 port_num,
|
||||
const u8 cb_cat, const u64 select_mask,
|
||||
void *cb_addr);
|
||||
|
||||
u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num,
|
||||
const u8 cb_cat, const u64 select_mask,
|
||||
void *cb_addr);
|
||||
|
||||
#define H_REGBCMC_PN EHEA_BMASK_IBM(48, 63)
|
||||
#define H_REGBCMC_REGTYPE EHEA_BMASK_IBM(61, 63)
|
||||
#define H_REGBCMC_MACADDR EHEA_BMASK_IBM(16, 63)
|
||||
#define H_REGBCMC_VLANID EHEA_BMASK_IBM(52, 63)
|
||||
|
||||
u64 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num,
|
||||
const u8 reg_type, const u64 mc_mac_addr,
|
||||
const u16 vlan_id, const u32 hcall_id);
|
||||
|
||||
u64 ehea_h_reset_events(const u64 adapter_handle, const u64 neq_handle,
|
||||
const u64 event_mask);
|
||||
|
||||
#endif /* __EHEA_PHYP_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,358 @@
|
||||
/*
|
||||
* linux/drivers/net/ehea/ehea_qmr.h
|
||||
*
|
||||
* eHEA ethernet device driver for IBM eServer System p
|
||||
*
|
||||
* (C) Copyright IBM Corp. 2006
|
||||
*
|
||||
* Authors:
|
||||
* Christoph Raisch <raisch@de.ibm.com>
|
||||
* Jan-Bernd Themann <themann@de.ibm.com>
|
||||
* Thomas Klein <tklein@de.ibm.com>
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __EHEA_QMR_H__
|
||||
#define __EHEA_QMR_H__
|
||||
|
||||
#include "ehea.h"
|
||||
#include "ehea_hw.h"
|
||||
|
||||
/*
|
||||
* page size of ehea hardware queues
|
||||
*/
|
||||
|
||||
#define EHEA_PAGESHIFT 12
|
||||
#define EHEA_PAGESIZE 4096UL
|
||||
|
||||
/* Some abbreviations used here:
|
||||
*
|
||||
* WQE - Work Queue Entry
|
||||
* SWQE - Send Work Queue Entry
|
||||
* RWQE - Receive Work Queue Entry
|
||||
* CQE - Completion Queue Entry
|
||||
* EQE - Event Queue Entry
|
||||
* MR - Memory Region
|
||||
*/
|
||||
|
||||
/* Use of WR_ID field for EHEA */
|
||||
#define EHEA_WR_ID_COUNT EHEA_BMASK_IBM(0, 19)
|
||||
#define EHEA_WR_ID_TYPE EHEA_BMASK_IBM(20, 23)
|
||||
#define EHEA_SWQE2_TYPE 0x1
|
||||
#define EHEA_SWQE3_TYPE 0x2
|
||||
#define EHEA_RWQE2_TYPE 0x3
|
||||
#define EHEA_RWQE3_TYPE 0x4
|
||||
#define EHEA_WR_ID_INDEX EHEA_BMASK_IBM(24, 47)
|
||||
#define EHEA_WR_ID_REFILL EHEA_BMASK_IBM(48, 63)
|
||||
|
||||
struct ehea_vsgentry {
|
||||
u64 vaddr;
|
||||
u32 l_key;
|
||||
u32 len;
|
||||
};
|
||||
|
||||
/* maximum number of sg entries allowed in a WQE */
|
||||
#define EHEA_MAX_WQE_SG_ENTRIES 252
|
||||
#define SWQE2_MAX_IMM (0xD0 - 0x30)
|
||||
#define SWQE3_MAX_IMM 224
|
||||
|
||||
/* tx control flags for swqe */
|
||||
#define EHEA_SWQE_CRC 0x8000
|
||||
#define EHEA_SWQE_IP_CHECKSUM 0x4000
|
||||
#define EHEA_SWQE_TCP_CHECKSUM 0x2000
|
||||
#define EHEA_SWQE_TSO 0x1000
|
||||
#define EHEA_SWQE_SIGNALLED_COMPLETION 0x0800
|
||||
#define EHEA_SWQE_VLAN_INSERT 0x0400
|
||||
#define EHEA_SWQE_IMM_DATA_PRESENT 0x0200
|
||||
#define EHEA_SWQE_DESCRIPTORS_PRESENT 0x0100
|
||||
#define EHEA_SWQE_WRAP_CTL_REC 0x0080
|
||||
#define EHEA_SWQE_WRAP_CTL_FORCE 0x0040
|
||||
#define EHEA_SWQE_BIND 0x0020
|
||||
#define EHEA_SWQE_PURGE 0x0010
|
||||
|
||||
/* sizeof(struct ehea_swqe) less the union */
|
||||
#define SWQE_HEADER_SIZE 32
|
||||
|
||||
struct ehea_swqe {
|
||||
u64 wr_id;
|
||||
u16 tx_control;
|
||||
u16 vlan_tag;
|
||||
u8 reserved1;
|
||||
u8 ip_start;
|
||||
u8 ip_end;
|
||||
u8 immediate_data_length;
|
||||
u8 tcp_offset;
|
||||
u8 reserved2;
|
||||
u16 tcp_end;
|
||||
u8 wrap_tag;
|
||||
u8 descriptors; /* number of valid descriptors in WQE */
|
||||
u16 reserved3;
|
||||
u16 reserved4;
|
||||
u16 mss;
|
||||
u32 reserved5;
|
||||
union {
|
||||
/* Send WQE Format 1 */
|
||||
struct {
|
||||
struct ehea_vsgentry sg_list[EHEA_MAX_WQE_SG_ENTRIES];
|
||||
} no_immediate_data;
|
||||
|
||||
/* Send WQE Format 2 */
|
||||
struct {
|
||||
struct ehea_vsgentry sg_entry;
|
||||
/* 0x30 */
|
||||
u8 immediate_data[SWQE2_MAX_IMM];
|
||||
/* 0xd0 */
|
||||
struct ehea_vsgentry sg_list[EHEA_MAX_WQE_SG_ENTRIES-1];
|
||||
} immdata_desc __attribute__ ((packed));
|
||||
|
||||
/* Send WQE Format 3 */
|
||||
struct {
|
||||
u8 immediate_data[SWQE3_MAX_IMM];
|
||||
} immdata_nodesc;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct ehea_rwqe {
|
||||
u64 wr_id; /* work request ID */
|
||||
u8 reserved1[5];
|
||||
u8 data_segments;
|
||||
u16 reserved2;
|
||||
u64 reserved3;
|
||||
u64 reserved4;
|
||||
struct ehea_vsgentry sg_list[EHEA_MAX_WQE_SG_ENTRIES];
|
||||
};
|
||||
|
||||
#define EHEA_CQE_VLAN_TAG_XTRACT 0x0400
|
||||
|
||||
#define EHEA_CQE_TYPE_RQ 0x60
|
||||
#define EHEA_CQE_STAT_ERR_MASK 0x721F
|
||||
#define EHEA_CQE_STAT_FAT_ERR_MASK 0x1F
|
||||
#define EHEA_CQE_STAT_ERR_TCP 0x4000
|
||||
|
||||
struct ehea_cqe {
|
||||
u64 wr_id; /* work request ID from WQE */
|
||||
u8 type;
|
||||
u8 valid;
|
||||
u16 status;
|
||||
u16 reserved1;
|
||||
u16 num_bytes_transfered;
|
||||
u16 vlan_tag;
|
||||
u16 inet_checksum_value;
|
||||
u8 reserved2;
|
||||
u8 header_length;
|
||||
u16 reserved3;
|
||||
u16 page_offset;
|
||||
u16 wqe_count;
|
||||
u32 qp_token;
|
||||
u32 timestamp;
|
||||
u32 reserved4;
|
||||
u64 reserved5[3];
|
||||
};
|
||||
|
||||
#define EHEA_EQE_VALID EHEA_BMASK_IBM(0, 0)
|
||||
#define EHEA_EQE_IS_CQE EHEA_BMASK_IBM(1, 1)
|
||||
#define EHEA_EQE_IDENTIFIER EHEA_BMASK_IBM(2, 7)
|
||||
#define EHEA_EQE_QP_CQ_NUMBER EHEA_BMASK_IBM(8, 31)
|
||||
#define EHEA_EQE_QP_TOKEN EHEA_BMASK_IBM(32, 63)
|
||||
#define EHEA_EQE_CQ_TOKEN EHEA_BMASK_IBM(32, 63)
|
||||
#define EHEA_EQE_KEY EHEA_BMASK_IBM(32, 63)
|
||||
#define EHEA_EQE_PORT_NUMBER EHEA_BMASK_IBM(56, 63)
|
||||
#define EHEA_EQE_EQ_NUMBER EHEA_BMASK_IBM(48, 63)
|
||||
#define EHEA_EQE_SM_ID EHEA_BMASK_IBM(48, 63)
|
||||
#define EHEA_EQE_SM_MECH_NUMBER EHEA_BMASK_IBM(48, 55)
|
||||
#define EHEA_EQE_SM_PORT_NUMBER EHEA_BMASK_IBM(56, 63)
|
||||
|
||||
struct ehea_eqe {
|
||||
u64 entry;
|
||||
};
|
||||
|
||||
static inline void *hw_qeit_calc(struct hw_queue *queue, u64 q_offset)
|
||||
{
|
||||
struct ehea_page *current_page;
|
||||
|
||||
if (q_offset >= queue->queue_length)
|
||||
q_offset -= queue->queue_length;
|
||||
current_page = (queue->queue_pages)[q_offset >> EHEA_PAGESHIFT];
|
||||
return ¤t_page->entries[q_offset & (EHEA_PAGESIZE - 1)];
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_get(struct hw_queue *queue)
|
||||
{
|
||||
return hw_qeit_calc(queue, queue->current_q_offset);
|
||||
}
|
||||
|
||||
static inline void hw_qeit_inc(struct hw_queue *queue)
|
||||
{
|
||||
queue->current_q_offset += queue->qe_size;
|
||||
if (queue->current_q_offset >= queue->queue_length) {
|
||||
queue->current_q_offset = 0;
|
||||
/* toggle the valid flag */
|
||||
queue->toggle_state = (~queue->toggle_state) & 1;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_get_inc(struct hw_queue *queue)
|
||||
{
|
||||
void *retvalue = hw_qeit_get(queue);
|
||||
hw_qeit_inc(queue);
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_get_inc_valid(struct hw_queue *queue)
|
||||
{
|
||||
struct ehea_cqe *retvalue = hw_qeit_get(queue);
|
||||
u8 valid = retvalue->valid;
|
||||
void *pref;
|
||||
|
||||
if ((valid >> 7) == (queue->toggle_state & 1)) {
|
||||
/* this is a good one */
|
||||
hw_qeit_inc(queue);
|
||||
pref = hw_qeit_calc(queue, queue->current_q_offset);
|
||||
prefetch(pref);
|
||||
prefetch(pref + 128);
|
||||
} else
|
||||
retvalue = NULL;
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_get_valid(struct hw_queue *queue)
|
||||
{
|
||||
struct ehea_cqe *retvalue = hw_qeit_get(queue);
|
||||
void *pref;
|
||||
u8 valid;
|
||||
|
||||
pref = hw_qeit_calc(queue, queue->current_q_offset);
|
||||
prefetch(pref);
|
||||
prefetch(pref + 128);
|
||||
prefetch(pref + 256);
|
||||
valid = retvalue->valid;
|
||||
if (!((valid >> 7) == (queue->toggle_state & 1)))
|
||||
retvalue = NULL;
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_reset(struct hw_queue *queue)
|
||||
{
|
||||
queue->current_q_offset = 0;
|
||||
return hw_qeit_get(queue);
|
||||
}
|
||||
|
||||
static inline void *hw_qeit_eq_get_inc(struct hw_queue *queue)
|
||||
{
|
||||
u64 last_entry_in_q = queue->queue_length - queue->qe_size;
|
||||
void *retvalue;
|
||||
|
||||
retvalue = hw_qeit_get(queue);
|
||||
queue->current_q_offset += queue->qe_size;
|
||||
if (queue->current_q_offset > last_entry_in_q) {
|
||||
queue->current_q_offset = 0;
|
||||
queue->toggle_state = (~queue->toggle_state) & 1;
|
||||
}
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
static inline void *hw_eqit_eq_get_inc_valid(struct hw_queue *queue)
|
||||
{
|
||||
void *retvalue = hw_qeit_get(queue);
|
||||
u32 qe = *(u8*)retvalue;
|
||||
if ((qe >> 7) == (queue->toggle_state & 1))
|
||||
hw_qeit_eq_get_inc(queue);
|
||||
else
|
||||
retvalue = NULL;
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
static inline struct ehea_rwqe *ehea_get_next_rwqe(struct ehea_qp *qp,
|
||||
int rq_nr)
|
||||
{
|
||||
struct hw_queue *queue;
|
||||
|
||||
if (rq_nr == 1)
|
||||
queue = &qp->hw_rqueue1;
|
||||
else if (rq_nr == 2)
|
||||
queue = &qp->hw_rqueue2;
|
||||
else
|
||||
queue = &qp->hw_rqueue3;
|
||||
|
||||
return hw_qeit_get_inc(queue);
|
||||
}
|
||||
|
||||
static inline struct ehea_swqe *ehea_get_swqe(struct ehea_qp *my_qp,
|
||||
int *wqe_index)
|
||||
{
|
||||
struct hw_queue *queue = &my_qp->hw_squeue;
|
||||
struct ehea_swqe *wqe_p;
|
||||
|
||||
*wqe_index = (queue->current_q_offset) >> (7 + EHEA_SG_SQ);
|
||||
wqe_p = hw_qeit_get_inc(&my_qp->hw_squeue);
|
||||
|
||||
return wqe_p;
|
||||
}
|
||||
|
||||
static inline void ehea_post_swqe(struct ehea_qp *my_qp, struct ehea_swqe *swqe)
|
||||
{
|
||||
iosync();
|
||||
ehea_update_sqa(my_qp, 1);
|
||||
}
|
||||
|
||||
static inline struct ehea_cqe *ehea_poll_rq1(struct ehea_qp *qp, int *wqe_index)
|
||||
{
|
||||
struct hw_queue *queue = &qp->hw_rqueue1;
|
||||
|
||||
*wqe_index = (queue->current_q_offset) >> (7 + EHEA_SG_RQ1);
|
||||
return hw_qeit_get_valid(queue);
|
||||
}
|
||||
|
||||
static inline void ehea_inc_rq1(struct ehea_qp *qp)
|
||||
{
|
||||
hw_qeit_inc(&qp->hw_rqueue1);
|
||||
}
|
||||
|
||||
static inline struct ehea_cqe *ehea_poll_cq(struct ehea_cq *my_cq)
|
||||
{
|
||||
return hw_qeit_get_inc_valid(&my_cq->hw_queue);
|
||||
}
|
||||
|
||||
#define EHEA_CQ_REGISTER_ORIG 0
|
||||
#define EHEA_EQ_REGISTER_ORIG 0
|
||||
|
||||
enum ehea_eq_type {
|
||||
EHEA_EQ = 0, /* event queue */
|
||||
EHEA_NEQ /* notification event queue */
|
||||
};
|
||||
|
||||
struct ehea_eq *ehea_create_eq(struct ehea_adapter *adapter,
|
||||
enum ehea_eq_type type,
|
||||
const u32 length, const u8 eqe_gen);
|
||||
|
||||
int ehea_destroy_eq(struct ehea_eq *eq);
|
||||
|
||||
struct ehea_eqe *ehea_poll_eq(struct ehea_eq *eq);
|
||||
|
||||
struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter, int cqe,
|
||||
u64 eq_handle, u32 cq_token);
|
||||
|
||||
int ehea_destroy_cq(struct ehea_cq *cq);
|
||||
|
||||
struct ehea_qp *ehea_create_qp(struct ehea_adapter * adapter, u32 pd,
|
||||
struct ehea_qp_init_attr *init_attr);
|
||||
|
||||
int ehea_destroy_qp(struct ehea_qp *qp);
|
||||
|
||||
int ehea_reg_mr_adapter(struct ehea_adapter *adapter);
|
||||
|
||||
#endif /* __EHEA_QMR_H__ */
|
||||
Reference in New Issue
Block a user