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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
This commit is contained in:
David S. Miller
@@ -281,7 +281,9 @@ enum ath5k_radio {
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AR5K_RF5112 = 2,
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AR5K_RF2413 = 3,
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AR5K_RF5413 = 4,
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AR5K_RF2425 = 5,
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AR5K_RF2316 = 5,
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AR5K_RF2317 = 6,
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AR5K_RF2425 = 7,
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};
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/*
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@@ -289,7 +291,7 @@ enum ath5k_radio {
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*/
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enum ath5k_srev_type {
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AR5K_VERSION_VER,
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AR5K_VERSION_MAC,
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AR5K_VERSION_RAD,
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};
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@@ -301,23 +303,24 @@ struct ath5k_srev_name {
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#define AR5K_SREV_UNKNOWN 0xffff
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#define AR5K_SREV_VER_AR5210 0x00
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#define AR5K_SREV_VER_AR5311 0x10
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#define AR5K_SREV_VER_AR5311A 0x20
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#define AR5K_SREV_VER_AR5311B 0x30
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#define AR5K_SREV_VER_AR5211 0x40
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#define AR5K_SREV_VER_AR5212 0x50
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#define AR5K_SREV_VER_AR5213 0x55
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#define AR5K_SREV_VER_AR5213A 0x59
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#define AR5K_SREV_VER_AR2413 0x78
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#define AR5K_SREV_VER_AR2414 0x79
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#define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
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#define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
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#define AR5K_SREV_VER_AR5413 0xa4
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#define AR5K_SREV_VER_AR5414 0xa5
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#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
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#define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
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#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
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#define AR5K_SREV_AR5210 0x00 /* Crete */
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#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
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#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
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#define AR5K_SREV_AR5311B 0x30 /* Spirit */
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#define AR5K_SREV_AR5211 0x40 /* Oahu */
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#define AR5K_SREV_AR5212 0x50 /* Venice */
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#define AR5K_SREV_AR5213 0x55 /* ??? */
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#define AR5K_SREV_AR5213A 0x59 /* Hainan */
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#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
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#define AR5K_SREV_AR2414 0x70 /* Griffin */
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#define AR5K_SREV_AR5424 0x90 /* Condor */
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#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
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#define AR5K_SREV_AR5414 0xa0 /* Eagle */
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#define AR5K_SREV_AR2415 0xb0 /* Cobra */
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#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
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#define AR5K_SREV_AR5418 0xca /* PCI-E */
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#define AR5K_SREV_AR2425 0xe0 /* Swan */
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#define AR5K_SREV_AR2417 0xf0 /* Nala */
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#define AR5K_SREV_RAD_5110 0x00
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#define AR5K_SREV_RAD_5111 0x10
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@@ -329,10 +332,20 @@ struct ath5k_srev_name {
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#define AR5K_SREV_RAD_2112 0x40
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#define AR5K_SREV_RAD_2112A 0x45
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#define AR5K_SREV_RAD_2112B 0x46
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#define AR5K_SREV_RAD_SC0 0x50 /* Found on 2413/2414 */
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#define AR5K_SREV_RAD_SC1 0x60 /* Found on 5413/5414 */
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#define AR5K_SREV_RAD_SC2 0xa0 /* Found on 2424-5/5424 */
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#define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
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#define AR5K_SREV_RAD_2413 0x50
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#define AR5K_SREV_RAD_5413 0x60
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#define AR5K_SREV_RAD_2316 0x70
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#define AR5K_SREV_RAD_2317 0x80
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#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
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#define AR5K_SREV_RAD_2425 0xa2
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#define AR5K_SREV_RAD_5133 0xc0
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#define AR5K_SREV_PHY_5211 0x30
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#define AR5K_SREV_PHY_5212 0x41
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#define AR5K_SREV_PHY_2112B 0x43
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#define AR5K_SREV_PHY_2413 0x45
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#define AR5K_SREV_PHY_5413 0x61
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#define AR5K_SREV_PHY_2425 0x70
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/* IEEE defs */
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#define IEEE80211_MAX_LEN 2500
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@@ -137,7 +137,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
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/*
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* Set the mac revision based on the pci id
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* Set the mac version based on the pci id
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*/
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ah->ah_version = mac_version;
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@@ -160,87 +160,132 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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0xffffffff;
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ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_5GHZ);
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ah->ah_phy = AR5K_PHY(0);
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if (ah->ah_version == AR5K_AR5210)
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ah->ah_radio_2ghz_revision = 0;
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else
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/* Try to identify radio chip based on it's srev */
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switch (ah->ah_radio_5ghz_revision & 0xf0) {
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case AR5K_SREV_RAD_5111:
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ah->ah_radio = AR5K_RF5111;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
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break;
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case AR5K_SREV_RAD_5112:
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case AR5K_SREV_RAD_2112:
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ah->ah_radio = AR5K_RF5112;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
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break;
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case AR5K_SREV_RAD_2413:
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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break;
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case AR5K_SREV_RAD_5413:
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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break;
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case AR5K_SREV_RAD_2316:
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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break;
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case AR5K_SREV_RAD_2317:
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ah->ah_radio = AR5K_RF2317;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
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break;
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case AR5K_SREV_RAD_5424:
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if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
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ah->ah_mac_version == AR5K_SREV_AR2417){
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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}
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break;
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default:
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/* Identify radio based on mac/phy srev */
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if (ah->ah_version == AR5K_AR5210) {
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ah->ah_radio = AR5K_RF5110;
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ah->ah_single_chip = false;
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} else if (ah->ah_version == AR5K_AR5211) {
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ah->ah_radio = AR5K_RF5111;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
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ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else if (srev == AR5K_SREV_AR5213A &&
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ah->ah_phy_revision == AR5K_SREV_PHY_2112B) {
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ah->ah_radio = AR5K_RF5112;
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ah->ah_single_chip = false;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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} else {
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ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
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ret = -ENODEV;
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goto err_free;
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}
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}
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/* Return on unsuported chips (unsupported eeprom etc) */
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if ((srev >= AR5K_SREV_VER_AR5416) &&
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(srev < AR5K_SREV_VER_AR2425)) {
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if ((srev >= AR5K_SREV_AR5416) &&
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(srev < AR5K_SREV_AR2425)) {
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ATH5K_ERR(sc, "Device not yet supported.\n");
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ret = -ENODEV;
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goto err_free;
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} else if (srev == AR5K_SREV_VER_AR2425) {
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ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
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}
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/* Identify single chip solutions */
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if (((srev <= AR5K_SREV_VER_AR5414) &&
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(srev >= AR5K_SREV_VER_AR2413)) ||
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(srev == AR5K_SREV_VER_AR2425)) {
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ah->ah_single_chip = true;
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} else {
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ah->ah_single_chip = false;
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}
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/* Single chip radio */
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if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
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ah->ah_radio_2ghz_revision = 0;
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/* Identify the radio chip*/
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if (ah->ah_version == AR5K_AR5210) {
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ah->ah_radio = AR5K_RF5110;
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/*
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* Register returns 0x0/0x04 for radio revision
|
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* so ath5k_hw_radio_revision doesn't parse the value
|
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* correctly. For now we are based on mac's srev to
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* identify RF2425 radio.
|
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*/
|
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} else if (srev == AR5K_SREV_VER_AR2425) {
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ah->ah_radio = AR5K_RF2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
|
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
|
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ah->ah_radio = AR5K_RF5111;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
|
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
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ah->ah_radio = AR5K_RF5112;
|
||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
|
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
|
||||
ah->ah_radio = AR5K_RF2413;
|
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
|
||||
} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
|
||||
ah->ah_radio = AR5K_RF5413;
|
||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
|
||||
} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
|
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/* AR5424 */
|
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if (srev >= AR5K_SREV_VER_AR5424) {
|
||||
ah->ah_radio = AR5K_RF5413;
|
||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
|
||||
/* AR2424 */
|
||||
} else {
|
||||
ah->ah_radio = AR5K_RF2413; /* For testing */
|
||||
ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
|
||||
}
|
||||
}
|
||||
ah->ah_phy = AR5K_PHY(0);
|
||||
|
||||
/*
|
||||
* Write PCI-E power save settings
|
||||
*/
|
||||
if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
|
||||
ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
|
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ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
|
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ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
|
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ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
|
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ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
|
||||
ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
|
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ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
|
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ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
|
||||
ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
|
||||
ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
|
||||
ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
|
||||
ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
|
||||
/* Shut off RX when elecidle is asserted */
|
||||
ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
|
||||
ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
|
||||
/* TODO: EEPROM work */
|
||||
ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
|
||||
/* Shut off PLL and CLKREQ active in L1 */
|
||||
ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
|
||||
/* Preserce other settings */
|
||||
ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
|
||||
ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
|
||||
ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
|
||||
/* Reset SERDES to load new settings */
|
||||
ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -250,14 +295,13 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
/* Write AR5K_PCICFG_UNK on 2112B and later chips */
|
||||
if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
|
||||
srev > AR5K_SREV_VER_AR2413) {
|
||||
ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG);
|
||||
}
|
||||
/* Enable pci core retry fix on Hainan (5213A) and later chips */
|
||||
if (srev >= AR5K_SREV_AR5213A)
|
||||
ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
|
||||
|
||||
/*
|
||||
* Get card capabilities, values, ...
|
||||
* Get card capabilities, calibration values etc
|
||||
* TODO: EEPROM work
|
||||
*/
|
||||
ret = ath5k_eeprom_init(ah);
|
||||
if (ret) {
|
||||
@@ -273,7 +317,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
/* Get MAC address */
|
||||
/* Set MAC address */
|
||||
ret = ath5k_eeprom_read_mac(ah, mac);
|
||||
if (ret) {
|
||||
ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
|
||||
|
||||
@@ -72,7 +72,7 @@ MODULE_AUTHOR("Nick Kossifidis");
|
||||
MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
|
||||
MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
|
||||
MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
|
||||
|
||||
|
||||
/* Known PCI ids */
|
||||
@@ -93,41 +93,48 @@ static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
|
||||
{ PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
|
||||
{ PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
|
||||
{ PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
|
||||
{ PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
|
||||
{ PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
|
||||
{ PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
|
||||
{ 0 }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
|
||||
|
||||
/* Known SREVs */
|
||||
static struct ath5k_srev_name srev_names[] = {
|
||||
{ "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
|
||||
{ "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
|
||||
{ "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
|
||||
{ "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
|
||||
{ "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
|
||||
{ "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
|
||||
{ "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
|
||||
{ "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
|
||||
{ "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
|
||||
{ "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
|
||||
{ "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
|
||||
{ "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
|
||||
{ "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
|
||||
{ "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
|
||||
{ "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
|
||||
{ "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
|
||||
{ "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
|
||||
{ "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
|
||||
{ "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
|
||||
{ "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
|
||||
{ "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
|
||||
{ "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
|
||||
{ "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
|
||||
{ "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
|
||||
{ "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
|
||||
{ "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
|
||||
{ "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
|
||||
{ "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
|
||||
{ "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
|
||||
{ "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
|
||||
{ "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
|
||||
{ "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
|
||||
{ "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
|
||||
{ "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
|
||||
{ "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
|
||||
{ "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
|
||||
{ "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
|
||||
{ "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
|
||||
{ "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
|
||||
{ "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
|
||||
{ "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
|
||||
{ "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
|
||||
{ "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
|
||||
{ "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
|
||||
{ "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
|
||||
{ "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
|
||||
{ "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
|
||||
{ "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
|
||||
{ "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
|
||||
{ "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
|
||||
{ "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
|
||||
{ "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
|
||||
{ "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
|
||||
{ "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
|
||||
{ "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
|
||||
{ "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
|
||||
{ "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
|
||||
};
|
||||
@@ -390,7 +397,11 @@ ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
|
||||
for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
|
||||
if (srev_names[i].sr_type != type)
|
||||
continue;
|
||||
if ((val & 0xff) < srev_names[i + 1].sr_val) {
|
||||
|
||||
if ((val & 0xf0) == srev_names[i].sr_val)
|
||||
name = srev_names[i].sr_name;
|
||||
|
||||
if ((val & 0xff) == srev_names[i].sr_val) {
|
||||
name = srev_names[i].sr_name;
|
||||
break;
|
||||
}
|
||||
@@ -536,7 +547,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
|
||||
goto err_ah;
|
||||
|
||||
ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
|
||||
ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
|
||||
ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
|
||||
sc->ah->ah_mac_srev,
|
||||
sc->ah->ah_phy_revision);
|
||||
|
||||
|
||||
@@ -68,7 +68,7 @@ int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
|
||||
/*
|
||||
* It may take some time to disable the DMA receive unit
|
||||
*/
|
||||
for (i = 2000; i > 0 &&
|
||||
for (i = 1000; i > 0 &&
|
||||
(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
|
||||
i--)
|
||||
udelay(10);
|
||||
@@ -182,11 +182,10 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
* have any pending frames. Returns -EBUSY if we still have pending frames,
|
||||
* -EINVAL if queue number is out of range.
|
||||
*
|
||||
* TODO: Test queue drain code
|
||||
*/
|
||||
int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
{
|
||||
unsigned int i = 100;
|
||||
unsigned int i = 40;
|
||||
u32 tx_queue, pending;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
@@ -233,13 +232,53 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
|
||||
udelay(100);
|
||||
} while (--i && pending);
|
||||
|
||||
/* For 2413+ order PCU to drop packets using
|
||||
* QUIET mechanism */
|
||||
if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
|
||||
pending){
|
||||
/* Set periodicity and duration */
|
||||
ath5k_hw_reg_write(ah,
|
||||
AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
|
||||
AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
|
||||
AR5K_QUIET_CTL2);
|
||||
|
||||
/* Enable quiet period for current TSF */
|
||||
ath5k_hw_reg_write(ah,
|
||||
AR5K_QUIET_CTL1_QT_EN |
|
||||
AR5K_REG_SM(ath5k_hw_reg_read(ah,
|
||||
AR5K_TSF_L32_5211) >> 10,
|
||||
AR5K_QUIET_CTL1_NEXT_QT_TSF),
|
||||
AR5K_QUIET_CTL1);
|
||||
|
||||
/* Force channel idle high */
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
|
||||
AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
|
||||
|
||||
/* Wait a while and disable mechanism */
|
||||
udelay(200);
|
||||
AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
|
||||
AR5K_QUIET_CTL1_QT_EN);
|
||||
|
||||
/* Re-check for pending frames */
|
||||
i = 40;
|
||||
do {
|
||||
pending = ath5k_hw_reg_read(ah,
|
||||
AR5K_QUEUE_STATUS(queue)) &
|
||||
AR5K_QCU_STS_FRMPENDCNT;
|
||||
udelay(100);
|
||||
} while (--i && pending);
|
||||
|
||||
AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
|
||||
AR5K_DIAG_SW_CHANEL_IDLE_HIGH);
|
||||
}
|
||||
|
||||
/* Clear register */
|
||||
ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
|
||||
if (pending)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* TODO: Check for success else return error */
|
||||
/* TODO: Check for success on 5210 else return error */
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -415,7 +454,7 @@ done:
|
||||
bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
|
||||
{
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
return ath5k_hw_reg_read(ah, AR5K_INTPEND);
|
||||
return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -633,8 +633,20 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
|
||||
*/
|
||||
void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
ATH5K_TRACE(ah->ah_sc);
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
|
||||
|
||||
val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
|
||||
|
||||
/*
|
||||
* Each write to the RESET_TSF bit toggles a hardware internal
|
||||
* signal to reset TSF, but if left high it will cause a TSF reset
|
||||
* on the next chip reset as well. Thus we always write the value
|
||||
* twice to clear the signal.
|
||||
*/
|
||||
ath5k_hw_reg_write(ah, val, AR5K_BEACON);
|
||||
ath5k_hw_reg_write(ah, val, AR5K_BEACON);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -375,7 +375,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
case AR5K_TX_QUEUE_BEACON:
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
|
||||
AR5K_QCU_MISC_FRSHED_DBA_GT |
|
||||
AR5K_QCU_MISC_CBREXP_BCN |
|
||||
AR5K_QCU_MISC_CBREXP_BCN_DIS |
|
||||
AR5K_QCU_MISC_BCN_ENABLE);
|
||||
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
|
||||
@@ -395,8 +395,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
case AR5K_TX_QUEUE_CAB:
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
|
||||
AR5K_QCU_MISC_FRSHED_DBA_GT |
|
||||
AR5K_QCU_MISC_CBREXP |
|
||||
AR5K_QCU_MISC_CBREXP_BCN);
|
||||
AR5K_QCU_MISC_CBREXP_DIS |
|
||||
AR5K_QCU_MISC_CBREXP_BCN_DIS);
|
||||
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
|
||||
(AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
|
||||
@@ -405,7 +405,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
|
||||
|
||||
case AR5K_TX_QUEUE_UAPSD:
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
|
||||
AR5K_QCU_MISC_CBREXP);
|
||||
AR5K_QCU_MISC_CBREXP_DIS);
|
||||
break;
|
||||
|
||||
case AR5K_TX_QUEUE_DATA:
|
||||
|
||||
+405
-172
File diff suppressed because it is too large
Load Diff
@@ -543,13 +543,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
||||
ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
|
||||
|
||||
if (channel->hw_value == CHANNEL_G)
|
||||
if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
|
||||
if (ah->ah_mac_srev < AR5K_SREV_AR2413)
|
||||
ath5k_hw_reg_write(ah, 0x00f80d80,
|
||||
0x994c);
|
||||
else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
|
||||
else if (ah->ah_mac_srev < AR5K_SREV_AR5424)
|
||||
ath5k_hw_reg_write(ah, 0x00380140,
|
||||
0x994c);
|
||||
else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
|
||||
else if (ah->ah_mac_srev < AR5K_SREV_AR2425)
|
||||
ath5k_hw_reg_write(ah, 0x00fc0ec0,
|
||||
0x994c);
|
||||
else /* 2425 */
|
||||
@@ -915,7 +915,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
||||
ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
|
||||
ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
|
||||
ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
|
||||
if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
|
||||
if (ah->ah_mac_srev >= AR5K_SREV_AR2413)
|
||||
ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
|
||||
}
|
||||
|
||||
|
||||
@@ -815,7 +815,7 @@ void b43_dummy_transmission(struct b43_wldev *dev)
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
for (i = 0x00; i < 0x0A; i++) {
|
||||
for (i = 0x00; i < 0x19; i++) {
|
||||
value = b43_read16(dev, 0x0690);
|
||||
if (!(value & 0x0100))
|
||||
break;
|
||||
@@ -4543,9 +4543,11 @@ static void b43_sprom_fixup(struct ssb_bus *bus)
|
||||
pdev = bus->host_pci;
|
||||
if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
|
||||
IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
|
||||
bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2875,6 +2875,13 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (conf->flags & IEEE80211_CONF_PS)
|
||||
ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3);
|
||||
else
|
||||
ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM);
|
||||
if (ret)
|
||||
IWL_DEBUG_MAC80211("Error setting power level\n");
|
||||
|
||||
IWL_DEBUG_MAC80211("TX Power old=%d new=%d\n",
|
||||
priv->tx_power_user_lmt, conf->power_level);
|
||||
|
||||
@@ -4236,13 +4243,13 @@ static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (err) {
|
||||
err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
/* both attempts failed: */
|
||||
if (err) {
|
||||
printk(KERN_WARNING "%s: No suitable DMA available.\n",
|
||||
|
||||
@@ -64,7 +64,7 @@
|
||||
#define CSR_BASE (0x000)
|
||||
|
||||
#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
|
||||
#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
|
||||
#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
|
||||
#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
|
||||
#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
|
||||
#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
|
||||
|
||||
@@ -247,8 +247,8 @@
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
|
||||
|
||||
#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
|
||||
#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
|
||||
#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
|
||||
#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
|
||||
#define RX_RB_TIMEOUT (0x10)
|
||||
|
||||
#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
|
||||
@@ -260,8 +260,9 @@
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
|
||||
#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
|
||||
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
|
||||
#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
|
||||
#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@@ -376,7 +376,9 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
|
||||
{
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
unsigned int rb_size;
|
||||
u32 rb_size;
|
||||
const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
|
||||
const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
ret = iwl_grab_nic_access(priv);
|
||||
@@ -398,26 +400,32 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
|
||||
|
||||
/* Tell device where to find RBD circular buffer in DRAM */
|
||||
iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
|
||||
rxq->dma_addr >> 8);
|
||||
(u32)(rxq->dma_addr >> 8));
|
||||
|
||||
/* Tell device where in DRAM to update its Rx status */
|
||||
iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
|
||||
(priv->shared_phys + priv->rb_closed_offset) >> 4);
|
||||
|
||||
/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
|
||||
/* Enable Rx DMA
|
||||
* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in
|
||||
* the credit mechanism in 5000 HW RX FIFO
|
||||
* Direct rx interrupts to hosts
|
||||
* Rx buffer size 4 or 8k
|
||||
* RB timeout 0x10
|
||||
* 256 RBDs
|
||||
*/
|
||||
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
|
||||
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
|
||||
FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
|
||||
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
|
||||
rb_size |
|
||||
/* 0x10 << 4 | */
|
||||
(RX_QUEUE_SIZE_LOG <<
|
||||
FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
|
||||
|
||||
/*
|
||||
* iwl_write32(priv,CSR_INT_COAL_REG,0);
|
||||
*/
|
||||
rb_size|
|
||||
(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
|
||||
(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
|
||||
|
||||
iwl_release_nic_access(priv);
|
||||
|
||||
iwl_write32(priv, CSR_INT_COALESCING, 0x40);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1949,7 +1949,7 @@ int lbs_set_tpc_cfg(struct lbs_private *priv, int enable, int8_t p0, int8_t p1,
|
||||
cmd.hdr.size = cpu_to_le16(sizeof(cmd));
|
||||
cmd.action = cpu_to_le16(CMD_ACT_SET);
|
||||
cmd.enable = !!enable;
|
||||
cmd.usesnr = !!enable;
|
||||
cmd.usesnr = !!usesnr;
|
||||
cmd.P0 = p0;
|
||||
cmd.P1 = p1;
|
||||
cmd.P2 = p2;
|
||||
|
||||
@@ -32,6 +32,12 @@ int lbs_set_power_adapt_cfg(struct lbs_private *priv, int enable, int8_t p0,
|
||||
int lbs_set_tpc_cfg(struct lbs_private *priv, int enable, int8_t p0, int8_t p1,
|
||||
int8_t p2, int usesnr);
|
||||
|
||||
int lbs_set_power_adapt_cfg(struct lbs_private *priv, int enable, int8_t p0,
|
||||
int8_t p1, int8_t p2);
|
||||
|
||||
int lbs_set_tpc_cfg(struct lbs_private *priv, int enable, int8_t p0, int8_t p1,
|
||||
int8_t p2, int usesnr);
|
||||
|
||||
int lbs_cmd_copyback(struct lbs_private *priv, unsigned long extra,
|
||||
struct cmd_header *resp);
|
||||
|
||||
|
||||
@@ -189,7 +189,6 @@ static inline void lbs_deb_hex(unsigned int grp, const char *prompt, u8 *buf, in
|
||||
#define MRVDRV_CMD_UPLD_RDY 0x0008
|
||||
#define MRVDRV_CARDEVENT 0x0010
|
||||
|
||||
|
||||
/* Automatic TX control default levels */
|
||||
#define POW_ADAPT_DEFAULT_P0 13
|
||||
#define POW_ADAPT_DEFAULT_P1 15
|
||||
|
||||
@@ -1025,6 +1025,18 @@ static int lbs_set_rate(struct net_device *dev, struct iw_request_info *info,
|
||||
new_rate);
|
||||
goto out;
|
||||
}
|
||||
if (priv->fwrelease < 0x09000000) {
|
||||
ret = lbs_set_power_adapt_cfg(priv, 0,
|
||||
POW_ADAPT_DEFAULT_P0,
|
||||
POW_ADAPT_DEFAULT_P1,
|
||||
POW_ADAPT_DEFAULT_P2);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
ret = lbs_set_tpc_cfg(priv, 0, TPC_DEFAULT_P0, TPC_DEFAULT_P1,
|
||||
TPC_DEFAULT_P2, 1);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Try the newer command first (Firmware Spec 5.1 and above) */
|
||||
|
||||
@@ -149,7 +149,8 @@ int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
|
||||
u32 code = le32_to_cpu(bootrec->code);
|
||||
switch (code) {
|
||||
case BR_CODE_COMPONENT_ID:
|
||||
priv->fw_interface = be32_to_cpup(bootrec->data);
|
||||
priv->fw_interface = be32_to_cpup((__be32 *)
|
||||
bootrec->data);
|
||||
switch (priv->fw_interface) {
|
||||
case FW_FMAC:
|
||||
printk(KERN_INFO "p54: FreeMAC firmware\n");
|
||||
@@ -181,9 +182,8 @@ int p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
|
||||
priv->rx_end = le32_to_cpu(desc->rx_end) - 0x3500;
|
||||
priv->headroom = desc->headroom;
|
||||
priv->tailroom = desc->tailroom;
|
||||
if (bootrec->len == 11)
|
||||
priv->rx_mtu = (size_t) le16_to_cpu(
|
||||
(__le16)bootrec->data[10]);
|
||||
if (le32_to_cpu(bootrec->len) == 11)
|
||||
priv->rx_mtu = le16_to_cpu(bootrec->rx_mtu);
|
||||
else
|
||||
priv->rx_mtu = (size_t)
|
||||
0x620 - priv->tx_hdr_len;
|
||||
@@ -306,11 +306,11 @@ static int p54_convert_rev1(struct ieee80211_hw *dev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char* p54_rf_chips[] = { "NULL", "Indigo?", "Duette",
|
||||
static const char *p54_rf_chips[] = { "NULL", "Indigo?", "Duette",
|
||||
"Frisbee", "Xbow", "Longbow" };
|
||||
static int p54_init_xbow_synth(struct ieee80211_hw *dev);
|
||||
|
||||
int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
|
||||
static int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
|
||||
{
|
||||
struct p54_common *priv = dev->priv;
|
||||
struct eeprom_pda_wrap *wrap = NULL;
|
||||
@@ -617,7 +617,7 @@ static void p54_rx_eeprom_readback(struct ieee80211_hw *dev,
|
||||
if (!priv->eeprom)
|
||||
return ;
|
||||
|
||||
memcpy(priv->eeprom, eeprom->data, eeprom->len);
|
||||
memcpy(priv->eeprom, eeprom->data, le16_to_cpu(eeprom->len));
|
||||
|
||||
complete(&priv->eeprom_comp);
|
||||
}
|
||||
@@ -777,8 +777,9 @@ int p54_read_eeprom(struct ieee80211_hw *dev)
|
||||
hdr->len = cpu_to_le16(blocksize + sizeof(*eeprom_hdr));
|
||||
eeprom_hdr->offset = cpu_to_le16(offset);
|
||||
eeprom_hdr->len = cpu_to_le16(blocksize);
|
||||
p54_assign_address(dev, NULL, hdr, hdr->len + sizeof(*hdr));
|
||||
priv->tx(dev, hdr, hdr->len + sizeof(*hdr), 0);
|
||||
p54_assign_address(dev, NULL, hdr, le16_to_cpu(hdr->len) +
|
||||
sizeof(*hdr));
|
||||
priv->tx(dev, hdr, le16_to_cpu(hdr->len) + sizeof(*hdr), 0);
|
||||
|
||||
if (!wait_for_completion_interruptible_timeout(&priv->eeprom_comp, HZ)) {
|
||||
printk(KERN_ERR "%s: device does not respond!\n",
|
||||
@@ -1247,18 +1248,20 @@ static void p54_configure_filter(struct ieee80211_hw *dev,
|
||||
|
||||
if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
|
||||
if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
|
||||
p54_set_filter(dev, priv->filter_type, NULL);
|
||||
p54_set_filter(dev, le16_to_cpu(priv->filter_type),
|
||||
NULL);
|
||||
else
|
||||
p54_set_filter(dev, priv->filter_type, priv->bssid);
|
||||
p54_set_filter(dev, le16_to_cpu(priv->filter_type),
|
||||
priv->bssid);
|
||||
}
|
||||
|
||||
if (changed_flags & FIF_PROMISC_IN_BSS) {
|
||||
if (*total_flags & FIF_PROMISC_IN_BSS)
|
||||
p54_set_filter(dev, priv->filter_type |
|
||||
cpu_to_le16(0x8), NULL);
|
||||
p54_set_filter(dev, le16_to_cpu(priv->filter_type) |
|
||||
0x8, NULL);
|
||||
else
|
||||
p54_set_filter(dev, priv->filter_type &
|
||||
~cpu_to_le16(0x8), priv->bssid);
|
||||
p54_set_filter(dev, le16_to_cpu(priv->filter_type) &
|
||||
~0x8, priv->bssid);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -18,7 +18,8 @@
|
||||
struct bootrec {
|
||||
__le32 code;
|
||||
__le32 len;
|
||||
u32 data[0];
|
||||
u32 data[10];
|
||||
__le16 rx_mtu;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bootrec_exp_if {
|
||||
|
||||
@@ -218,17 +218,17 @@ static void p54u_tx_3887(struct ieee80211_hw *dev, struct p54_control_hdr *data,
|
||||
usb_submit_urb(data_urb, GFP_ATOMIC);
|
||||
}
|
||||
|
||||
__le32 p54u_lm87_chksum(const u32 *data, size_t length)
|
||||
static __le32 p54u_lm87_chksum(const u32 *data, size_t length)
|
||||
{
|
||||
__le32 chk = 0;
|
||||
u32 chk = 0;
|
||||
|
||||
length >>= 2;
|
||||
while (length--) {
|
||||
chk ^= cpu_to_le32(*data++);
|
||||
chk ^= *data++;
|
||||
chk = (chk >> 5) ^ (chk << 3);
|
||||
}
|
||||
|
||||
return chk;
|
||||
return cpu_to_le32(chk);
|
||||
}
|
||||
|
||||
static void p54u_tx_lm87(struct ieee80211_hw *dev,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user