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crypto: mediatek - Add crypto driver support for some MediaTek chips
This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ryder Lee
Herbert Xu
@@ -553,6 +553,23 @@ config CRYPTO_DEV_ROCKCHIP
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This driver interfaces with the hardware crypto accelerator.
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Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
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config CRYPTO_DEV_MEDIATEK
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tristate "MediaTek's EIP97 Cryptographic Engine driver"
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depends on ARM && (ARCH_MEDIATEK || COMPILE_TEST)
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select NEON
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select KERNEL_MODE_NEON
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select ARM_CRYPTO
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select CRYPTO_AES
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select CRYPTO_BLKCIPHER
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select CRYPTO_SHA1_ARM_NEON
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select CRYPTO_SHA256_ARM
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select CRYPTO_SHA512_ARM
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select CRYPTO_HMAC
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help
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This driver allows you to utilize the hardware crypto accelerator
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EIP97 which can be found on the MT7623 MT2701, MT8521p, etc ....
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Select this if you want to use it for AES/SHA1/SHA2 algorithms.
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source "drivers/crypto/chelsio/Kconfig"
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source "drivers/crypto/virtio/Kconfig"
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@@ -11,6 +11,7 @@ obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
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obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
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obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
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obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
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obj-$(CONFIG_CRYPTO_DEV_MXC_SCC) += mxc-scc.o
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obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
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@@ -0,0 +1,2 @@
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obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mtk-crypto.o
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mtk-crypto-objs:= mtk-platform.o mtk-aes.o mtk-sha.o
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,238 @@
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/*
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* Driver for EIP97 cryptographic accelerator.
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*
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* Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __MTK_PLATFORM_H_
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#define __MTK_PLATFORM_H_
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#include <crypto/algapi.h>
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#include <crypto/internal/hash.h>
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#include <crypto/scatterwalk.h>
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#include <linux/crypto.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/scatterlist.h>
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#include "mtk-regs.h"
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#define MTK_RDR_PROC_THRESH BIT(0)
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#define MTK_RDR_PROC_MODE BIT(23)
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#define MTK_CNT_RST BIT(31)
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#define MTK_IRQ_RDR0 BIT(1)
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#define MTK_IRQ_RDR1 BIT(3)
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#define MTK_IRQ_RDR2 BIT(5)
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#define MTK_IRQ_RDR3 BIT(7)
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#define SIZE_IN_WORDS(x) ((x) >> 2)
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/**
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* Ring 0/1 are used by AES encrypt and decrypt.
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* Ring 2/3 are used by SHA.
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*/
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enum {
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RING0 = 0,
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RING1,
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RING2,
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RING3,
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RING_MAX,
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};
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#define MTK_REC_NUM (RING_MAX / 2)
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#define MTK_IRQ_NUM 5
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/**
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* struct mtk_desc - DMA descriptor
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* @hdr: the descriptor control header
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* @buf: DMA address of input buffer segment
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* @ct: DMA address of command token that control operation flow
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* @ct_hdr: the command token control header
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* @tag: the user-defined field
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* @tfm: DMA address of transform state
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* @bound: align descriptors offset boundary
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*
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* Structure passed to the crypto engine to describe where source
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* data needs to be fetched and how it needs to be processed.
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*/
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struct mtk_desc {
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__le32 hdr;
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__le32 buf;
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__le32 ct;
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__le32 ct_hdr;
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__le32 tag;
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__le32 tfm;
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__le32 bound[2];
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};
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#define MTK_DESC_NUM 512
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#define MTK_DESC_OFF SIZE_IN_WORDS(sizeof(struct mtk_desc))
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#define MTK_DESC_SZ (MTK_DESC_OFF - 2)
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#define MTK_DESC_RING_SZ ((sizeof(struct mtk_desc) * MTK_DESC_NUM))
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#define MTK_DESC_CNT(x) ((MTK_DESC_OFF * (x)) << 2)
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#define MTK_DESC_LAST cpu_to_le32(BIT(22))
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#define MTK_DESC_FIRST cpu_to_le32(BIT(23))
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#define MTK_DESC_BUF_LEN(x) cpu_to_le32(x)
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#define MTK_DESC_CT_LEN(x) cpu_to_le32((x) << 24)
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/**
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* struct mtk_ring - Descriptor ring
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* @cmd_base: pointer to command descriptor ring base
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* @cmd_dma: DMA address of command descriptor ring
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* @res_base: pointer to result descriptor ring base
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* @res_dma: DMA address of result descriptor ring
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* @pos: current position in the ring
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*
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* A descriptor ring is a circular buffer that is used to manage
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* one or more descriptors. There are two type of descriptor rings;
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* the command descriptor ring and result descriptor ring.
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*/
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struct mtk_ring {
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struct mtk_desc *cmd_base;
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dma_addr_t cmd_dma;
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struct mtk_desc *res_base;
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dma_addr_t res_dma;
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u32 pos;
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};
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/**
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* struct mtk_aes_dma - Structure that holds sg list info
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* @sg: pointer to scatter-gather list
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* @nents: number of entries in the sg list
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* @remainder: remainder of sg list
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* @sg_len: number of entries in the sg mapped list
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*/
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struct mtk_aes_dma {
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struct scatterlist *sg;
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int nents;
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u32 remainder;
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u32 sg_len;
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};
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/**
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* struct mtk_aes_rec - AES operation record
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* @queue: crypto request queue
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* @req: pointer to ablkcipher request
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* @task: the tasklet is use in AES interrupt
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* @src: the structure that holds source sg list info
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* @dst: the structure that holds destination sg list info
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* @aligned_sg: the scatter list is use to alignment
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* @real_dst: pointer to the destination sg list
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* @total: request buffer length
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* @buf: pointer to page buffer
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* @info: pointer to AES transform state and command token
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* @ct_hdr: AES command token control field
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* @ct_size: size of AES command token
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* @ct_dma: DMA address of AES command token
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* @tfm_dma: DMA address of AES transform state
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* @id: record identification
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* @flags: it's describing AES operation state
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* @lock: the ablkcipher queue lock
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*
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* Structure used to record AES execution state.
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*/
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struct mtk_aes_rec {
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struct crypto_queue queue;
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struct ablkcipher_request *req;
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struct tasklet_struct task;
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struct mtk_aes_dma src;
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struct mtk_aes_dma dst;
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struct scatterlist aligned_sg;
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struct scatterlist *real_dst;
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size_t total;
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void *buf;
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void *info;
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__le32 ct_hdr;
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u32 ct_size;
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dma_addr_t ct_dma;
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dma_addr_t tfm_dma;
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u8 id;
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unsigned long flags;
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/* queue lock */
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spinlock_t lock;
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};
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/**
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* struct mtk_sha_rec - SHA operation record
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* @queue: crypto request queue
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* @req: pointer to ahash request
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* @task: the tasklet is use in SHA interrupt
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* @info: pointer to SHA transform state and command token
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* @ct_hdr: SHA command token control field
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* @ct_size: size of SHA command token
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* @ct_dma: DMA address of SHA command token
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* @tfm_dma: DMA address of SHA transform state
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* @id: record identification
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* @flags: it's describing SHA operation state
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* @lock: the ablkcipher queue lock
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*
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* Structure used to record SHA execution state.
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*/
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struct mtk_sha_rec {
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struct crypto_queue queue;
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struct ahash_request *req;
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struct tasklet_struct task;
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void *info;
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__le32 ct_hdr;
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u32 ct_size;
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dma_addr_t ct_dma;
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dma_addr_t tfm_dma;
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u8 id;
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unsigned long flags;
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/* queue lock */
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spinlock_t lock;
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};
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/**
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* struct mtk_cryp - Cryptographic device
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* @base: pointer to mapped register I/O base
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* @dev: pointer to device
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* @clk_ethif: pointer to ethif clock
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* @clk_cryp: pointer to crypto clock
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* @irq: global system and rings IRQ
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* @ring: pointer to execution state of AES
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* @aes: pointer to execution state of SHA
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* @sha: each execution record map to a ring
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* @aes_list: device list of AES
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* @sha_list: device list of SHA
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* @tmp: pointer to temporary buffer for internal use
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* @tmp_dma: DMA address of temporary buffer
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* @rec: it's used to select SHA record for tfm
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*
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* Structure storing cryptographic device information.
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*/
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struct mtk_cryp {
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void __iomem *base;
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struct device *dev;
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struct clk *clk_ethif;
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struct clk *clk_cryp;
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int irq[MTK_IRQ_NUM];
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struct mtk_ring *ring[RING_MAX];
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struct mtk_aes_rec *aes[MTK_REC_NUM];
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struct mtk_sha_rec *sha[MTK_REC_NUM];
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struct list_head aes_list;
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struct list_head sha_list;
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void *tmp;
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dma_addr_t tmp_dma;
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bool rec;
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};
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int mtk_cipher_alg_register(struct mtk_cryp *cryp);
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void mtk_cipher_alg_release(struct mtk_cryp *cryp);
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int mtk_hash_alg_register(struct mtk_cryp *cryp);
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void mtk_hash_alg_release(struct mtk_cryp *cryp);
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#endif /* __MTK_PLATFORM_H_ */
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@@ -0,0 +1,194 @@
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/*
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* Support for MediaTek cryptographic accelerator.
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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*/
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#ifndef __MTK_REGS_H__
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#define __MTK_REGS_H__
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/* HIA, Command Descriptor Ring Manager */
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#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
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#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
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#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
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#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
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#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
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#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
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#define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
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#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
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#define CDR_CFG(x) (0x20 + ((x) << 12))
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#define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
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#define CDR_THRESH(x) (0x28 + ((x) << 12))
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#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12))
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#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12))
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#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12))
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#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12))
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#define CDR_STAT(x) (0x3C + ((x) << 12))
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/* HIA, Result Descriptor Ring Manager */
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#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12))
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#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12))
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#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12))
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#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12))
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#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12))
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#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12))
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#define RDR_RING_SIZE(x) (0x818 + ((x) << 12))
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#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12))
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#define RDR_CFG(x) (0x820 + ((x) << 12))
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#define RDR_DMA_CFG(x) (0x824 + ((x) << 12))
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#define RDR_THRESH(x) (0x828 + ((x) << 12))
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#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12))
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#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12))
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#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12))
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#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12))
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#define RDR_STAT(x) (0x83C + ((x) << 12))
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/* HIA, Ring AIC */
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#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12))
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#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12))
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#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12))
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#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12))
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#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12))
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#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12))
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#define AIC_ACK(x) (0xE010 - ((x) << 12))
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#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12))
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#define AIC_OPTIONS(x) (0xE018 - ((x) << 12))
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#define AIC_VERSION(x) (0xE01C - ((x) << 12))
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/* HIA, Global AIC */
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#define AIC_G_POL_CTRL 0xF800
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#define AIC_G_TYPE_CTRL 0xF804
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#define AIC_G_ENABLE_CTRL 0xF808
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#define AIC_G_RAW_STAT 0xF80C
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#define AIC_G_ENABLE_SET 0xF80C
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#define AIC_G_ENABLED_STAT 0xF810
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#define AIC_G_ACK 0xF810
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#define AIC_G_ENABLE_CLR 0xF814
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#define AIC_G_OPTIONS 0xF818
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#define AIC_G_VERSION 0xF81C
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/* HIA, Data Fetch Engine */
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#define DFE_CFG 0xF000
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#define DFE_PRIO_0 0xF010
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#define DFE_PRIO_1 0xF014
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#define DFE_PRIO_2 0xF018
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#define DFE_PRIO_3 0xF01C
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/* HIA, Data Fetch Engine access monitoring for CDR */
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#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3))
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#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3))
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/* HIA, Data Fetch Engine thread control and status for thread */
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#define DFE_THR_CTRL 0xF200
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#define DFE_THR_STAT 0xF204
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#define DFE_THR_DESC_CTRL 0xF208
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#define DFE_THR_DESC_DPTR_LO 0xF210
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#define DFE_THR_DESC_DPTR_HI 0xF214
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#define DFE_THR_DESC_ACDPTR_LO 0xF218
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#define DFE_THR_DESC_ACDPTR_HI 0xF21C
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/* HIA, Data Store Engine */
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#define DSE_CFG 0xF400
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#define DSE_PRIO_0 0xF410
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#define DSE_PRIO_1 0xF414
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#define DSE_PRIO_2 0xF418
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#define DSE_PRIO_3 0xF41C
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/* HIA, Data Store Engine access monitoring for RDR */
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#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3))
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#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3))
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/* HIA, Data Store Engine thread control and status for thread */
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#define DSE_THR_CTRL 0xF600
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#define DSE_THR_STAT 0xF604
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#define DSE_THR_DESC_CTRL 0xF608
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#define DSE_THR_DESC_DPTR_LO 0xF610
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#define DSE_THR_DESC_DPTR_HI 0xF614
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#define DSE_THR_DESC_S_DPTR_LO 0xF618
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#define DSE_THR_DESC_S_DPTR_HI 0xF61C
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#define DSE_THR_ERROR_STAT 0xF620
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/* HIA Global */
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#define HIA_MST_CTRL 0xFFF4
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#define HIA_OPTIONS 0xFFF8
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#define HIA_VERSION 0xFFFC
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/* Processing Engine Input Side, Processing Engine */
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#define PE_IN_DBUF_THRESH 0x10000
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#define PE_IN_TBUF_THRESH 0x10100
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/* Packet Engine Configuration / Status Registers */
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#define PE_TOKEN_CTRL_STAT 0x11000
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#define PE_FUNCTION_EN 0x11004
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#define PE_CONTEXT_CTRL 0x11008
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#define PE_INTERRUPT_CTRL_STAT 0x11010
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#define PE_CONTEXT_STAT 0x1100C
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#define PE_OUT_TRANS_CTRL_STAT 0x11018
|
||||
#define PE_OUT_BUF_CTRL 0x1101C
|
||||
|
||||
/* Packet Engine PRNG Registers */
|
||||
#define PE_PRNG_STAT 0x11040
|
||||
#define PE_PRNG_CTRL 0x11044
|
||||
#define PE_PRNG_SEED_L 0x11048
|
||||
#define PE_PRNG_SEED_H 0x1104C
|
||||
#define PE_PRNG_KEY_0_L 0x11050
|
||||
#define PE_PRNG_KEY_0_H 0x11054
|
||||
#define PE_PRNG_KEY_1_L 0x11058
|
||||
#define PE_PRNG_KEY_1_H 0x1105C
|
||||
#define PE_PRNG_RES_0 0x11060
|
||||
#define PE_PRNG_RES_1 0x11064
|
||||
#define PE_PRNG_RES_2 0x11068
|
||||
#define PE_PRNG_RES_3 0x1106C
|
||||
#define PE_PRNG_LFSR_L 0x11070
|
||||
#define PE_PRNG_LFSR_H 0x11074
|
||||
|
||||
/* Packet Engine AIC */
|
||||
#define PE_EIP96_AIC_POL_CTRL 0x113C0
|
||||
#define PE_EIP96_AIC_TYPE_CTRL 0x113C4
|
||||
#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8
|
||||
#define PE_EIP96_AIC_RAW_STAT 0x113CC
|
||||
#define PE_EIP96_AIC_ENABLE_SET 0x113CC
|
||||
#define PE_EIP96_AIC_ENABLED_STAT 0x113D0
|
||||
#define PE_EIP96_AIC_ACK 0x113D0
|
||||
#define PE_EIP96_AIC_ENABLE_CLR 0x113D4
|
||||
#define PE_EIP96_AIC_OPTIONS 0x113D8
|
||||
#define PE_EIP96_AIC_VERSION 0x113DC
|
||||
|
||||
/* Packet Engine Options & Version Registers */
|
||||
#define PE_EIP96_OPTIONS 0x113F8
|
||||
#define PE_EIP96_VERSION 0x113FC
|
||||
|
||||
/* Processing Engine Output Side */
|
||||
#define PE_OUT_DBUF_THRESH 0x11C00
|
||||
#define PE_OUT_TBUF_THRESH 0x11D00
|
||||
|
||||
/* Processing Engine Local AIC */
|
||||
#define PE_AIC_POL_CTRL 0x11F00
|
||||
#define PE_AIC_TYPE_CTRL 0x11F04
|
||||
#define PE_AIC_ENABLE_CTRL 0x11F08
|
||||
#define PE_AIC_RAW_STAT 0x11F0C
|
||||
#define PE_AIC_ENABLE_SET 0x11F0C
|
||||
#define PE_AIC_ENABLED_STAT 0x11F10
|
||||
#define PE_AIC_ENABLE_CLR 0x11F14
|
||||
#define PE_AIC_OPTIONS 0x11F18
|
||||
#define PE_AIC_VERSION 0x11F1C
|
||||
|
||||
/* Processing Engine General Configuration and Version */
|
||||
#define PE_IN_FLIGHT 0x11FF0
|
||||
#define PE_OPTIONS 0x11FF8
|
||||
#define PE_VERSION 0x11FFC
|
||||
|
||||
/* EIP-97 - Global */
|
||||
#define EIP97_CLOCK_STATE 0x1FFE4
|
||||
#define EIP97_FORCE_CLOCK_ON 0x1FFE8
|
||||
#define EIP97_FORCE_CLOCK_OFF 0x1FFEC
|
||||
#define EIP97_MST_CTRL 0x1FFF4
|
||||
#define EIP97_OPTIONS 0x1FFF8
|
||||
#define EIP97_VERSION 0x1FFFC
|
||||
#endif /* __MTK_REGS_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user