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Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk updates from Linus Walleij:
"New drivers:
- Qualcomm SDM845: this is their new flagship SoC platform which
seems to be targeted at premium mobile handsets.
- Renesas R-Car M3-N SoC.
- Renesas R8A77980 SoC.
- NXP (ex Freescale) i.MX 6SLL SoC.
- Mediatek MT2712 SoC.
- Allwinner H6 SoC.
Improvements:
- Uniphier adds a few new functions and pins.
- Renesas refactorings and additional pin definitions.
- Improved pin groups for Axis Artpec6.
Cleanup:
- Drop the TZ1090 drivers. This platform is no longer maintained and
is being deleted.
- Drop ST-Ericsson U8540/U9540 support as this was never
productified.
- Overall minor fixes and janitorial"
* tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
pinctrl: uniphier: add UART hardware flow control pin-mux settings
pinctrl: sunxi: add support for the Allwinner H6 main pin controller
pinctrl: sunxi: change irq_bank_base to irq_bank_map
pinctrl: sunxi: introduce IRQ bank conversion function
pinctrl: sunxi: refactor irq related register function to have desc
pinctrl: msm8998: Remove owner assignment from platform_driver
pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group
pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings
pinctrl/amd: poll InterruptEnable bits in enable_irq
pinctrl: ocelot: fix gpio direction
pinctrl: mtk: fix check warnings.
pintcrl: mtk: support bias-disable of generic and special pins simultaneously
pinctrl: add mt2712 pinctrl driver
pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0
pinctrl: imx: Add pinctrl driver support for imx6sll
dt-bindings: imx: update pinctrl doc for imx6sll
pinctrl: intel: Implement intel_gpio_get_direction callback
pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency
pinctrl: mediatek: mtk-common: use true and false for boolean values
pinctrl: sunxi: always look for apb block
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,178 @@
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Actions Semi S900 Pin Controller
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This binding describes the pin controller found in the S900 SoC.
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Required Properties:
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- compatible: Should be "actions,s900-pinctrl"
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- reg: Should contain the register base address and size of
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the pin controller.
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- clocks: phandle of the clock feeding the pin controller
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
|
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subnodes. Each of these subnodes represents some desired configuration for a
|
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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Pinmux functions are available only for the pin groups while pinconf
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parameters are available for both pin groups and individual pins.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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Required Properties:
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- pins: An array of strings, each string containing the name of a pin.
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These pins are used for selecting the pull control and schmitt
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trigger parameters. The following are the list of pins
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available:
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eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
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eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
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sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
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i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
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pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
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eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
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lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
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lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
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lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
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lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
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sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
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sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
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spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
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uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
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uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
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uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
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i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
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csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
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csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
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dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
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csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
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sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
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nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
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nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
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nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
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nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
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nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
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nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
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- groups: An array of strings, each string containing the name of a pin
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group. These pin groups are used for selecting the pinmux
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functions.
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lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
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sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
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rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
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rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
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i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
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pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
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eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
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eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
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lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
|
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spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
|
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uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
|
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sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
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uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
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csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
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dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
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nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
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csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
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These pin groups are used for selecting the drive strength
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parameters.
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sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
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rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
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rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
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sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
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i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
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lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
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sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
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spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
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uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
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These pin groups are used for selecting the slew rate
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parameters.
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sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
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rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
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rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
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i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
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pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
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spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
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uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
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sensor0_sr
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- function: An array of strings, each string containing the name of the
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pinmux functions. These functions can only be selected by
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the corresponding pin groups. The following are the list of
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pinmux functions available:
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eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
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uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
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pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
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sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
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usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
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nand1, spdif, sirq0, sirq1, sirq2
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Optional Properties:
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- bias-bus-hold: No arguments. The specified pins should retain the previous
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state value.
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- bias-high-impedance: No arguments. The specified pins should be configured
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as high impedance.
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- bias-pull-down: No arguments. The specified pins should be configured as
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pull down.
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- bias-pull-up: No arguments. The specified pins should be configured as
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pull up.
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- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
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pins
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- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
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pins
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- slew-rate: Integer. Sets slew rate for the specified pins.
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Valid values are:
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<0> - Slow
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<1> - Fast
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- drive-strength: Integer. Selects the drive strength for the specified
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pins in mA.
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Valid values are:
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<2>
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<4>
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<8>
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<12>
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Example:
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s900-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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uart2-default: uart2-default {
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pinmux {
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groups = "lvds_oep_odn_mfp";
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function = "uart2";
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};
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pinconf {
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groups = "lvds_oep_odn_drv";
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drive-strength = <12>;
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};
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};
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};
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@@ -27,6 +27,7 @@ Required properties:
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"allwinner,sun50i-a64-pinctrl"
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"allwinner,sun50i-a64-r-pinctrl"
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"allwinner,sun50i-h5-pinctrl"
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"allwinner,sun50i-h6-pinctrl"
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"nextthing,gr8-pinctrl"
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- reg: Should contain the register physical address and length for the
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@@ -19,8 +19,10 @@ Required subnode-properties:
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Available functions and groups (function: group0, group1...):
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gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
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i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
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spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
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uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
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spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
|
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uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
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uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
|
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uart5nocts
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cpuclkout: cpuclkoutgrp0
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udlclkout: udlclkoutgrp0
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i2c1: i2c1grp0
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@@ -32,12 +34,12 @@ Required subnode-properties:
|
||||
spi0: spi0grp0
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spi1: spi1grp0
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pciedebug: pciedebuggrp0
|
||||
uart0: uart0grp0, uart0grp1
|
||||
uart1: uart1grp0
|
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uart2: uart2grp0, uart2grp1
|
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uart0: uart0grp0, uart0grp1, uart0grp2
|
||||
uart1: uart1grp0, uart1grp1
|
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uart2: uart2grp0, uart2grp1, uart2grp2
|
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uart3: uart3grp0
|
||||
uart4: uart4grp0
|
||||
uart5: uart5grp0
|
||||
uart4: uart4grp0, uart4grp1
|
||||
uart5: uart5grp0, uart5grp1, uart5nocts
|
||||
nand: nandgrp0
|
||||
sdio0: sdio0grp0
|
||||
sdio1: sdio1grp0
|
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|
||||
@@ -0,0 +1,40 @@
|
||||
* Freescale i.MX6 SLL IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx6sll-iomuxc"
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
||||
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
|
||||
imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
|
||||
the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
|
||||
Reference Manual for detailed CONFIG settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_LVE (1 << 22)
|
||||
PAD_CTL_HYS (1 << 16)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
PAD_CTL_PUE (1 << 13)
|
||||
PAD_CTL_PKE (1 << 12)
|
||||
PAD_CTL_ODE (1 << 11)
|
||||
PAD_CTL_SPEED_LOW (0 << 6)
|
||||
PAD_CTL_SPEED_MED (1 << 6)
|
||||
PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
PAD_CTL_DSE_260ohm (1 << 3)
|
||||
PAD_CTL_DSE_130ohm (2 << 3)
|
||||
PAD_CTL_DSE_87ohm (3 << 3)
|
||||
PAD_CTL_DSE_65ohm (4 << 3)
|
||||
PAD_CTL_DSE_52ohm (5 << 3)
|
||||
PAD_CTL_DSE_43ohm (6 << 3)
|
||||
PAD_CTL_DSE_37ohm (7 << 3)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
Refer to imx6sll-pinfunc.h in device tree source folder for all available
|
||||
imx6sll PIN_FUNC_ID.
|
||||
@@ -1,127 +0,0 @@
|
||||
ImgTec TZ1090 PDC pin controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "img,tz1090-pdc-pinctrl"
|
||||
- reg: Should contain the register physical address and length of the
|
||||
SOC_GPIO_CONTROL registers in the PDC register region.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
|
||||
of subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function. For this reason, even seemingly boolean
|
||||
values are actually tristates in this binding: unspecified, off, or on.
|
||||
Unspecified is represented as an absent property, and off/on are represented as
|
||||
integer values 0 and 1.
|
||||
|
||||
Required subnode-properties:
|
||||
- tz1090,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- tz1090,function: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below, including
|
||||
which pingroups can be muxed to them.
|
||||
- supported generic pinconfig properties (for further details see
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
|
||||
- bias-disable
|
||||
- bias-high-impedance
|
||||
- bias-bus-hold
|
||||
- bias-pull-up
|
||||
- bias-pull-down
|
||||
- input-schmitt-enable
|
||||
- input-schmitt-disable
|
||||
- drive-strength: Integer, control drive strength of pins in mA.
|
||||
2: 2mA
|
||||
4: 4mA
|
||||
8: 8mA
|
||||
12: 12mA
|
||||
- low-power-enable: Flag, power-on-start weak pull-down for invalid power.
|
||||
- low-power-disable: Flag, power-on-start weak pull-down disabled.
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the TZ1090 TRM for complete details regarding which groups
|
||||
support which functionality. The Linux pinctrl driver may also be a useful
|
||||
reference.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
pins:
|
||||
|
||||
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
|
||||
bias-bus-hold (which can also be provided to any of the groups below to set
|
||||
it for all gpio pins in that group).
|
||||
|
||||
gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
|
||||
|
||||
mux groups:
|
||||
|
||||
These all support function.
|
||||
|
||||
gpio0
|
||||
pins: gpio0.
|
||||
function: ir_mod_stable_out.
|
||||
gpio1
|
||||
pins: gpio1.
|
||||
function: ir_mod_power_out.
|
||||
|
||||
drive groups:
|
||||
|
||||
These support input-schmitt-enable, input-schmitt-disable,
|
||||
drive-strength, low-power-enable, and low-power-disable.
|
||||
|
||||
pdc
|
||||
pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
|
||||
ext_power.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl_pdc: pinctrl@2006500 {
|
||||
#gpio-range-cells = <3>;
|
||||
compatible = "img,tz1090-pdc-pinctrl";
|
||||
reg = <0x02006500 0x100>;
|
||||
};
|
||||
|
||||
Example board file extracts:
|
||||
|
||||
&pinctrl_pdc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&syswake_default>;
|
||||
|
||||
syswake_default: syswakes {
|
||||
syswake_cfg {
|
||||
tz1090,pins = "sys_wake0",
|
||||
"sys_wake1",
|
||||
"sys_wake2";
|
||||
pull-up;
|
||||
};
|
||||
};
|
||||
irmod_default: irmod {
|
||||
gpio0_cfg {
|
||||
tz1090,pins = "gpio0";
|
||||
tz1090,function = "ir_mod_stable_out";
|
||||
};
|
||||
gpio1_cfg {
|
||||
tz1090,pins = "gpio1";
|
||||
tz1090,function = "ir_mod_power_out";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ir: ir@2006200 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&irmod_default>;
|
||||
};
|
||||
@@ -1,227 +0,0 @@
|
||||
ImgTec TZ1090 pin controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "img,tz1090-pinctrl"
|
||||
- reg: Should contain the register physical address and length of the pad
|
||||
configuration registers (CR_PADS_* and CR_IF_CTL0).
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function. For this reason, even seemingly boolean
|
||||
values are actually tristates in this binding: unspecified, off, or on.
|
||||
Unspecified is represented as an absent property, and off/on are represented as
|
||||
integer values 0 and 1.
|
||||
|
||||
Required subnode-properties:
|
||||
- tz1090,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- tz1090,function: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below, including
|
||||
which pingroups can be muxed to them.
|
||||
- supported generic pinconfig properties (for further details see
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
|
||||
- bias-disable
|
||||
- bias-high-impedance
|
||||
- bias-bus-hold
|
||||
- bias-pull-up
|
||||
- bias-pull-down
|
||||
- input-schmitt-enable
|
||||
- input-schmitt-disable
|
||||
- drive-strength: Integer, control drive strength of pins in mA.
|
||||
2: 2mA
|
||||
4: 4mA
|
||||
8: 8mA
|
||||
12: 12mA
|
||||
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the TZ1090 TRM for complete details regarding which groups
|
||||
support which functionality. The Linux pinctrl driver may also be a useful
|
||||
reference.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
gpio pins:
|
||||
|
||||
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
|
||||
bias-bus-hold (which can also be provided to any of the groups below to set
|
||||
it for all pins in that group).
|
||||
|
||||
They also all support the some form of muxing. Any pins which are contained
|
||||
in one of the mux groups (see below) can be muxed only to the functions
|
||||
supported by the mux group. All other pins can be muxed to the "perip"
|
||||
function which enables them with their intended peripheral.
|
||||
|
||||
Different pins in the same mux group cannot be muxed to different functions,
|
||||
however it is possible to mux only a subset of the pins in a mux group to a
|
||||
particular function and leave the remaining pins unmuxed. This is useful if
|
||||
the board connects certain pins in a group to other devices to be controlled
|
||||
by GPIO, and you don't want the usual peripheral to have any control of the
|
||||
pin.
|
||||
|
||||
ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
|
||||
i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
|
||||
i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
|
||||
scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
|
||||
sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
|
||||
spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
|
||||
spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
|
||||
tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
|
||||
tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
|
||||
tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
|
||||
tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
|
||||
tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
|
||||
uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
|
||||
|
||||
bias-high-impediance: supported.
|
||||
bias-pull-up: supported.
|
||||
bias-pull-down: supported.
|
||||
bias-bus-hold: supported.
|
||||
function: perip or those supported by pin's mux group.
|
||||
|
||||
other pins:
|
||||
|
||||
These other pins are part of various pin groups below, but can't be
|
||||
controlled as GPIOs. They do however support bias-high-impediance,
|
||||
bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
|
||||
to any of the groups below to set it for all pins in that group).
|
||||
|
||||
clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
|
||||
|
||||
bias-high-impediance: supported.
|
||||
bias-pull-up: supported.
|
||||
bias-pull-down: supported.
|
||||
bias-bus-hold: supported.
|
||||
|
||||
mux groups:
|
||||
|
||||
These all support function, and some support drive configs.
|
||||
|
||||
afe
|
||||
pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
|
||||
ant_sel1, gain0, gain1, gain2, gain3, gain4,
|
||||
gain5, gain6, gain7.
|
||||
function: afe, ts_out_0.
|
||||
input-schmitt-enable: supported.
|
||||
input-schmitt-disable: supported.
|
||||
drive-strength: supported.
|
||||
pdm_d
|
||||
pins: pdm_d.
|
||||
function: pdm_dac, usb_vbus.
|
||||
sdh
|
||||
pins: sdh_cd, sdh_wp, sdh_clk_in.
|
||||
function: sdh, sdio.
|
||||
sdio
|
||||
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
|
||||
sdio_d3.
|
||||
function: sdio, sdh.
|
||||
spi1_cs2
|
||||
pins: spi1_cs2.
|
||||
function: spi1_cs2, usb_vbus.
|
||||
tft
|
||||
pins: tft_red0, tft_red1, tft_red2, tft_red3,
|
||||
tft_red4, tft_red5, tft_red6, tft_red7,
|
||||
tft_green0, tft_green1, tft_green2, tft_green3,
|
||||
tft_green4, tft_green5, tft_green6, tft_green7,
|
||||
tft_blue0, tft_blue1, tft_blue2, tft_blue3,
|
||||
tft_blue4, tft_blue5, tft_blue6, tft_blue7,
|
||||
tft_vdden_gd, tft_panelclk, tft_blank_ls,
|
||||
tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
|
||||
tft_pwrsave.
|
||||
function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
|
||||
lcd_trace, phy_ringosc.
|
||||
input-schmitt-enable: supported.
|
||||
input-schmitt-disable: supported.
|
||||
drive-strength: supported.
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support input-schmitt-enable, input-schmitt-disable,
|
||||
and drive-strength.
|
||||
|
||||
jtag
|
||||
pins: tck, trst, tdi, tdo, tms.
|
||||
scb1
|
||||
pins: scb1_sdat, scb1_sclk.
|
||||
scb2
|
||||
pins: scb2_sdat, scb2_sclk.
|
||||
spi0
|
||||
pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
|
||||
spi1
|
||||
pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
|
||||
uart
|
||||
pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
|
||||
uart1_txd, uart1_rxd.
|
||||
drive_i2s
|
||||
pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
|
||||
i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
|
||||
drive_pdm
|
||||
pins: clk_out0, pdm_b, pdm_a.
|
||||
drive_scb0
|
||||
pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
|
||||
drive_sdio
|
||||
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
|
||||
sdh_wp, sdh_cd, sdh_clk_in.
|
||||
|
||||
convenience groups:
|
||||
|
||||
These are just convenient groupings of pins and don't support any drive
|
||||
configs.
|
||||
|
||||
uart0
|
||||
pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
|
||||
uart1
|
||||
pins: uart1_rxd, uart1_txd.
|
||||
scb0
|
||||
pins: scb0_sclk, scb0_sdat.
|
||||
i2s
|
||||
pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
|
||||
i2s_lrclk_out, i2s_mclk.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl: pinctrl@2005800 {
|
||||
#gpio-range-cells = <3>;
|
||||
compatible = "img,tz1090-pinctrl";
|
||||
reg = <0x02005800 0xe4>;
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
&pinctrl {
|
||||
uart0_default: uart0 {
|
||||
uart0_cfg {
|
||||
tz1090,pins = "uart0_rxd",
|
||||
"uart0_txd";
|
||||
tz1090,function = "perip";
|
||||
};
|
||||
};
|
||||
tft_default: tft {
|
||||
tft_cfg {
|
||||
tz1090,pins = "tft";
|
||||
tz1090,function = "tft";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart@2004b00 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_default>;
|
||||
};
|
||||
@@ -45,6 +45,8 @@ Optional properties:
|
||||
- first cell is the pin number
|
||||
- second cell is used to specify flags.
|
||||
- interrupt-controller: Marks the device node as a interrupt controller.
|
||||
- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
|
||||
the IRQ output as open drain active low.
|
||||
|
||||
Optional device specific properties:
|
||||
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
|
||||
|
||||
@@ -76,12 +76,12 @@ Examples:
|
||||
|
||||
...
|
||||
{
|
||||
syscfg_pctl_a: syscfg_pctl_a@10005000 {
|
||||
syscfg_pctl_a: syscfg-pctl-a@10005000 {
|
||||
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
syscfg_pctl_b: syscfg_pctl_b@1020c020 {
|
||||
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
|
||||
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
|
||||
reg = <0 0x1020C020 0 0x1000>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,176 @@
|
||||
Qualcomm SDM845 TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDM845 platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdm845-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc2_clk, sdc2_cmd, sdc2_data
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
|
||||
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
|
||||
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
|
||||
atest_usb21, atest_usb22, atest_usb23, audio_ref,
|
||||
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
|
||||
gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
|
||||
lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
|
||||
pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
|
||||
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
|
||||
qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
|
||||
qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
|
||||
qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
|
||||
qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
|
||||
sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
|
||||
tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
|
||||
tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
|
||||
tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
|
||||
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
|
||||
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
|
||||
vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
|
||||
wlan2_adc1,
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configued as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@3400000 {
|
||||
compatible = "qcom,sdm845-pinctrl";
|
||||
reg = <0x03400000 0xc00000>;
|
||||
interrupts = <GIC_SPI 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
qup9_active: qup9-active {
|
||||
mux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "qup9";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -15,7 +15,7 @@ Required Properties:
|
||||
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
|
||||
@@ -24,7 +24,9 @@ Required Properties:
|
||||
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
|
||||
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
|
||||
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
|
||||
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
|
||||
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
|
||||
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
|
||||
|
||||
|
||||
@@ -244,18 +244,6 @@ config PINCTRL_ST
|
||||
select PINCONF
|
||||
select GPIOLIB_IRQCHIP
|
||||
|
||||
config PINCTRL_TZ1090
|
||||
bool "Toumaz Xenif TZ1090 pin control driver"
|
||||
depends on SOC_TZ1090
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
config PINCTRL_TZ1090_PDC
|
||||
bool "Toumaz Xenif TZ1090 PDC pin control driver"
|
||||
depends on SOC_TZ1090
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_U300
|
||||
bool "U300 pin controller driver"
|
||||
depends on ARCH_U300
|
||||
|
||||
@@ -31,8 +31,6 @@ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
|
||||
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
|
||||
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
|
||||
obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
|
||||
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
|
||||
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
|
||||
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
|
||||
|
||||
+29
-80
@@ -1416,6 +1416,7 @@ int pinctrl_register_mappings(const struct pinctrl_map *maps,
|
||||
{
|
||||
return pinctrl_register_map(maps, num_maps, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_register_mappings);
|
||||
|
||||
void pinctrl_unregister_map(const struct pinctrl_map *map)
|
||||
{
|
||||
@@ -1586,6 +1587,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl_pins);
|
||||
|
||||
static int pinctrl_groups_show(struct seq_file *s, void *what)
|
||||
{
|
||||
@@ -1631,6 +1633,7 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl_groups);
|
||||
|
||||
static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
|
||||
{
|
||||
@@ -1664,6 +1667,7 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl_gpioranges);
|
||||
|
||||
static int pinctrl_devices_show(struct seq_file *s, void *what)
|
||||
{
|
||||
@@ -1690,6 +1694,7 @@ static int pinctrl_devices_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl_devices);
|
||||
|
||||
static inline const char *map_type(enum pinctrl_map_type type)
|
||||
{
|
||||
@@ -1743,6 +1748,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl_maps);
|
||||
|
||||
static int pinctrl_show(struct seq_file *s, void *what)
|
||||
{
|
||||
@@ -1788,87 +1794,30 @@ static int pinctrl_show(struct seq_file *s, void *what)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinctrl_pins_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_pins_show, inode->i_private);
|
||||
}
|
||||
|
||||
static int pinctrl_groups_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_groups_show, inode->i_private);
|
||||
}
|
||||
|
||||
static int pinctrl_gpioranges_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_gpioranges_show, inode->i_private);
|
||||
}
|
||||
|
||||
static int pinctrl_devices_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_devices_show, NULL);
|
||||
}
|
||||
|
||||
static int pinctrl_maps_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_maps_show, NULL);
|
||||
}
|
||||
|
||||
static int pinctrl_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pinctrl_show, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations pinctrl_pins_ops = {
|
||||
.open = pinctrl_pins_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct file_operations pinctrl_groups_ops = {
|
||||
.open = pinctrl_groups_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct file_operations pinctrl_gpioranges_ops = {
|
||||
.open = pinctrl_gpioranges_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct file_operations pinctrl_devices_ops = {
|
||||
.open = pinctrl_devices_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct file_operations pinctrl_maps_ops = {
|
||||
.open = pinctrl_maps_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static const struct file_operations pinctrl_ops = {
|
||||
.open = pinctrl_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
DEFINE_SHOW_ATTRIBUTE(pinctrl);
|
||||
|
||||
static struct dentry *debugfs_root;
|
||||
|
||||
static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct dentry *device_root;
|
||||
const char *debugfs_name;
|
||||
|
||||
device_root = debugfs_create_dir(dev_name(pctldev->dev),
|
||||
debugfs_root);
|
||||
if (pctldev->desc->name &&
|
||||
strcmp(dev_name(pctldev->dev), pctldev->desc->name)) {
|
||||
debugfs_name = devm_kasprintf(pctldev->dev, GFP_KERNEL,
|
||||
"%s-%s", dev_name(pctldev->dev),
|
||||
pctldev->desc->name);
|
||||
if (!debugfs_name) {
|
||||
pr_warn("failed to determine debugfs dir name for %s\n",
|
||||
dev_name(pctldev->dev));
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
debugfs_name = dev_name(pctldev->dev);
|
||||
}
|
||||
|
||||
device_root = debugfs_create_dir(debugfs_name, debugfs_root);
|
||||
pctldev->device_root = device_root;
|
||||
|
||||
if (IS_ERR(device_root) || !device_root) {
|
||||
@@ -1877,11 +1826,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
|
||||
return;
|
||||
}
|
||||
debugfs_create_file("pins", S_IFREG | S_IRUGO,
|
||||
device_root, pctldev, &pinctrl_pins_ops);
|
||||
device_root, pctldev, &pinctrl_pins_fops);
|
||||
debugfs_create_file("pingroups", S_IFREG | S_IRUGO,
|
||||
device_root, pctldev, &pinctrl_groups_ops);
|
||||
device_root, pctldev, &pinctrl_groups_fops);
|
||||
debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
|
||||
device_root, pctldev, &pinctrl_gpioranges_ops);
|
||||
device_root, pctldev, &pinctrl_gpioranges_fops);
|
||||
if (pctldev->desc->pmxops)
|
||||
pinmux_init_device_debugfs(device_root, pctldev);
|
||||
if (pctldev->desc->confops)
|
||||
@@ -1903,11 +1852,11 @@ static void pinctrl_init_debugfs(void)
|
||||
}
|
||||
|
||||
debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
|
||||
debugfs_root, NULL, &pinctrl_devices_ops);
|
||||
debugfs_root, NULL, &pinctrl_devices_fops);
|
||||
debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO,
|
||||
debugfs_root, NULL, &pinctrl_maps_ops);
|
||||
debugfs_root, NULL, &pinctrl_maps_fops);
|
||||
debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO,
|
||||
debugfs_root, NULL, &pinctrl_ops);
|
||||
debugfs_root, NULL, &pinctrl_fops);
|
||||
}
|
||||
|
||||
#else /* CONFIG_DEBUG_FS */
|
||||
|
||||
@@ -122,8 +122,10 @@ static int dt_to_map_one_config(struct pinctrl *p,
|
||||
/* OK let's just assume this will appear later then */
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
if (!pctldev)
|
||||
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
|
||||
/* If we're creating a hog we can use the passed pctldev */
|
||||
if (pctldev && (np_pctldev == p->dev->of_node))
|
||||
break;
|
||||
pctldev = get_pinctrl_dev_from_of_node(np_pctldev);
|
||||
if (pctldev)
|
||||
break;
|
||||
/* Do not defer probing of hogs (circular loop) */
|
||||
|
||||
@@ -82,6 +82,13 @@ config PINCTRL_IMX6SL
|
||||
help
|
||||
Say Y here to enable the imx6sl pinctrl driver
|
||||
|
||||
config PINCTRL_IMX6SLL
|
||||
bool "IMX6SLL pinctrl driver"
|
||||
depends on SOC_IMX6SLL
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx6sll pinctrl driver
|
||||
|
||||
config PINCTRL_IMX6SX
|
||||
bool "IMX6SX pinctrl driver"
|
||||
depends on SOC_IMX6SX
|
||||
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6SLL) += pinctrl-imx6sll.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
|
||||
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
|
||||
|
||||
@@ -0,0 +1,360 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx6sll_pads {
|
||||
MX6SLL_PAD_RESERVE0 = 0,
|
||||
MX6SLL_PAD_RESERVE1 = 1,
|
||||
MX6SLL_PAD_RESERVE2 = 2,
|
||||
MX6SLL_PAD_RESERVE3 = 3,
|
||||
MX6SLL_PAD_RESERVE4 = 4,
|
||||
MX6SLL_PAD_WDOG_B = 5,
|
||||
MX6SLL_PAD_REF_CLK_24M = 6,
|
||||
MX6SLL_PAD_REF_CLK_32K = 7,
|
||||
MX6SLL_PAD_PWM1 = 8,
|
||||
MX6SLL_PAD_KEY_COL0 = 9,
|
||||
MX6SLL_PAD_KEY_ROW0 = 10,
|
||||
MX6SLL_PAD_KEY_COL1 = 11,
|
||||
MX6SLL_PAD_KEY_ROW1 = 12,
|
||||
MX6SLL_PAD_KEY_COL2 = 13,
|
||||
MX6SLL_PAD_KEY_ROW2 = 14,
|
||||
MX6SLL_PAD_KEY_COL3 = 15,
|
||||
MX6SLL_PAD_KEY_ROW3 = 16,
|
||||
MX6SLL_PAD_KEY_COL4 = 17,
|
||||
MX6SLL_PAD_KEY_ROW4 = 18,
|
||||
MX6SLL_PAD_KEY_COL5 = 19,
|
||||
MX6SLL_PAD_KEY_ROW5 = 20,
|
||||
MX6SLL_PAD_KEY_COL6 = 21,
|
||||
MX6SLL_PAD_KEY_ROW6 = 22,
|
||||
MX6SLL_PAD_KEY_COL7 = 23,
|
||||
MX6SLL_PAD_KEY_ROW7 = 24,
|
||||
MX6SLL_PAD_EPDC_DATA00 = 25,
|
||||
MX6SLL_PAD_EPDC_DATA01 = 26,
|
||||
MX6SLL_PAD_EPDC_DATA02 = 27,
|
||||
MX6SLL_PAD_EPDC_DATA03 = 28,
|
||||
MX6SLL_PAD_EPDC_DATA04 = 29,
|
||||
MX6SLL_PAD_EPDC_DATA05 = 30,
|
||||
MX6SLL_PAD_EPDC_DATA06 = 31,
|
||||
MX6SLL_PAD_EPDC_DATA07 = 32,
|
||||
MX6SLL_PAD_EPDC_DATA08 = 33,
|
||||
MX6SLL_PAD_EPDC_DATA09 = 34,
|
||||
MX6SLL_PAD_EPDC_DATA10 = 35,
|
||||
MX6SLL_PAD_EPDC_DATA11 = 36,
|
||||
MX6SLL_PAD_EPDC_DATA12 = 37,
|
||||
MX6SLL_PAD_EPDC_DATA13 = 38,
|
||||
MX6SLL_PAD_EPDC_DATA14 = 39,
|
||||
MX6SLL_PAD_EPDC_DATA15 = 40,
|
||||
MX6SLL_PAD_EPDC_SDCLK = 41,
|
||||
MX6SLL_PAD_EPDC_SDLE = 42,
|
||||
MX6SLL_PAD_EPDC_SDOE = 43,
|
||||
MX6SLL_PAD_EPDC_SDSHR = 44,
|
||||
MX6SLL_PAD_EPDC_SDCE0 = 45,
|
||||
MX6SLL_PAD_EPDC_SDCE1 = 46,
|
||||
MX6SLL_PAD_EPDC_SDCE2 = 47,
|
||||
MX6SLL_PAD_EPDC_SDCE3 = 48,
|
||||
MX6SLL_PAD_EPDC_GDCLK = 49,
|
||||
MX6SLL_PAD_EPDC_GDOE = 50,
|
||||
MX6SLL_PAD_EPDC_GDRL = 51,
|
||||
MX6SLL_PAD_EPDC_GDSP = 52,
|
||||
MX6SLL_PAD_EPDC_VCOM0 = 53,
|
||||
MX6SLL_PAD_EPDC_VCOM1 = 54,
|
||||
MX6SLL_PAD_EPDC_BDR0 = 55,
|
||||
MX6SLL_PAD_EPDC_BDR1 = 56,
|
||||
MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
|
||||
MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
|
||||
MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
|
||||
MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
|
||||
MX6SLL_PAD_EPDC_PWR_COM = 61,
|
||||
MX6SLL_PAD_EPDC_PWR_INT = 62,
|
||||
MX6SLL_PAD_EPDC_PWR_STAT = 63,
|
||||
MX6SLL_PAD_EPDC_PWR_WAKE = 64,
|
||||
MX6SLL_PAD_LCD_CLK = 65,
|
||||
MX6SLL_PAD_LCD_ENABLE = 66,
|
||||
MX6SLL_PAD_LCD_HSYNC = 67,
|
||||
MX6SLL_PAD_LCD_VSYNC = 68,
|
||||
MX6SLL_PAD_LCD_RESET = 69,
|
||||
MX6SLL_PAD_LCD_DATA00 = 70,
|
||||
MX6SLL_PAD_LCD_DATA01 = 71,
|
||||
MX6SLL_PAD_LCD_DATA02 = 72,
|
||||
MX6SLL_PAD_LCD_DATA03 = 73,
|
||||
MX6SLL_PAD_LCD_DATA04 = 74,
|
||||
MX6SLL_PAD_LCD_DATA05 = 75,
|
||||
MX6SLL_PAD_LCD_DATA06 = 76,
|
||||
MX6SLL_PAD_LCD_DATA07 = 77,
|
||||
MX6SLL_PAD_LCD_DATA08 = 78,
|
||||
MX6SLL_PAD_LCD_DATA09 = 79,
|
||||
MX6SLL_PAD_LCD_DATA10 = 80,
|
||||
MX6SLL_PAD_LCD_DATA11 = 81,
|
||||
MX6SLL_PAD_LCD_DATA12 = 82,
|
||||
MX6SLL_PAD_LCD_DATA13 = 83,
|
||||
MX6SLL_PAD_LCD_DATA14 = 84,
|
||||
MX6SLL_PAD_LCD_DATA15 = 85,
|
||||
MX6SLL_PAD_LCD_DATA16 = 86,
|
||||
MX6SLL_PAD_LCD_DATA17 = 87,
|
||||
MX6SLL_PAD_LCD_DATA18 = 88,
|
||||
MX6SLL_PAD_LCD_DATA19 = 89,
|
||||
MX6SLL_PAD_LCD_DATA20 = 90,
|
||||
MX6SLL_PAD_LCD_DATA21 = 91,
|
||||
MX6SLL_PAD_LCD_DATA22 = 92,
|
||||
MX6SLL_PAD_LCD_DATA23 = 93,
|
||||
MX6SLL_PAD_AUD_RXFS = 94,
|
||||
MX6SLL_PAD_AUD_RXC = 95,
|
||||
MX6SLL_PAD_AUD_RXD = 96,
|
||||
MX6SLL_PAD_AUD_TXC = 97,
|
||||
MX6SLL_PAD_AUD_TXFS = 98,
|
||||
MX6SLL_PAD_AUD_TXD = 99,
|
||||
MX6SLL_PAD_AUD_MCLK = 100,
|
||||
MX6SLL_PAD_UART1_RXD = 101,
|
||||
MX6SLL_PAD_UART1_TXD = 102,
|
||||
MX6SLL_PAD_I2C1_SCL = 103,
|
||||
MX6SLL_PAD_I2C1_SDA = 104,
|
||||
MX6SLL_PAD_I2C2_SCL = 105,
|
||||
MX6SLL_PAD_I2C2_SDA = 106,
|
||||
MX6SLL_PAD_ECSPI1_SCLK = 107,
|
||||
MX6SLL_PAD_ECSPI1_MOSI = 108,
|
||||
MX6SLL_PAD_ECSPI1_MISO = 109,
|
||||
MX6SLL_PAD_ECSPI1_SS0 = 110,
|
||||
MX6SLL_PAD_ECSPI2_SCLK = 111,
|
||||
MX6SLL_PAD_ECSPI2_MOSI = 112,
|
||||
MX6SLL_PAD_ECSPI2_MISO = 113,
|
||||
MX6SLL_PAD_ECSPI2_SS0 = 114,
|
||||
MX6SLL_PAD_SD1_CLK = 115,
|
||||
MX6SLL_PAD_SD1_CMD = 116,
|
||||
MX6SLL_PAD_SD1_DATA0 = 117,
|
||||
MX6SLL_PAD_SD1_DATA1 = 118,
|
||||
MX6SLL_PAD_SD1_DATA2 = 119,
|
||||
MX6SLL_PAD_SD1_DATA3 = 120,
|
||||
MX6SLL_PAD_SD1_DATA4 = 121,
|
||||
MX6SLL_PAD_SD1_DATA5 = 122,
|
||||
MX6SLL_PAD_SD1_DATA6 = 123,
|
||||
MX6SLL_PAD_SD1_DATA7 = 124,
|
||||
MX6SLL_PAD_SD2_RESET = 125,
|
||||
MX6SLL_PAD_SD2_CLK = 126,
|
||||
MX6SLL_PAD_SD2_CMD = 127,
|
||||
MX6SLL_PAD_SD2_DATA0 = 128,
|
||||
MX6SLL_PAD_SD2_DATA1 = 129,
|
||||
MX6SLL_PAD_SD2_DATA2 = 130,
|
||||
MX6SLL_PAD_SD2_DATA3 = 131,
|
||||
MX6SLL_PAD_SD2_DATA4 = 132,
|
||||
MX6SLL_PAD_SD2_DATA5 = 133,
|
||||
MX6SLL_PAD_SD2_DATA6 = 134,
|
||||
MX6SLL_PAD_SD2_DATA7 = 135,
|
||||
MX6SLL_PAD_SD3_CLK = 136,
|
||||
MX6SLL_PAD_SD3_CMD = 137,
|
||||
MX6SLL_PAD_SD3_DATA0 = 138,
|
||||
MX6SLL_PAD_SD3_DATA1 = 139,
|
||||
MX6SLL_PAD_SD3_DATA2 = 140,
|
||||
MX6SLL_PAD_SD3_DATA3 = 141,
|
||||
MX6SLL_PAD_GPIO4_IO20 = 142,
|
||||
MX6SLL_PAD_GPIO4_IO21 = 143,
|
||||
MX6SLL_PAD_GPIO4_IO19 = 144,
|
||||
MX6SLL_PAD_GPIO4_IO25 = 145,
|
||||
MX6SLL_PAD_GPIO4_IO18 = 146,
|
||||
MX6SLL_PAD_GPIO4_IO24 = 147,
|
||||
MX6SLL_PAD_GPIO4_IO23 = 148,
|
||||
MX6SLL_PAD_GPIO4_IO17 = 149,
|
||||
MX6SLL_PAD_GPIO4_IO22 = 150,
|
||||
MX6SLL_PAD_GPIO4_IO16 = 151,
|
||||
MX6SLL_PAD_GPIO4_IO26 = 152,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
|
||||
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
|
||||
.pins = imx6sll_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
|
||||
.gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
|
||||
};
|
||||
|
||||
static const struct of_device_id imx6sll_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx6sll_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx6sll_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx6sll-pinctrl",
|
||||
.of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imx6sll_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx6sll_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx6sll_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx6sll_pinctrl_init);
|
||||
@@ -788,6 +788,24 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
|
||||
}
|
||||
|
||||
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
void __iomem *reg;
|
||||
u32 padcfg0;
|
||||
|
||||
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
|
||||
if (!reg)
|
||||
return -EINVAL;
|
||||
|
||||
padcfg0 = readl(reg);
|
||||
|
||||
if (padcfg0 & PADCFG0_PMODE_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
return !!(padcfg0 & PADCFG0_GPIOTXDIS);
|
||||
}
|
||||
|
||||
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_gpio_direction_input(chip->base + offset);
|
||||
@@ -804,6 +822,7 @@ static const struct gpio_chip intel_gpio_chip = {
|
||||
.owner = THIS_MODULE,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.get_direction = intel_gpio_get_direction,
|
||||
.direction_input = intel_gpio_direction_input,
|
||||
.direction_output = intel_gpio_direction_output,
|
||||
.get = intel_gpio_get,
|
||||
|
||||
@@ -32,6 +32,13 @@ config PINCTRL_MT8127
|
||||
select PINCTRL_MTK
|
||||
|
||||
# For ARMv8 SoCs
|
||||
config PINCTRL_MT2712
|
||||
bool "MediaTek MT2712 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK
|
||||
|
||||
config PINCTRL_MT7622
|
||||
bool "MediaTek MT7622 pin control"
|
||||
depends on OF
|
||||
|
||||
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
|
||||
|
||||
# SoC Drivers
|
||||
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
|
||||
obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
|
||||
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
|
||||
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
|
||||
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user