Merge 3.8-rc5 into char-misc-next

This pulls in all of the 3.8-rc5 fixes into this branch so we can test easier.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
2013-01-25 12:34:27 -08:00
247 changed files with 2027 additions and 1228 deletions
@@ -81,7 +81,8 @@ PA31 TXD4
Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
The PERIPH 0 means gpio.
The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin need a pull up.
@@ -126,7 +127,7 @@ pinctrl@fffff400 {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x1>; /* PB15 periph with pullup */
1 15 0x1 0x1>; /* PB15 periph A with pullup */
};
};
};
+9 -9
View File
@@ -175,9 +175,9 @@ consists of multiple segments as described below.
align with the zone size <-|
|-> align with the segment size
_________________________________________________________________________
| | | Node | Segment | Segment | |
| Superblock | Checkpoint | Address | Info. | Summary | Main |
| (SB) | (CP) | Table (NAT) | Table (SIT) | Area (SSA) | |
| | | Segment | Node | Segment | |
| Superblock | Checkpoint | Info. | Address | Summary | Main |
| (SB) | (CP) | Table (SIT) | Table (NAT) | Area (SSA) | |
|____________|_____2______|______N______|______N______|______N_____|__N___|
. .
. .
@@ -200,14 +200,14 @@ consists of multiple segments as described below.
: It contains file system information, bitmaps for valid NAT/SIT sets, orphan
inode lists, and summary entries of current active segments.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Information Table (SIT)
: It contains segment information such as valid block count and bitmap for the
validity of all the blocks.
- Node Address Table (NAT)
: It is composed of a block address table for all the node blocks stored in
Main area.
- Segment Summary Area (SSA)
: It contains summary entries which contains the owner information of all the
data and node blocks stored in Main area.
@@ -236,13 +236,13 @@ For file system consistency, each CP points to which NAT and SIT copies are
valid, as shown as below.
+--------+----------+---------+
| CP | NAT | SIT |
| CP | SIT | NAT |
+--------+----------+---------+
. . . .
. . . .
. . . .
+-------+-------+--------+--------+--------+--------+
| CP #0 | CP #1 | NAT #0 | NAT #1 | SIT #0 | SIT #1 |
| CP #0 | CP #1 | SIT #0 | SIT #1 | NAT #0 | NAT #1 |
+-------+-------+--------+--------+--------+--------+
| ^ ^
| | |
+1 -1
View File
@@ -6592,7 +6592,7 @@ F: drivers/media/platform/s3c-camif/
F: include/media/s3c_camif.h
SERIAL DRIVERS
M: Alan Cox <alan@linux.intel.com>
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial
+2 -2
View File
@@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 8
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME = Terrified Chipmunk
# *DOCUMENTATION*
@@ -169,7 +169,7 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
-e s/arm.*/arm/ -e s/sa110/arm/ \
-e s/s390x/s390/ -e s/parisc64/parisc/ \
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
-e s/sh[234].*/sh/ )
-e s/sh[234].*/sh/ -e s/aarch64.*/arm64/ )
# Cross compiling and selecting different set of gcc/bin-utils
# ---------------------------------------------------------------------------
+1 -1
View File
@@ -26,7 +26,7 @@
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
reg = <0x00000000 0x40000000>; /* 1 GB */
};
soc {
+6 -8
View File
@@ -50,27 +50,25 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>;
interrupts = <87>, <88>, <89>;
};
};
};
+9 -12
View File
@@ -51,39 +51,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {
+9 -12
View File
@@ -66,39 +66,36 @@
};
gpio0: gpio@d0018100 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018100 0x40>,
<0xd0018800 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018140 0x40>,
<0xd0018840 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <20>, <21>, <22>, <23>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,armadaxp-gpio";
reg = <0xd0018180 0x40>,
<0xd0018870 0x30>;
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <24>;
interrupts = <91>;
};
ethernet@d0034000 {
+2 -2
View File
@@ -336,8 +336,8 @@
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
gpios = <&pioA 25 0 /* sda */
&pioA 26 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
+40 -20
View File
@@ -143,6 +143,11 @@
atmel,pins =
<0 3 0x1 0x0>; /* PA3 periph A */
};
pinctrl_usart0_sck: usart0_sck-0 {
atmel,pins =
<0 4 0x1 0x0>; /* PA4 periph A */
};
};
usart1 {
@@ -154,12 +159,17 @@
pinctrl_usart1_rts: usart1_rts-0 {
atmel,pins =
<3 27 0x3 0x0>; /* PC27 periph C */
<2 27 0x3 0x0>; /* PC27 periph C */
};
pinctrl_usart1_cts: usart1_cts-0 {
atmel,pins =
<3 28 0x3 0x0>; /* PC28 periph C */
<2 28 0x3 0x0>; /* PC28 periph C */
};
pinctrl_usart1_sck: usart1_sck-0 {
atmel,pins =
<2 28 0x3 0x0>; /* PC29 periph C */
};
};
@@ -172,46 +182,56 @@
pinctrl_uart2_rts: uart2_rts-0 {
atmel,pins =
<0 0 0x2 0x0>; /* PB0 periph B */
<1 0 0x2 0x0>; /* PB0 periph B */
};
pinctrl_uart2_cts: uart2_cts-0 {
atmel,pins =
<0 1 0x2 0x0>; /* PB1 periph B */
<1 1 0x2 0x0>; /* PB1 periph B */
};
pinctrl_usart2_sck: usart2_sck-0 {
atmel,pins =
<1 2 0x2 0x0>; /* PB2 periph B */
};
};
usart3 {
pinctrl_uart3: usart3-0 {
atmel,pins =
<3 23 0x2 0x1 /* PC22 periph B with pullup */
3 23 0x2 0x0>; /* PC23 periph B */
<2 23 0x2 0x1 /* PC22 periph B with pullup */
2 23 0x2 0x0>; /* PC23 periph B */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
<3 24 0x2 0x0>; /* PC24 periph B */
<2 24 0x2 0x0>; /* PC24 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
<3 25 0x2 0x0>; /* PC25 periph B */
<2 25 0x2 0x0>; /* PC25 periph B */
};
pinctrl_usart3_sck: usart3_sck-0 {
atmel,pins =
<2 26 0x2 0x0>; /* PC26 periph B */
};
};
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<3 8 0x3 0x0 /* PC8 periph C */
3 9 0x3 0x1>; /* PC9 periph C with pullup */
<2 8 0x3 0x0 /* PC8 periph C */
2 9 0x3 0x1>; /* PC9 periph C with pullup */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<3 16 0x3 0x0 /* PC16 periph C */
3 17 0x3 0x1>; /* PC17 periph C with pullup */
<2 16 0x3 0x0 /* PC16 periph C */
2 17 0x3 0x1>; /* PC17 periph C with pullup */
};
};
@@ -240,14 +260,14 @@
pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
atmel,pins =
<1 8 0x1 0x0 /* PA8 periph A */
1 11 0x1 0x0 /* PA11 periph A */
1 12 0x1 0x0 /* PA12 periph A */
1 13 0x1 0x0 /* PA13 periph A */
1 14 0x1 0x0 /* PA14 periph A */
1 15 0x1 0x0 /* PA15 periph A */
1 16 0x1 0x0 /* PA16 periph A */
1 17 0x1 0x0>; /* PA17 periph A */
<1 8 0x1 0x0 /* PB8 periph A */
1 11 0x1 0x0 /* PB11 periph A */
1 12 0x1 0x0 /* PB12 periph A */
1 13 0x1 0x0 /* PB13 periph A */
1 14 0x1 0x0 /* PB14 periph A */
1 15 0x1 0x0 /* PB15 periph A */
1 16 0x1 0x0 /* PB16 periph A */
1 17 0x1 0x0>; /* PB17 periph A */
};
};
+6 -6
View File
@@ -96,8 +96,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@@ -120,8 +120,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@@ -141,8 +141,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
+12 -2
View File
@@ -26,10 +26,15 @@
};
&uart0 { status = "okay"; };
&sdio0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
&sdio0 {
status = "okay";
/* sdio0 card detect is connected to wrong pin on CuBox */
cd-gpios = <&gpio0 12 1>;
};
&spi0 {
status = "okay";
@@ -42,9 +47,14 @@
};
&pinctrl {
pinctrl-0 = <&pmx_gpio_18>;
pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>;
pinctrl-names = "default";
pmx_gpio_12: pmx-gpio-12 {
marvell,pins = "mpp12";
marvell,function = "gpio";
};
pmx_gpio_18: pmx-gpio-18 {
marvell,pins = "mpp18";
marvell,function = "gpio";
+4 -4
View File
@@ -115,8 +115,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@@ -139,8 +139,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3 3>;
samsung,dw-mshc-ddr-timing = <1 2 3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
@@ -1,4 +1,5 @@
/include/ "kirkwood.dtsi"
/include/ "kirkwood-6281.dtsi"
/ {
chosen {
@@ -6,6 +7,21 @@
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
&pmx_ns2_sata0 &pmx_ns2_sata1>;
pinctrl-names = "default";
pmx_ns2_sata0: pmx-ns2-sata0 {
marvell,pins = "mpp21";
marvell,function = "sata0";
};
pmx_ns2_sata1: pmx-ns2-sata1 {
marvell,pins = "mpp20";
marvell,function = "sata1";
};
};
serial@12000 {
clock-frequency = <166666667>;
status = "okay";
+2
View File
@@ -36,6 +36,7 @@
reg = <0x10100 0x40>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <35>, <36>, <37>, <38>;
};
@@ -46,6 +47,7 @@
reg = <0x10140 0x40>;
ngpios = <18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <39>, <40>, <41>;
};
+2
View File
@@ -48,6 +48,8 @@
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
+4 -2
View File
@@ -60,19 +60,21 @@
};
uart0: uart@01c28000 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <1>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};
uart1: uart@01c28400 {
compatible = "ns8250";
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
status = "disabled";
};
@@ -45,7 +45,6 @@
reg = <1>;
};
/* A7s disabled till big.LITTLE patches are available...
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
@@ -63,7 +62,6 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
};
*/
};
memory@80000000 {
+2 -1
View File
@@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
@@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+2
View File
@@ -100,12 +100,14 @@ ENTRY(printch)
b 1b
ENDPROC(printch)
#ifdef CONFIG_MMU
ENTRY(debug_ll_addr)
addruart r2, r3, ip
str r2, [r0]
str r3, [r1]
mov pc, lr
ENDPROC(debug_ll_addr)
#endif
#else

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