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Merge tag 'drm-for-v4.8' of git://people.freedesktop.org/~airlied/linux
Merge drm updates from Dave Airlie:
"This is the main drm pull request for 4.8.
I'm down with a cold at the moment so hopefully this isn't in too bad
a state, I finished pulling stuff last week mostly (nouveau fixes just
went in today), so only this message should be influenced by illness.
Apologies to anyone who's major feature I missed :-)
Core:
Lockless GEM BO freeing
Non-blocking atomic work
Documentation changes (rst/sphinx)
Prep for new fencing changes
Simple display helpers
Master/auth changes
Register/unregister rework
Loads of trivial patches/fixes.
New stuff:
ARM Mali display driver (not the 3D chip)
sii902x RGB->HDMI bridge
Panel:
Support for new panels
Improved backlight support
Bridge:
Convert ADV7511 to bridge driver
ADV7533 support
TC358767 (DSI/DPI to eDP) encoder chip support
i915:
BXT support enabled by default
GVT-g infrastructure
GuC command submission and fixes
BXT workarounds
SKL/BKL workarounds
Demidlayering device registration
Thundering herd fixes
Missing pci ids
Atomic updates
amdgpu/radeon:
ATPX improvements for better dGPU power control on PX systems
New power features for CZ/BR/ST
Pipelined BO moves and evictions in TTM
GPU scheduler improvements
GPU reset improvements
Overclocking on dGPUs with amdgpu
Polaris powermanagement enabled
nouveau:
GK20A/GM20B volt and clock improvements.
Initial support for GP100/GP104 GPUs, GP104 will not yet support
acceleration due to NVIDIA having not released firmware for them as of yet.
exynos:
Exynos5433 SoC with IOMMU support.
vc4:
Shader validation for branching
imx-drm:
Atomic mode setting conversion
Reworked DMFC FIFO allocation
External bridge support
analogix-dp:
RK3399 eDP support
Lots of fixes.
rockchip:
Lots of small fixes.
msm:
DT bindings cleanups
Shrinker and madvise support
ASoC HDMI codec support
tegra:
Host1x driver cleanups
SOR reworking for DP support
Runtime PM support
omapdrm:
PLL enhancements
Header refactoring
Gamma table support
arcgpu:
Simulator support
virtio-gpu:
Atomic modesetting fixes.
rcar-du:
Misc fixes.
mediatek:
MT8173 HDMI support
sti:
ASOC HDMI codec support
Minor fixes
fsl-dcu:
Suspend/resume support
Bridge support
amdkfd:
Minor fixes.
etnaviv:
Enable GPU clock gating
hisilicon:
Vblank and other fixes"
* tag 'drm-for-v4.8' of git://people.freedesktop.org/~airlied/linux: (1575 commits)
drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup
drm/nouveau/acpi: fix lockup with PCIe runtime PM
drm/nouveau/acpi: check for function 0x1B before using it
drm/nouveau/acpi: return supported DSM functions
drm/nouveau/acpi: ensure matching ACPI handle and supported functions
drm/nouveau/fbcon: fix font width not divisible by 8
drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events
drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce
drm/amdgpu: add query device id and revision id into system info entry at CGS
drm/amdgpu: add new definition in bif header
drm/amd/powerplay: rename smum header guards
drm/amdgpu: enable UVD context buffer for older HW
drm/amdgpu: fix default UVD context size
drm/amdgpu: fix incorrect type of info_id
drm/amdgpu: make amdgpu_cgs_call_acpi_method as static
drm/amdgpu: comment out unused defaults_staturn_pro static const structure to fix the build
drm/amdgpu: enable UVD VM only on polaris
drm/amdgpu: increase timeout of IB test
drm/amdgpu: add destroy session when generate VCE destroy msg.
drm/amd: fix deadlock of job_list_lock V2
...
This commit is contained in:
Linus Torvalds
@@ -16,7 +16,7 @@ DOCBOOKS := z8530book.xml device-drivers.xml \
|
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genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \
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80211.xml debugobjects.xml sh.xml regulator.xml \
|
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alsa-driver-api.xml writing-an-alsa-driver.xml \
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tracepoint.xml gpu.xml media_api.xml w1.xml \
|
||||
tracepoint.xml media_api.xml w1.xml \
|
||||
writing_musb_glue_layer.xml crypto-API.xml iio.xml
|
||||
|
||||
include Documentation/DocBook/media/Makefile
|
||||
|
||||
@@ -161,6 +161,10 @@ X!Edrivers/base/interface.c
|
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!Iinclude/linux/fence.h
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!Edrivers/dma-buf/seqno-fence.c
|
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!Iinclude/linux/seqno-fence.h
|
||||
!Edrivers/dma-buf/fence-array.c
|
||||
!Iinclude/linux/fence-array.h
|
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!Edrivers/dma-buf/reservation.c
|
||||
!Iinclude/linux/reservation.h
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!Edrivers/dma-buf/sync_file.c
|
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!Iinclude/linux/sync_file.h
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</sect2>
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,65 @@
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ARM Mali-DP
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The following bindings apply to a family of Display Processors sold as
|
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licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
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DP650 processors that offer multiple composition layers, support for
|
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rotation and scaling output.
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Required properties:
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- compatible: should be one of
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"arm,mali-dp500"
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"arm,mali-dp550"
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"arm,mali-dp650"
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depending on the particular implementation present in the hardware
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- reg: Physical base address and size of the block of registers used by
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the processor.
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- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
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interrupt client nodes.
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- interrupt-names: name of the engine inside the processor that will
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use the corresponding interrupt. Should be one of "DE" or "SE".
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: A list of clock names. It should contain:
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- "pclk": for the APB interface clock
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- "aclk": for the AXI interface clock
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- "mclk": for the main processor clock
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- "pxlclk": for the pixel clock feeding the output PLL of the processor.
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- arm,malidp-output-port-lines: Array of u8 values describing the number
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of output lines per channel (R, G and B).
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Required sub-nodes:
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- port: The Mali DP connection to an encoder input port. The connection
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is modelled using the OF graph bindings specified in
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Documentation/devicetree/bindings/graph.txt
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Optional properties:
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- memory-region: phandle to a node describing memory (see
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
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to be used for the framebuffer; if not present, the framebuffer may
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be located anywhere in memory.
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Example:
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/ {
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...
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dp0: malidp@6f200000 {
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compatible = "arm,mali-dp650";
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reg = <0 0x6f200000 0 0x20000>;
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memory-region = <&display_reserved>;
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interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 168 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "DE", "SE";
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clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
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clock-names = "pxlclk", "mclk", "aclk", "pclk";
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arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
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port {
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dp0_output: endpoint {
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remote-endpoint = <&tda998x_2_input>;
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};
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};
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};
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|
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...
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};
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@@ -1,13 +1,19 @@
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Analog Device ADV7511(W)/13 HDMI Encoders
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Analog Device ADV7511(W)/13/33 HDMI Encoders
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-----------------------------------------
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The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters
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The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
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compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
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S/PDIF, CEC and HDCP.
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S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
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the others support RGB interface.
|
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|
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Required properties:
|
||||
|
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- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513"
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- compatible: Should be one of:
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"adi,adv7511"
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"adi,adv7511w"
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"adi,adv7513"
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"adi,adv7533"
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- reg: I2C slave address
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The ADV7511 supports a large number of input data formats that differ by their
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@@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and
|
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- adi,input-justification: The input bit justification ("left", "evenly",
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"right").
|
||||
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||||
The following properties are required for ADV7533:
|
||||
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- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
|
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be one of 1, 2, 3 or 4.
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||||
|
||||
Optional properties:
|
||||
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||||
- interrupts: Specifier for the ADV7511 interrupt
|
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@@ -42,13 +53,18 @@ Optional properties:
|
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- adi,embedded-sync: The input uses synchronization signals embedded in the
|
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data stream (similar to BT.656). Defaults to separate H/V synchronization
|
||||
signals.
|
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- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
|
||||
generator. The chip will rely on the sync signals in the DSI data lanes,
|
||||
rather than generate its own timings for HDMI output.
|
||||
|
||||
Required nodes:
|
||||
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||||
The ADV7511 has two video ports. Their connections are modelled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
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- Video port 0 for the RGB or YUV input
|
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- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
|
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remote endpoint phandle should be a reference to a valid mipi_dsi_host device
|
||||
node.
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- Video port 1 for the HDMI output
|
||||
|
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|
||||
|
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@@ -5,6 +5,7 @@ Required properties for dp-controller:
|
||||
platform specific such as:
|
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* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
* "rockchip,rk3399-edp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
sii902x HDMI bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "sil,sii9022"
|
||||
- reg: i2c address of the bridge
|
||||
|
||||
Optional properties:
|
||||
- interrupts-extended or interrupt-parent + interrupts: describe
|
||||
the interrupt line used to inform the host about hotplug events.
|
||||
- reset-gpios: OF device-tree gpio specification for RST_N pin.
|
||||
|
||||
Optional subnodes:
|
||||
- video input: this subnode can contain a video input port node
|
||||
to connect the bridge to a display controller output (See this
|
||||
documentation [1]).
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
hdmi-bridge@39 {
|
||||
compatible = "sil,sii9022";
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||||
reg = <0x39>;
|
||||
reset-gpios = <&pioA 1 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
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||||
bridge_in: endpoint {
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||||
remote-endpoint = <&dc_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
Toshiba TC358767 eDP bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "toshiba,tc358767"
|
||||
- reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
|
||||
- clock-names: should be "ref"
|
||||
- clocks: OF device-tree clock specification for refclk input. The reference
|
||||
clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
|
||||
|
||||
Optional properties:
|
||||
- shutdown-gpios: OF device-tree gpio specification for SD pin
|
||||
(active high shutdown input)
|
||||
- reset-gpios: OF device-tree gpio specification for RSTX pin
|
||||
(active low system reset)
|
||||
- ports: the ports node can contain video interface port nodes to connect
|
||||
to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
|
||||
- port@0: DSI input port
|
||||
- port@1: DPI input port
|
||||
- port@2: eDP/DP output port
|
||||
|
||||
[1]: Documentation/devicetree/bindings/graph.txt
|
||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
edp-bridge@68 {
|
||||
compatible = "toshiba,tc358767";
|
||||
reg = <0x68>;
|
||||
shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
|
||||
clock-names = "ref";
|
||||
clocks = <&edp_refclk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -8,6 +8,7 @@ Required properties:
|
||||
Optional properties:
|
||||
- label: a symbolic name for the connector
|
||||
- hpd-gpios: HPD GPIO number
|
||||
- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
|
||||
|
||||
Required nodes:
|
||||
- Video port for HDMI input
|
||||
|
||||
@@ -12,7 +12,7 @@ Required properties:
|
||||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
- port Video port for the panel output
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
@@ -24,6 +24,11 @@ dcu: dcu@2ce0000 {
|
||||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
|
||||
port {
|
||||
dcu_out: endpoint {
|
||||
remote-endpoint = <&panel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,148 @@
|
||||
Mediatek HDMI Encoder
|
||||
=====================
|
||||
|
||||
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
|
||||
its parallel input.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi".
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
|
||||
- phys: phandle link to the HDMI PHY node.
|
||||
See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
|
||||
- phy-names: must contain "hdmi"
|
||||
- mediatek,syscon-hdmi: phandle link and register offset to the system
|
||||
configuration registers. For mt8173 this must be offset 0x900 into the
|
||||
MMSYS_CONFIG region: <&mmsys 0x900>.
|
||||
- ports: A node containing input and output port nodes with endpoint
|
||||
definitions as documented in Documentation/devicetree/bindings/graph.txt.
|
||||
- port@0: The input port in the ports node should be connected to a DPI output
|
||||
port.
|
||||
- port@1: The output port in the ports node should be connected to the input
|
||||
port of a connector node that contains a ddc-i2c-bus property, or to the
|
||||
input port of an attached bridge chip, such as a SlimPort transmitter.
|
||||
|
||||
HDMI CEC
|
||||
========
|
||||
|
||||
The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-cec"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clock
|
||||
|
||||
HDMI DDC
|
||||
========
|
||||
|
||||
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
|
||||
The Mediatek's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: device clock
|
||||
- clock-names: Should be "ddc-i2c".
|
||||
|
||||
HDMI PHY
|
||||
========
|
||||
|
||||
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
|
||||
output and drives the HDMI pads.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-hdmi-phy"
|
||||
- reg: Physical base address and length of the module's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-names: must contain "pll_ref"
|
||||
- clock-output-names: must be "hdmitx_dig_cts" on mt8173
|
||||
- #phy-cells: must be <0>
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
|
||||
- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
|
||||
|
||||
Example:
|
||||
|
||||
cec: cec@10013000 {
|
||||
compatible = "mediatek,mt8173-cec";
|
||||
reg = <0 0x10013000 0 0xbc>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
};
|
||||
|
||||
hdmi_phy: hdmi-phy@10209100 {
|
||||
compatible = "mediatek,mt8173-hdmi-phy";
|
||||
reg = <0 0x10209100 0 0x24>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
||||
clock-names = "pll_ref";
|
||||
clock-output-names = "hdmitx_dig_cts";
|
||||
mediatek,ibias = <0xa>;
|
||||
mediatek,ibias_up = <0x1c>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hdmi_ddc0: i2c@11012000 {
|
||||
compatible = "mediatek,mt8173-hdmi-ddc";
|
||||
reg = <0 0x11012000 0 0x1c>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_I2C5>;
|
||||
clock-names = "ddc-i2c";
|
||||
};
|
||||
|
||||
hdmi0: hdmi@14025000 {
|
||||
compatible = "mediatek,mt8173-hdmi";
|
||||
reg = <0 0x14025000 0 0x400>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLLCK>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pin>;
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
|
||||
assigned-clock-parents = <&hdmi_phy>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
ddc-i2c-bus = <&hdmiddc0>;
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -11,8 +11,7 @@ Required properties:
|
||||
be 0 or 1, since we have 2 DSI controllers at most for now.
|
||||
- interrupts: The interrupt signal from the DSI block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks.
|
||||
- clock-names: the following clocks are required:
|
||||
* "mdp_core_clk"
|
||||
* "iface_clk"
|
||||
@@ -23,16 +22,21 @@ Required properties:
|
||||
* "core_clk"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src_clk"
|
||||
- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
|
||||
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||
by a DSI PHY block. See [1] for details on clock bindings.
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- qcom,dsi-phy: phandle to DSI PHY device node
|
||||
- phys: phandle to DSI PHY device node
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||
an endpoint subnode as defined in [2] and [3].
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
See files in Documentation/devicetree/bindings/display/panel/ for each supported
|
||||
panel.
|
||||
See files in [4] for each supported panel.
|
||||
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||
driving a panel which needs 2 DSI links.
|
||||
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||
@@ -44,34 +48,38 @@ Optional properties:
|
||||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- port: DSI controller output port, containing one endpoint subnode.
|
||||
- ports: contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: set to phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
|
||||
to the physical lanes on the given platform. The value contained in
|
||||
index n describes what logical data lane is mapped to the physical data
|
||||
lane n (DATAn, where n lies between 0 and 3).
|
||||
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||
device graph info.
|
||||
|
||||
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||
to the logical lanes on the given platform. The value contained in
|
||||
index n describes what physical lane is mapped to the logical lane n
|
||||
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||
[3] for more info on the data-lanes property.
|
||||
|
||||
For example:
|
||||
|
||||
qcom,data-lane-map = <3 0 1 2>;
|
||||
data-lanes = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA3 is mapped to
|
||||
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
|
||||
to phys DATA2 and logic DATA2 to phys DATA3.
|
||||
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
|
||||
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
|
||||
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
|
||||
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
|
||||
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
|
||||
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
|
||||
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
|
||||
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
|
||||
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
|
||||
<0 1 2 3>
|
||||
<1 2 3 0>
|
||||
<2 3 0 1>
|
||||
<3 0 1 2>
|
||||
<0 3 2 1>
|
||||
<1 0 3 2>
|
||||
<2 1 0 3>
|
||||
<3 2 1 0>
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
@@ -86,11 +94,12 @@ Required properties:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
|
||||
be 0 or 1, since we have 2 DSI PHYs at most for now.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface_clk"
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
@@ -99,11 +108,16 @@ Optional properties:
|
||||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||
regulator is wanted.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
Example:
|
||||
mdss_dsi0: qcom,mdss_dsi@fd922800 {
|
||||
dsi0: dsi@fd922800 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
qcom,dsi-host-index = <0>;
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupt-parent = <&mdp>;
|
||||
interrupts = <4 0>;
|
||||
reg-names = "dsi_ctrl";
|
||||
reg = <0xfd922800 0x200>;
|
||||
@@ -124,19 +138,48 @@ Example:
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>;
|
||||
|
||||
assigned-clocks =
|
||||
<&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents =
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>;
|
||||
|
||||
vdda-supply = <&pma8084_l2>;
|
||||
vdd-supply = <&pma8084_l22>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0>;
|
||||
phys = <&dsi_phy0>;
|
||||
phy-names ="dsi-phy";
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
qcom,sync-dual-dsi;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mdss_dsi_active>;
|
||||
pinctrl-1 = <&mdss_dsi_suspend>;
|
||||
pinctrl-0 = <&dsi_active>;
|
||||
pinctrl-1 = <&dsi_suspend>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "sharp,lq101r1sx01";
|
||||
@@ -152,16 +195,9 @@ Example:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
@@ -173,6 +209,7 @@ Example:
|
||||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface_clk";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
|
||||
@@ -1,59 +0,0 @@
|
||||
Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
* "qcom,mdp5" - mdp5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
For MDP4:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mdp_clk"
|
||||
For MDP5:
|
||||
* "bus_clk"
|
||||
* "iface_clk"
|
||||
* "core_clk_src"
|
||||
* "core_clk"
|
||||
* "lut_clk" (some MDP5 versions may not need this)
|
||||
* "vsync_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
gpus = <&gpu>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"src_clk",
|
||||
"hdmi_clk",
|
||||
"mdp_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_SRC>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc TV_SRC>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,112 @@
|
||||
Qualcomm adreno/snapdragon MDP4 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the MDP4 display controller found in
|
||||
SoCs like MSM8960, APQ8064 and MSM8660.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "lut_clk"
|
||||
* "hdmi_clk"
|
||||
* "tv_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The output port mappings are:
|
||||
Port 0 -> LCDC/LVDS
|
||||
Port 1 -> DSI1 Cmd/Video
|
||||
Port 2 -> DSI2 Cmd/Video
|
||||
Port 3 -> DTV
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: hdmi@4a00000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&mdp_dtv_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
mdp: mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"hdmi_clk",
|
||||
"tv_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_CLK>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp_lvds_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
mdp_dsi2_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
mdp_dtv_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,160 @@
|
||||
Qualcomm adreno/snapdragon MDP5 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
|
||||
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss" - MDSS
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdss_phys"
|
||||
* "vbif_phys"
|
||||
- interrupts: The interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "vsync_clk"
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
MDP5:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp5" - MDP5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdp_phys"
|
||||
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
|
||||
- interrupt-parent: phandle to the MDSS block
|
||||
through MDP block
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
- * "bus_clk"
|
||||
- * "iface_clk"
|
||||
- * "core_clk"
|
||||
- * "vsync_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The availability of output ports can vary across SoC revisions:
|
||||
|
||||
For MSM8974 and APQ8084:
|
||||
Port 0 -> MDP_INTF0 (eDP)
|
||||
Port 1 -> MDP_INTF1 (DSI1)
|
||||
Port 2 -> MDP_INTF2 (DSI2)
|
||||
Port 3 -> MDP_INTF3 (HDMI)
|
||||
|
||||
For MSM8916:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
|
||||
For MSM8994 and MSM8996:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
Port 1 -> MDP_INTF2 (DSI2)
|
||||
Port 2 -> MDP_INTF3 (HDMI)
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdss: mdss@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"vsync_clk"
|
||||
|
||||
interrupts = <0 72 0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp: mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0 0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"core_clk",
|
||||
"vsync_clk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@1a98000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@1a98300 {
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp079qx1-sp0v"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
LG 9.7" (2048x1536 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp097qx1-spa1"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -7,6 +7,8 @@ Required properties:
|
||||
Optional properties:
|
||||
- label: a symbolic name for the panel
|
||||
- enable-gpios: panel enable gpio
|
||||
- reset-gpios: GPIO to control the RESET pin
|
||||
- vcc-supply: phandle of regulator that will be used to enable power to the display
|
||||
|
||||
Required nodes:
|
||||
- "panel-timing" containing video timings
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
Samsung 12.2" (2560x1600 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "samsung,lsn122dl01-c01"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,7 @@
|
||||
Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq101k1ly04"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user