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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: drivers/net/ethernet/rocker/rocker.c The rocker commit was two overlapping changes, one to rename the ->vport member to ->pport, and another making the bitmask expression use '1ULL' instead of plain '1'. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -35,3 +35,11 @@ Contact: Corentin Chary <corentin.chary@gmail.com>
|
||||
Description: Use your USB ports to charge devices, even
|
||||
when your laptop is powered off.
|
||||
1 means enabled, 0 means disabled.
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||||
|
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What: /sys/devices/platform/samsung/lid_handling
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Date: December 11, 2014
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||||
KernelVersion: 3.19
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||||
Contact: Julijonas Kikutis <julijonas.kikutis@gmail.com>
|
||||
Description: Some Samsung laptops handle lid closing quicker and
|
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only handle lid opening with this mode enabled.
|
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1 means enabled, 0 means disabled.
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|
||||
@@ -0,0 +1,114 @@
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_backlight_mode
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Date: June 8, 2014
|
||||
KernelVersion: 3.15
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||||
Contact: Azael Avalos <coproscefalo@gmail.com>
|
||||
Description: This file controls the keyboard backlight operation mode, valid
|
||||
values are:
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||||
* 0x1 -> FN-Z
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* 0x2 -> AUTO (also called TIMER)
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* 0x8 -> ON
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* 0x10 -> OFF
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Note that the kernel 3.16 onwards this file accepts all listed
|
||||
parameters, kernel 3.15 only accepts the first two (FN-Z and
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||||
AUTO).
|
||||
Users: KToshiba
|
||||
|
||||
What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_backlight_timeout
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||||
Date: June 8, 2014
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||||
KernelVersion: 3.15
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||||
Contact: Azael Avalos <coproscefalo@gmail.com>
|
||||
Description: This file controls the timeout of the keyboard backlight
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whenever the operation mode is set to AUTO (or TIMER),
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valid values range from 0-60.
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||||
Note that the kernel 3.15 only had support for the first
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||||
keyboard type, the kernel 3.16 added support for the second
|
||||
type and the range accepted for type 2 is 1-60.
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||||
See the entry named "kbd_type"
|
||||
Users: KToshiba
|
||||
|
||||
What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/position
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Date: June 8, 2014
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KernelVersion: 3.15
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file shows the absolute position of the built-in
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accelereometer.
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/touchpad
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Date: June 8, 2014
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KernelVersion: 3.15
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Contact: Azael Avalos <coproscefalo@gmail.com>
|
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Description: This files controls the status of the touchpad and pointing
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stick (if available), valid values are:
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* 0 -> OFF
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* 1 -> ON
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Users: KToshiba
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/available_kbd_modes
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Date: August 3, 2014
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KernelVersion: 3.16
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file shows the supported keyboard backlight modes
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the system supports, which can be:
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* 0x1 -> FN-Z
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* 0x2 -> AUTO (also called TIMER)
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* 0x8 -> ON
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* 0x10 -> OFF
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Note that not all keyboard types support the listed modes.
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See the entry named "available_kbd_modes"
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Users: KToshiba
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_type
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Date: August 3, 2014
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KernelVersion: 3.16
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file shows the current keyboard backlight type,
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which can be:
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* 1 -> Type 1, supporting modes FN-Z and AUTO
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* 2 -> Type 2, supporting modes TIMER, ON and OFF
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Users: KToshiba
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/version
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Date: February, 2015
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KernelVersion: 3.20
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file shows the current version of the driver
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/fan
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Date: February, 2015
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KernelVersion: 3.20
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file controls the state of the internal fan, valid
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values are:
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* 0 -> OFF
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* 1 -> ON
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/kbd_function_keys
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Date: February, 2015
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KernelVersion: 3.20
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file controls the Special Functions (hotkeys) operation
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mode, valid values are:
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* 0 -> Normal Operation
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* 1 -> Special Functions
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In the "Normal Operation" mode, the F{1-12} keys are as usual
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and the hotkeys are accessed via FN-F{1-12}.
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In the "Special Functions" mode, the F{1-12} keys trigger the
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hotkey and the F{1-12} keys are accessed via FN-F{1-12}.
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/panel_power_on
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Date: February, 2015
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KernelVersion: 3.20
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file controls whether the laptop should turn ON whenever
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the LID is opened, valid values are:
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* 0 -> Disabled
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* 1 -> Enabled
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What: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/TOS{1900,620{0,7,8}}:00/usb_three
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Date: February, 2015
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KernelVersion: 3.20
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Contact: Azael Avalos <coproscefalo@gmail.com>
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Description: This file controls whether the USB 3 functionality, valid
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values are:
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* 0 -> Disabled (Acts as a regular USB 2)
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* 1 -> Enabled (Full USB 3 functionality)
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@@ -197,6 +197,7 @@
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may be configured as a kernel built-in or a kernel loadable module.
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You can only make use of <constant>kgdbwait</constant> and early
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debugging if you build kgdboc into the kernel as a built-in.
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</para>
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<para>Optionally you can elect to activate kms (Kernel Mode
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Setting) integration. When you use kms with kgdboc and you have a
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video driver that has atomic mode setting hooks, it is possible to
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@@ -206,7 +207,6 @@
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crashes or doing analysis of memory with kdb while allowing the
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full graphics console applications to run.
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</para>
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</para>
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<sect2 id="kgdbocArgs">
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<title>kgdboc arguments</title>
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<para>Usage: <constant>kgdboc=[kms][[,]kbd][[,]serial_device][,baud]</constant></para>
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@@ -284,7 +284,6 @@
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</listitem>
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</orderedlist>
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</para>
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</sect3>
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<para>NOTE: Kgdboc does not support interrupting the target via the
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gdb remote protocol. You must manually send a sysrq-g unless you
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have a proxy that splits console output to a terminal program.
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@@ -305,6 +304,7 @@
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as well as on the initial connect, or to use a debugger proxy that
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allows an unmodified gdb to do the debugging.
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||||
</para>
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||||
</sect3>
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</sect2>
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</sect1>
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<sect1 id="kgdbwait">
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@@ -350,12 +350,12 @@
|
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</para>
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||||
</listitem>
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</orderedlist>
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</para>
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<para>IMPORTANT NOTE: You cannot use kgdboc + kgdbcon on a tty that is an
|
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active system console. An example of incorrect usage is <constant>console=ttyS0,115200 kgdboc=ttyS0 kgdbcon</constant>
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</para>
|
||||
<para>It is possible to use this option with kgdboc on a tty that is not a system console.
|
||||
</para>
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</para>
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||||
</sect1>
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<sect1 id="kgdbreboot">
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<title>Run time parameter: kgdbreboot</title>
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@@ -404,8 +404,8 @@ supported and the interface files "release_agent" and
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be understood as an underflow into the highest possible value, -2 or
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-10M etc. do not work, so it's not consistent.
|
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memory.low, memory.high, and memory.max will use the string
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"infinity" to indicate and set the highest possible value.
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memory.low, memory.high, and memory.max will use the string "max" to
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indicate and set the highest possible value.
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5. Planned Changes
|
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@@ -73,6 +73,8 @@ the operations defined in clk.h:
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unsigned long *parent_rate);
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long (*determine_rate)(struct clk_hw *hw,
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unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
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int (*set_parent)(struct clk_hw *hw, u8 index);
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@@ -51,7 +51,7 @@ Parameters: <cipher> <key> <iv_offset> <device path> \
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Otherwise #opt_params is the number of following arguments.
|
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|
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Example of optional parameters section:
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1 allow_discards
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3 allow_discards same_cpu_crypt submit_from_crypt_cpus
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||||
allow_discards
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Block discard requests (a.k.a. TRIM) are passed through the crypt device.
|
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@@ -63,6 +63,19 @@ allow_discards
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used space etc.) if the discarded blocks can be located easily on the
|
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device later.
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same_cpu_crypt
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Perform encryption using the same cpu that IO was submitted on.
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The default is to use an unbound workqueue so that encryption work
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is automatically balanced between available CPUs.
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submit_from_crypt_cpus
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Disable offloading writes to a separate thread after encryption.
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There are some situations where offloading write bios from the
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encryption threads to a single thread degrades performance
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significantly. The default is to offload write bios to the same
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thread because it benefits CFQ to have writes submitted using the
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same context.
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Example scripts
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||||
===============
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LUKS (Linux Unified Key Setup) is now the preferred way to set up disk
|
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@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
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- "samsung,exynos7-clock-peris"
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- "samsung,exynos7-clock-fsys0"
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- "samsung,exynos7-clock-fsys1"
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- "samsung,exynos7-clock-mscl"
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- "samsung,exynos7-clock-aud"
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- reg: physical base address of the controller and the length of
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memory mapped region.
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@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
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- dout_sclk_bus1_pll
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- dout_sclk_cc_pll
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- dout_sclk_mfc_pll
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- dout_sclk_aud_pll
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Input clocks for top1 clock controller:
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- fin_pll
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@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
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- sclk_uart1
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- sclk_uart2
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- sclk_uart3
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- sclk_spi0
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- sclk_spi1
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- sclk_spi2
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- sclk_spi3
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- sclk_spi4
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- sclk_i2s1
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- sclk_pcm1
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- sclk_spdif
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Input clocks for peris clock controller:
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- fin_pll
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@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
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- dout_aclk_fsys1_200
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- dout_sclk_mmc0
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- dout_sclk_mmc1
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||||
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Input clocks for aud clock controller:
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- fin_pll
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- fout_aud_pll
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@@ -1,4 +1,4 @@
|
||||
NVIDIA Tegra124 Clock And Reset Controller
|
||||
NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
||||
for muxing and gating Tegra's clocks, and setting their rates.
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "nvidia,tegra124-car"
|
||||
- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
|
||||
- reg : Should contain CAR registers location and length
|
||||
- clocks : Should contain phandle and clock specifiers for two clocks:
|
||||
the 32 KHz "32k_in", and the board-specific oscillator "osc".
|
||||
- #clock-cells : Should be 1.
|
||||
In clock consumers, this cell represents the clock ID exposed by the
|
||||
CAR. The assignments may be found in header file
|
||||
<dt-bindings/clock/tegra124-car.h>.
|
||||
CAR. The assignments may be found in the header files
|
||||
<dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
|
||||
to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
|
||||
(for Tegra124-specific clocks).
|
||||
- #reset-cells : Should be 1.
|
||||
In clock consumers, this cell represents the bit number in the CAR's
|
||||
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
Qualcomm LPASS Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,lcc-msm8960"
|
||||
"qcom,lcc-apq8064"
|
||||
"qcom,lcc-ipq8064"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
clock-controller@28000000 {
|
||||
compatible = "qcom,lcc-ipq8064";
|
||||
reg = <0x28000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -1,6 +1,6 @@
|
||||
* Clock Block on Freescale CoreNet Platforms
|
||||
* Clock Block on Freescale QorIQ Platforms
|
||||
|
||||
Freescale CoreNet chips take primary clocking input from the external
|
||||
Freescale qoriq chips take primary clocking input from the external
|
||||
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
|
||||
multiple phase locked loops (PLL) to create a variety of frequencies
|
||||
which can then be passed to a variety of internal logic, including
|
||||
@@ -29,6 +29,7 @@ Required properties:
|
||||
* "fsl,t4240-clockgen"
|
||||
* "fsl,b4420-clockgen"
|
||||
* "fsl,b4860-clockgen"
|
||||
* "fsl,ls1021a-clockgen"
|
||||
Chassis clock strings include:
|
||||
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
|
||||
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
|
||||
|
||||
@@ -11,6 +11,7 @@ Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
|
||||
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
* Renesas R8A73A4 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
|
||||
and several fixed ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a73a4-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clocks ("extal1" and "extal2")
|
||||
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
|
||||
"m1", "m2", "zx", "zs", and "hp".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a73a4-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll2s", "pll2h", "z", "z2",
|
||||
"i", "m3", "b", "m1", "m2",
|
||||
"zx", "zs", "hp";
|
||||
};
|
||||
@@ -8,15 +8,18 @@ Required Properties:
|
||||
- compatible: Must be one of
|
||||
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||||
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||||
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
|
||||
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||||
- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- clocks: References to the parent clocks: first to the EXTAL clock, second
|
||||
to the USB_EXTAL clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
|
||||
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
|
||||
"adsp"
|
||||
|
||||
|
||||
Example
|
||||
@@ -26,8 +29,9 @@ Example
|
||||
compatible = "renesas,r8a7790-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0, "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "sd1", "z";
|
||||
"lb", "qspi", "sdh", "sd0", "sd1", "z",
|
||||
"rcan", "adsp";
|
||||
};
|
||||
|
||||
@@ -26,7 +26,7 @@ Required properties:
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
|
||||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
|
||||
@@ -55,9 +55,11 @@ Required properties:
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
|
||||
"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
|
||||
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
|
||||
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
|
||||
"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
|
||||
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
@@ -73,7 +75,9 @@ Required properties for all clocks:
|
||||
- #clock-cells : from common clock binding; shall be set to 0 except for
|
||||
the following compatibles where it shall be set to 1:
|
||||
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
|
||||
"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
|
||||
"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
|
||||
"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
|
||||
"allwinner,*-mmc-config-clk"
|
||||
- clock-output-names : shall be the corresponding names of the outputs.
|
||||
If the clock module only has one output, the name shall be the
|
||||
module name.
|
||||
@@ -81,6 +85,10 @@ Required properties for all clocks:
|
||||
And "allwinner,*-usb-clk" clocks also require:
|
||||
- reset-cells : shall be set to 1
|
||||
|
||||
The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
|
||||
- #reset-cells : shall be set to 1
|
||||
- resets : shall be the reset control phandle for the mmc block.
|
||||
|
||||
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
|
||||
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
|
||||
|
||||
@@ -95,6 +103,14 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
|
||||
is the normal PLL6 output, or "pll6". The second output is rate doubled
|
||||
PLL6, or "pll6x2".
|
||||
|
||||
The "allwinner,*-mmc-clk" clocks have three different outputs: the
|
||||
main clock, with the ID 0, and the output and sample clocks, with the
|
||||
IDs 1 and 2, respectively.
|
||||
|
||||
The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
|
||||
per mmc controller. The number of outputs is determined by the size of
|
||||
the address block, which is related to the overall mmc block.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: clk@01c20050 {
|
||||
@@ -138,11 +154,11 @@ cpu: cpu@01c20054 {
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
|
||||
};
|
||||
|
||||
mii_phy_tx_clk: clk@2 {
|
||||
@@ -170,3 +186,16 @@ gmac_clk: clk@01c20164 {
|
||||
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
||||
clock-output-names = "gmac";
|
||||
};
|
||||
|
||||
mmc_config_clk: clk@01c13000 {
|
||||
compatible = "allwinner,sun9i-a80-mmc-config-clk";
|
||||
reg = <0x01c13000 0x10>;
|
||||
clocks = <&ahb0_gates 8>;
|
||||
clock-names = "ahb";
|
||||
resets = <&ahb0_resets 8>;
|
||||
reset-names = "ahb";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clock-output-names = "mmc0_config", "mmc1_config",
|
||||
"mmc2_config", "mmc3_config";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
|
||||
synthesizer/multiplier/divider.
|
||||
|
||||
Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
|
||||
|
||||
I2C device node required properties:
|
||||
- compatible: shall be "ti,cdce706".
|
||||
- reg: i2c device address, shall be in range [0x68...0x6b].
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock
|
||||
handles, shall be reference clock(s) connected to CLK_IN0
|
||||
and CLK_IN1 pins.
|
||||
- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
|
||||
in case of crystal oscillator or differential signal input
|
||||
configuration. Use clk_in0 and clk_in1 in case of independent
|
||||
single-ended LVCMOS inputs configuration.
|
||||
|
||||
Example:
|
||||
|
||||
clocks {
|
||||
clk54: clk54 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
i2c0: i2c-master@0d090000 {
|
||||
...
|
||||
cdce706: clock-synth@69 {
|
||||
compatible = "ti,cdce706";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x69>;
|
||||
clocks = <&clk54>;
|
||||
clock-names = "clk_in0";
|
||||
};
|
||||
};
|
||||
...
|
||||
simple-audio-card,codec {
|
||||
...
|
||||
clocks = <&cdce706 4>;
|
||||
};
|
||||
@@ -0,0 +1,33 @@
|
||||
Binding for Texas Instruments FAPLL clock.
|
||||
|
||||
Binding status: Unstable - ABI compatibility may be broken in the future
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped FAPLL with usually two selectable input clocks
|
||||
(reference clock and bypass clock), and one or more child
|
||||
syntesizers.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dm816-fapll-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
||||
- reg : address and length of the register set for controlling the FAPLL.
|
||||
|
||||
Examples:
|
||||
main_fapll: main_fapll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm816-fapll-clock";
|
||||
reg = <0x400 0x40>;
|
||||
clocks = <&sys_clkin_ck &sys_clkin_ck>;
|
||||
clock-indices = <1>, <2>, <3>, <4>, <5>,
|
||||
<6>, <7>;
|
||||
clock-output-names = "main_pll_clk1",
|
||||
"main_pll_clk2",
|
||||
"main_pll_clk3",
|
||||
"main_pll_clk4",
|
||||
"main_pll_clk5",
|
||||
"main_pll_clk6",
|
||||
"main_pll_clk7";
|
||||
};
|
||||
@@ -0,0 +1,57 @@
|
||||
* IMG Multi-threaded DMA Controller (MDC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-mdc-dma".
|
||||
- reg: Must contain the base address and length of the MDC registers.
|
||||
- interrupts: Must contain all the per-channel DMA interrupts.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- sys: MDC system interface clock.
|
||||
- img,cr-periph: Must contain a phandle to the peripheral control syscon
|
||||
node which contains the DMA request to channel mapping registers.
|
||||
- img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
|
||||
The maximum burst size is this value multiplied by the hardware-reported bus
|
||||
width.
|
||||
- #dma-cells: Must be 3:
|
||||
- The first cell is the peripheral's DMA request line.
|
||||
- The second cell is a bitmap specifying to which channels the DMA request
|
||||
line may be mapped (i.e. bit N set indicates channel N is usable).
|
||||
- The third cell is the thread ID to be used by the channel.
|
||||
|
||||
Optional properties:
|
||||
- dma-channels: Number of supported DMA channels, up to 32. If not specified
|
||||
the number reported by the hardware is used.
|
||||
|
||||
Example:
|
||||
|
||||
mdc: dma-controller@18143000 {
|
||||
compatible = "img,pistachio-mdc-dma";
|
||||
reg = <0x18143000 0x1000>;
|
||||
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&system_clk>;
|
||||
clock-names = "sys";
|
||||
|
||||
img,max-burst-multiplier = <16>;
|
||||
img,cr-periph = <&cr_periph>;
|
||||
|
||||
#dma-cells = <3>;
|
||||
};
|
||||
|
||||
spi@18100f00 {
|
||||
...
|
||||
dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
|
||||
dma-names = "tx", "rx";
|
||||
...
|
||||
};
|
||||
@@ -5,9 +5,6 @@ controller instances named DMAC capable of serving multiple clients. Channels
|
||||
can be dedicated to specific clients or shared between a large number of
|
||||
clients.
|
||||
|
||||
DMA clients are connected to the DMAC ports referenced by an 8-bit identifier
|
||||
called MID/RID.
|
||||
|
||||
Each DMA client is connected to one dedicated port of the DMAC, identified by
|
||||
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
|
||||
256 clients in total. When the number of hardware channels is lower than the
|
||||
|
||||
@@ -38,7 +38,7 @@ Example:
|
||||
chan_allocation_order = <1>;
|
||||
chan_priority = <1>;
|
||||
block_size = <0xfff>;
|
||||
data_width = <3 3 0 0>;
|
||||
data_width = <3 3>;
|
||||
};
|
||||
|
||||
DMA clients connected to the Designware DMA controller must use the format
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
Broadcom iProc I2C controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible:
|
||||
Must be "brcm,iproc-i2c"
|
||||
|
||||
- reg:
|
||||
Define the base and range of the I/O address space that contain the iProc
|
||||
I2C controller registers
|
||||
|
||||
- interrupts:
|
||||
Should contain the I2C interrupt
|
||||
|
||||
- clock-frequency:
|
||||
This is the I2C bus clock. Need to be either 100000 or 400000
|
||||
|
||||
- #address-cells:
|
||||
Always 1 (for I2C addresses)
|
||||
|
||||
- #size-cells:
|
||||
Always 0
|
||||
|
||||
Example:
|
||||
i2c0: i2c@18008000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x18008000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
codec: wm8750@1a {
|
||||
compatible = "wlf,wm8750";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user