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drm: zte: add VGA driver support
It adds VGA driver support, which needs to configure corresponding VOU interface in RGB_888 format, and thus the following changes are needed on zx_vou. - Rename the CSC block of Graphic Layer a bit to make it more specific, and add CSC of Channel to support RGB output. - Bypass Dither block for RGB output. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1491910226-7831-1-git-send-email-shawnguo@kernel.org
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Shawn Guo
@@ -3,6 +3,7 @@ zxdrm-y := \
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zx_hdmi.o \
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zx_plane.o \
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zx_tvenc.o \
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zx_vga.o \
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zx_vou.o
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obj-$(CONFIG_DRM_ZTE) += zxdrm.o
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@@ -233,6 +233,7 @@ static struct platform_driver *drivers[] = {
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&zx_crtc_driver,
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&zx_hdmi_driver,
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&zx_tvenc_driver,
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&zx_vga_driver,
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&zx_drm_platform_driver,
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};
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@@ -14,6 +14,7 @@
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extern struct platform_driver zx_crtc_driver;
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extern struct platform_driver zx_hdmi_driver;
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extern struct platform_driver zx_tvenc_driver;
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extern struct platform_driver zx_vga_driver;
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static inline u32 zx_readl(void __iomem *reg)
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{
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
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/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ZX_VGA_REGS_H__
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#define __ZX_VGA_REGS_H__
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#define VGA_CMD_CFG 0x04
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#define VGA_CMD_TRANS BIT(6)
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#define VGA_CMD_COMBO BIT(5)
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#define VGA_CMD_RW BIT(4)
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#define VGA_SUB_ADDR 0x0c
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#define VGA_DEVICE_ADDR 0x10
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#define VGA_CLK_DIV_FS 0x14
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#define VGA_RXF_CTRL 0x20
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#define VGA_RX_FIFO_CLEAR BIT(7)
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#define VGA_DATA 0x24
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#define VGA_I2C_STATUS 0x28
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#define VGA_DEVICE_DISCONNECTED BIT(7)
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#define VGA_DEVICE_CONNECTED BIT(6)
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#define VGA_CLEAR_IRQ BIT(4)
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#define VGA_TRANS_DONE BIT(0)
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#define VGA_RXF_STATUS 0x30
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#define VGA_RXF_COUNT_SHIFT 2
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#define VGA_RXF_COUNT_MASK GENMASK(7, 2)
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#define VGA_AUTO_DETECT_PARA 0x34
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#define VGA_AUTO_DETECT_SEL 0x38
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#define VGA_DETECT_SEL_HAS_DEVICE BIT(1)
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#define VGA_DETECT_SEL_NO_DEVICE BIT(0)
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#endif /* __ZX_VGA_REGS_H__ */
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@@ -23,6 +23,7 @@
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#include <drm/drm_plane_helper.h>
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#include <drm/drmP.h>
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#include "zx_common_regs.h"
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#include "zx_drm_drv.h"
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#include "zx_plane.h"
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#include "zx_vou.h"
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@@ -122,6 +123,8 @@ struct zx_crtc {
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struct drm_plane *primary;
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struct zx_vou_hw *vou;
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void __iomem *chnreg;
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void __iomem *chncsc;
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void __iomem *dither;
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const struct zx_crtc_regs *regs;
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const struct zx_crtc_bits *bits;
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enum vou_chn_type chn_type;
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@@ -204,6 +207,11 @@ static struct vou_inf vou_infs[] = {
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.clocks_en_bits = BIT(15),
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.clocks_sel_bits = BIT(11) | BIT(0),
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},
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[VOU_VGA] = {
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.data_sel = VOU_RGB_888,
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.clocks_en_bits = BIT(1),
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.clocks_sel_bits = BIT(10),
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},
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};
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static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
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@@ -227,9 +235,26 @@ void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
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struct zx_crtc *zcrtc = to_zx_crtc(crtc);
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struct zx_vou_hw *vou = zcrtc->vou;
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struct vou_inf *inf = &vou_infs[id];
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void __iomem *dither = zcrtc->dither;
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void __iomem *csc = zcrtc->chncsc;
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bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
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u32 data_sel_shift = id << 1;
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if (inf->data_sel != VOU_YUV444) {
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/* Enable channel CSC for RGB output */
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zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
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CSC_BT709_IMAGE_YCBCR2RGB << CSC_COV_MODE_SHIFT);
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zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
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CSC_WORK_ENABLE);
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/* Bypass Dither block for RGB output */
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zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
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DITHER_BYSPASS);
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} else {
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zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
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zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
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}
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/* Select data format */
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zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
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inf->data_sel << data_sel_shift);
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@@ -525,20 +550,24 @@ static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
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if (chn_type == VOU_CHN_MAIN) {
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zplane->layer = vou->osd + MAIN_GL_OFFSET;
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zplane->csc = vou->osd + MAIN_CSC_OFFSET;
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zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
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zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
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zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
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zplane->bits = &zx_gl_bits[0];
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zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
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zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
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zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
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zcrtc->regs = &main_crtc_regs;
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zcrtc->bits = &main_crtc_bits;
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} else {
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zplane->layer = vou->osd + AUX_GL_OFFSET;
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zplane->csc = vou->osd + AUX_CSC_OFFSET;
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zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
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zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
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zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
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zplane->bits = &zx_gl_bits[1];
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zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
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zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
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zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
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zcrtc->regs = &aux_crtc_regs;
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zcrtc->bits = &aux_crtc_bits;
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}
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@@ -13,13 +13,17 @@
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/* Sub-module offset */
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#define MAIN_GL_OFFSET 0x130
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#define MAIN_CSC_OFFSET 0x580
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#define MAIN_GL_CSC_OFFSET 0x580
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#define MAIN_CHN_CSC_OFFSET 0x6c0
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#define MAIN_HBSC_OFFSET 0x820
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#define MAIN_DITHER_OFFSET 0x960
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#define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
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#define AUX_GL_OFFSET 0x200
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#define AUX_CSC_OFFSET 0x5d0
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#define AUX_GL_CSC_OFFSET 0x5d0
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#define AUX_CHN_CSC_OFFSET 0x710
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#define AUX_HBSC_OFFSET 0x860
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#define AUX_DITHER_OFFSET 0x970
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#define AUX_RSZ_OFFSET 0x800
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#define OSD_VL0_OFFSET 0x040
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@@ -78,6 +82,10 @@
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#define CHN_INTERLACE_BUF_CTRL 0x24
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#define CHN_INTERLACE_EN BIT(2)
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/* Dither registers */
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#define OSD_DITHER_CTRL0 0x00
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#define DITHER_BYSPASS BIT(31)
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/* TIMING_CTRL registers */
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#define TIMING_TC_ENABLE 0x04
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#define AUX_TC_EN BIT(1)
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