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Staging: et1310: Fix the coding style

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UTF-8 for copyright symbols etc included. Typedefs and anything else which
would cause actual code changes skipped.

Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
2009-06-10 17:30:41 +01:00
committed by Greg Kroah-Hartman
parent 297f06cea6
commit 64f930361b
27 changed files with 2172 additions and 2230 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/staging/et131x/et1310_address_map.h
+1058 -1058
View File
File diff suppressed because it is too large Load Diff
drivers/staging/et131x/et1310_eeprom.c
+19 -27
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -74,9 +74,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -155,7 +155,7 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
uint8_t bData, uint32_t unEepromId,
uint32_t unAddressingMode)
{
struct pci_dev *pdev = pAdapter->pdev;
struct pci_dev *pdev = pAdapter->pdev;
int32_t nIndex;
int32_t nRetries;
int32_t nError = false;
@@ -226,23 +226,20 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* bits 1:0 are equal to 1 */
bStatus & LBCIF_STATUS_I2C_IDLE)
/* bits 1:0 are equal to 1 */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
return FAILURE;
}
/* Step 2: */
bControl = 0;
bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
if (unAddressingMode == DUAL_BYTE) {
if (unAddressingMode == DUAL_BYTE)
bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
}
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
bControl)) {
@@ -281,20 +278,19 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* I2C write complete */
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* I2C write complete */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
break;
}
/*
* Step 6: Don't break here if we are revision 1, this is
* so we do a blind write for load bug.
*/
*/
if (bStatus & LBCIF_STATUS_GENERAL_ERROR
&& pAdapter->RevisionID == 0) {
break;
@@ -342,9 +338,8 @@ int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
bControl = EXTRACT_CONTROL_REG(unData);
if (bControl != 0xC0 || nIndex == 10000) {
if (bControl != 0xC0 || nIndex == 10000)
break;
}
nIndex++;
}
@@ -366,7 +361,7 @@ int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
uint8_t *pbData, uint32_t unEepromId,
uint32_t unAddressingMode)
{
struct pci_dev *pdev = pAdapter->pdev;
struct pci_dev *pdev = pAdapter->pdev;
int32_t nIndex;
int32_t nError = 0;
uint8_t bControl;
@@ -425,17 +420,15 @@ int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
return FAILURE;
}
/* Step 2: */
bControl = 0;
bControl |= LBCIF_CONTROL_LBCIF_ENABLE;
if (unAddressingMode == DUAL_BYTE) {
if (unAddressingMode == DUAL_BYTE)
bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
}
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
bControl)) {
@@ -469,9 +462,8 @@ int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))
return FAILURE;
}
/* Step 6: */
*pbData = EXTRACT_DATA_REGISTER(unDword1);
drivers/staging/et131x/et1310_eeprom.h
+3 -3
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
drivers/staging/et131x/et1310_jagcore.c
+9 -11
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -73,9 +73,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -198,21 +198,19 @@ void et131x_enable_interrupts(struct et131x_adapter *adapter)
uint32_t MaskValue;
/* Enable all global interrupts */
if ((adapter->FlowControl == TxOnly) || (adapter->FlowControl == Both)) {
if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
MaskValue = INT_MASK_ENABLE;
} else {
else
MaskValue = INT_MASK_ENABLE_NO_FLOW;
}
if (adapter->DriverNoPhyAccess) {
if (adapter->DriverNoPhyAccess)
MaskValue |= 0x10000;
}
adapter->CachedMaskValue.value = MaskValue;
writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
}
void et131x_disable_interrupts(struct et131x_adapter * adapter)
void et131x_disable_interrupts(struct et131x_adapter *adapter)
{
/* Disable all global interrupts */
adapter->CachedMaskValue.value = INT_MASK_DISABLE;
drivers/staging/et131x/et1310_jagcore.h
+9 -8
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -62,8 +62,8 @@
#include "et1310_address_map.h"
#define INTERNAL_MEM_SIZE 0x400 //1024 of internal memory
#define INTERNAL_MEM_RX_OFFSET 0x1FF //50% Tx, 50% Rx
#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
#define REGS_MAX_ARRAY 4096
@@ -78,9 +78,10 @@
*/
#define INT_MASK_DISABLE 0xffffffff
// NOTE: Masking out MAC_STAT Interrupt for now...
//#define INT_MASK_ENABLE 0xfff6bf17
//#define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
/* NOTE: Masking out MAC_STAT Interrupt for now...
* #define INT_MASK_ENABLE 0xfff6bf17
* #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
*/
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
drivers/staging/et131x/et1310_mac.c
+47 -65
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -73,9 +73,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -118,10 +118,10 @@ void ConfigMACRegs1(struct et131x_adapter *pAdapter)
writel(0xC00F0000, &pMac->cfg1.value);
/* Next lets configure the MAC Inter-packet gap register */
ipg.bits.non_B2B_ipg_1 = 0x38; // 58d
ipg.bits.non_B2B_ipg_2 = 0x58; // 88d
ipg.bits.min_ifg_enforce = 0x50; // 80d
ipg.bits.B2B_ipg = 0x60; // 96d
ipg.bits.non_B2B_ipg_1 = 0x38; /* 58d */
ipg.bits.non_B2B_ipg_2 = 0x58; /* 88d */
ipg.bits.min_ifg_enforce = 0x50; /* 80d */
ipg.bits.B2B_ipg = 0x60; /* 96d */
writel(ipg.value, &pMac->ipg.value);
/* Next lets configure the MAC Half Duplex register */
@@ -131,7 +131,7 @@ void ConfigMACRegs1(struct et131x_adapter *pAdapter)
hfdp.bits.no_backoff = 0x0;
hfdp.bits.excess_defer = 0x1;
hfdp.bits.rexmit_max = 0xF;
hfdp.bits.coll_window = 0x37; // 55d
hfdp.bits.coll_window = 0x37; /* 55d */
writel(hfdp.value, &pMac->hfdp.value);
/* Next lets configure the MAC Interface Control register */
@@ -251,21 +251,20 @@ void ConfigMACRegs2(struct et131x_adapter *pAdapter)
udelay(10);
delay++;
cfg1.value = readl(&pMac->cfg1.value);
} while ((!cfg1.bits.syncd_rx_en ||
!cfg1.bits.syncd_tx_en) &&
delay < 100);
} while ((!cfg1.bits.syncd_rx_en || !cfg1.bits.syncd_tx_en) &&
delay < 100);
if (delay == 100) {
DBG_ERROR(et131x_dbginfo,
"Syncd bits did not respond correctly cfg1 word 0x%08x\n",
cfg1.value);
"Syncd bits did not respond correctly cfg1 word 0x%08x\n",
cfg1.value);
}
DBG_TRACE(et131x_dbginfo,
"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
readl(&pMac->if_ctrl.value));
"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
readl(&pMac->if_ctrl.value));
/* Enable TXMAC */
ctl.bits.txmac_en = 0x1;
@@ -409,11 +408,10 @@ void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
* bit 16: Receive frame truncated.
* bit 17: Drop packet enable
*/
if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS)
writel(0x30038, &pRxMac->mif_ctrl.value);
} else {
else
writel(0x30030, &pRxMac->mif_ctrl.value);
}
/* Finally we initialize RxMac to be enabled & WOL disabled. Packet
* filter is always enabled since it is where the runt packets are
@@ -540,7 +538,7 @@ void ConfigMacStatRegs(struct et131x_adapter *pAdapter)
DBG_LEAVE(et131x_dbginfo);
}
void ConfigFlowControl(struct et131x_adapter * pAdapter)
void ConfigFlowControl(struct et131x_adapter *pAdapter)
{
if (pAdapter->uiDuplexMode == 0) {
pAdapter->FlowControl = None;
@@ -558,21 +556,19 @@ void ConfigFlowControl(struct et131x_adapter * pAdapter)
pAdapter->FlowControl = pAdapter->RegistryFlowControl;
} else if ((RemotePause == TRUEPHY_BIT_SET) &&
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
if (pAdapter->RegistryFlowControl == Both) {
if (pAdapter->RegistryFlowControl == Both)
pAdapter->FlowControl = Both;
} else {
else
pAdapter->FlowControl = None;
}
} else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
pAdapter->FlowControl = None;
} else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
RemoteAsyncPause == TRUEPHY_SET_BIT) */
if (pAdapter->RegistryFlowControl == Both) {
if (pAdapter->RegistryFlowControl == Both)
pAdapter->FlowControl = RxOnly;
} else {
else
pAdapter->FlowControl = None;
}
}
}
}
@@ -635,48 +631,34 @@ void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)
* revolution of the counter. This routine is called when the counter
* block indicates that one of the counters has wrapped.
*/
if (Carry1.bits.rfcs) {
if (Carry1.bits.rfcs)
pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.raln) {
if (Carry1.bits.raln)
pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;
}
if (Carry1.bits.rflr) {
if (Carry1.bits.rflr)
pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rfrg) {
if (Carry1.bits.rfrg)
pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rcde) {
if (Carry1.bits.rcde)
pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rovr) {
if (Carry1.bits.rovr)
pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rdrp) {
if (Carry1.bits.rdrp)
pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
}
if (Carry2.bits.tovr) {
if (Carry2.bits.tovr)
pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tund) {
if (Carry2.bits.tund)
pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tscl) {
if (Carry2.bits.tscl)
pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tdfr) {
if (Carry2.bits.tdfr)
pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tmcl) {
if (Carry2.bits.tmcl)
pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tlcl) {
if (Carry2.bits.tlcl)
pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tncl) {
if (Carry2.bits.tncl)
pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;
}
DBG_LEAVE(et131x_dbginfo);
}
@@ -707,14 +689,14 @@ void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)
/* Loop through our multicast array and set up the device */
for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {
DBG_VERBOSE(et131x_dbginfo,
"MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
nIndex,
pAdapter->MCList[nIndex][0],
pAdapter->MCList[nIndex][1],
pAdapter->MCList[nIndex][2],
pAdapter->MCList[nIndex][3],
pAdapter->MCList[nIndex][4],
pAdapter->MCList[nIndex][5]);
"MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
nIndex,
pAdapter->MCList[nIndex][0],
pAdapter->MCList[nIndex][1],
pAdapter->MCList[nIndex][2],
pAdapter->MCList[nIndex][3],
pAdapter->MCList[nIndex][4],
pAdapter->MCList[nIndex][5]);
result = ether_crc(6, pAdapter->MCList[nIndex]);
drivers/staging/et131x/et1310_mac.h
+4 -4
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -73,7 +73,7 @@
#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
#define UPDATE_COUNTER(HostCnt,DevCnt) \
#define UPDATE_COUNTER(HostCnt, DevCnt) \
HostCnt = HostCnt + DevCnt;
/* Forward declaration of the private adapter structure */
drivers/staging/et131x/et1310_phy.c
+98 -104
View File
File diff suppressed because it is too large Load Diff
drivers/staging/et131x/et1310_phy.h
+449 -449
View File
File diff suppressed because it is too large Load Diff
drivers/staging/et131x/et1310_pm.c
+9 -10
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -73,9 +73,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -139,9 +139,8 @@ void EnablePhyComa(struct et131x_adapter *pAdapter)
spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags);
/* Wait for outstanding Receive packets */
while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0)) {
while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0))
mdelay(2);
}
/* Gate off JAGCore 3 clock domains */
GlobalPmCSR.bits.pm_sysclk_gate = 0;
@@ -188,9 +187,9 @@ void DisablePhyComa(struct et131x_adapter *pAdapter)
et131x_reset_recv(pAdapter);
/* Bring the device back to the state it was during init prior to
* autonegotiation being complete. This way, when we get the auto-neg
* complete interrupt, we can complete init by calling ConfigMacREGS2.
*/
* autonegotiation being complete. This way, when we get the auto-neg
* complete interrupt, we can complete init by calling ConfigMacREGS2.
*/
et131x_soft_reset(pAdapter);
/* setup et1310 as per the documentation ?? */
drivers/staging/et131x/et1310_pm.h
+4 -4
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -62,7 +62,7 @@
#include "et1310_address_map.h"
#define MAX_WOL_PACKET_SIZE 0x80
#define MAX_WOL_MASK_SIZE ( MAX_WOL_PACKET_SIZE / 8 )
#define MAX_WOL_MASK_SIZE (MAX_WOL_PACKET_SIZE / 8)
#define NUM_WOL_PATTERNS 0x5
#define CRC16_POLY 0x1021
drivers/staging/et131x/et1310_rx.c
+53 -62
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -74,9 +74,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -120,7 +120,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
DBG_ENTER(et131x_dbginfo);
/* Setup some convenience pointers */
rx_ring = (RX_RING_t *) & adapter->RxRing;
rx_ring = (RX_RING_t *) &adapter->RxRing;
/* Alloc memory for the lookup table */
#ifdef USE_FBR0
@@ -250,11 +250,10 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* the size of FBR0. By allocating N buffers at once, we
* reduce this overhead.
*/
if (rx_ring->Fbr1BufferSize > 4096) {
if (rx_ring->Fbr1BufferSize > 4096)
Fbr1Align = 4096;
} else {
else
Fbr1Align = rx_ring->Fbr1BufferSize;
}
FBRChunkSize =
(FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
@@ -443,7 +442,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
DBG_ENTER(et131x_dbginfo);
/* Setup some convenience pointers */
rx_ring = (RX_RING_t *) & adapter->RxRing;
rx_ring = (RX_RING_t *) &adapter->RxRing;
/* Free RFDs and associated packet descriptors */
DBG_ASSERT(rx_ring->nReadyRecv == rx_ring->NumRfd);
@@ -471,11 +470,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
if (rx_ring->Fbr1MemVa[index]) {
uint32_t Fbr1Align;
if (rx_ring->Fbr1BufferSize > 4096) {
if (rx_ring->Fbr1BufferSize > 4096)
Fbr1Align = 4096;
} else {
else
Fbr1Align = rx_ring->Fbr1BufferSize;
}
bufsize =
(rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
@@ -491,8 +489,8 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
}
/* Now the FIFO itself */
rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa -
rx_ring->Fbr1offset);
rx_ring->pFbr1RingVa = (void *)((uint8_t *)
rx_ring->pFbr1RingVa - rx_ring->Fbr1offset);
bufsize =
(sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
@@ -525,8 +523,8 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
}
/* Now the FIFO itself */
rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa -
rx_ring->Fbr0offset);
rx_ring->pFbr0RingVa = (void *)((uint8_t *)
rx_ring->pFbr0RingVa - rx_ring->Fbr0offset);
bufsize =
(sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
@@ -556,12 +554,12 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
/* Free area of memory for the writeback of status information */
if (rx_ring->pRxStatusVa) {
rx_ring->pRxStatusVa = (void *)((uint8_t *) rx_ring->pRxStatusVa -
rx_ring->RxStatusOffset);
rx_ring->pRxStatusVa = (void *)((uint8_t *)
rx_ring->pRxStatusVa - rx_ring->RxStatusOffset);
pci_free_consistent(adapter->pdev,
sizeof(RX_STATUS_BLOCK_t) + 0x7,
rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
sizeof(RX_STATUS_BLOCK_t) + 0x7,
rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
rx_ring->pRxStatusVa = NULL;
}
@@ -606,7 +604,7 @@ int et131x_init_recv(struct et131x_adapter *adapter)
DBG_ENTER(et131x_dbginfo);
/* Setup some convenience pointers */
rx_ring = (RX_RING_t *) & adapter->RxRing;
rx_ring = (RX_RING_t *) &adapter->RxRing;
/* Setup each RFD */
for (RfdCount = 0; RfdCount < rx_ring->NumRfd; RfdCount++) {
@@ -636,9 +634,8 @@ int et131x_init_recv(struct et131x_adapter *adapter)
TotalNumRfd++;
}
if (TotalNumRfd > NIC_MIN_NUM_RFD) {
if (TotalNumRfd > NIC_MIN_NUM_RFD)
status = 0;
}
rx_ring->NumRfd = TotalNumRfd;
@@ -841,11 +838,10 @@ void et131x_rx_dma_disable(struct et131x_adapter *pAdapter)
if (csr.bits.halt_status != 1) {
udelay(5);
csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
if (csr.bits.halt_status != 1) {
if (csr.bits.halt_status != 1)
DBG_ERROR(et131x_dbginfo,
"RX Dma failed to enter halt state. CSR 0x%08x\n",
csr.value);
}
"RX Dma failed to enter halt state. CSR 0x%08x\n",
csr.value);
}
DBG_LEAVE(et131x_dbginfo);
@@ -859,30 +855,28 @@ void et131x_rx_dma_enable(struct et131x_adapter *pAdapter)
{
DBG_RX_ENTER(et131x_dbginfo);
if (pAdapter->RegistryPhyLoopbk) {
/* RxDMA is disabled for loopback operation. */
if (pAdapter->RegistryPhyLoopbk)
/* RxDMA is disabled for loopback operation. */
writel(0x1, &pAdapter->CSRAddress->rxdma.csr.value);
} else {
else {
/* Setup the receive dma configuration register for normal operation */
RXDMA_CSR_t csr = { 0 };
csr.bits.fbr1_enable = 1;
if (pAdapter->RxRing.Fbr1BufferSize == 4096) {
if (pAdapter->RxRing.Fbr1BufferSize == 4096)
csr.bits.fbr1_size = 1;
} else if (pAdapter->RxRing.Fbr1BufferSize == 8192) {
else if (pAdapter->RxRing.Fbr1BufferSize == 8192)
csr.bits.fbr1_size = 2;
} else if (pAdapter->RxRing.Fbr1BufferSize == 16384) {
else if (pAdapter->RxRing.Fbr1BufferSize == 16384)
csr.bits.fbr1_size = 3;
}
#ifdef USE_FBR0
csr.bits.fbr0_enable = 1;
if (pAdapter->RxRing.Fbr0BufferSize == 256) {
if (pAdapter->RxRing.Fbr0BufferSize == 256)
csr.bits.fbr0_size = 1;
} else if (pAdapter->RxRing.Fbr0BufferSize == 512) {
else if (pAdapter->RxRing.Fbr0BufferSize == 512)
csr.bits.fbr0_size = 2;
} else if (pAdapter->RxRing.Fbr0BufferSize == 1024) {
else if (pAdapter->RxRing.Fbr0BufferSize == 1024)
csr.bits.fbr0_size = 3;
}
#endif
writel(csr.value, &pAdapter->CSRAddress->rxdma.csr.value);
@@ -892,8 +886,8 @@ void et131x_rx_dma_enable(struct et131x_adapter *pAdapter)
csr.value = readl(&pAdapter->CSRAddress->rxdma.csr.value);
if (csr.bits.halt_status != 0) {
DBG_ERROR(et131x_dbginfo,
"RX Dma failed to exit halt state. CSR 0x%08x\n",
csr.value);
"RX Dma failed to exit halt state. CSR 0x%08x\n",
csr.value);
}
}
}
@@ -938,8 +932,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *pAdapter)
if (pRxStatusBlock->Word1.bits.PSRoffset ==
pRxLocal->local_psr_full.bits.psr_full &&
pRxStatusBlock->Word1.bits.PSRwrap ==
pRxLocal->local_psr_full.bits.psr_full_wrap) {
pRxStatusBlock->Word1.bits.PSRwrap ==
pRxLocal->local_psr_full.bits.psr_full_wrap) {
/* Looks like this ring is not updated yet */
DBG_RX(et131x_dbginfo, "(0)\n");
DBG_RX_LEAVE(et131x_dbginfo);
@@ -999,13 +993,13 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *pAdapter)
#ifdef USE_FBR0
if (ringIndex > 1 ||
(ringIndex == 0 &&
bufferIndex > pRxLocal->Fbr0NumEntries - 1) ||
(ringIndex == 1 &&
bufferIndex > pRxLocal->Fbr1NumEntries - 1))
(ringIndex == 0 &&
bufferIndex > pRxLocal->Fbr0NumEntries - 1) ||
(ringIndex == 1 &&
bufferIndex > pRxLocal->Fbr1NumEntries - 1))
#else
if (ringIndex != 1 ||
bufferIndex > pRxLocal->Fbr1NumEntries - 1)
bufferIndex > pRxLocal->Fbr1NumEntries - 1)
#endif
{
/* Illegal buffer or ring index cannot be used by S/W*/
@@ -1124,30 +1118,27 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *pAdapter)
* so we free our RFD when we return
* from this function.
*/
if (nIndex == pAdapter->MCAddressCount) {
if (nIndex == pAdapter->MCAddressCount)
localLen = 0;
}
}
if (localLen > 0) {
if (localLen > 0)
pAdapter->Stats.multircv++;
}
} else if (Word0.value & ALCATEL_BROADCAST_PKT) {
} else if (Word0.value & ALCATEL_BROADCAST_PKT)
pAdapter->Stats.brdcstrcv++;
} else {
else
/* Not sure what this counter measures in
* promiscuous mode. Perhaps we should check
* the MAC address to see if it is directed
* to us in promiscuous mode.
*/
pAdapter->Stats.unircv++;
}
}
if (localLen > 0) {
struct sk_buff *skb = NULL;
//pMpRfd->PacketSize = localLen - 4;
/* pMpRfd->PacketSize = localLen - 4; */
pMpRfd->PacketSize = localLen;
skb = dev_alloc_skb(pMpRfd->PacketSize + 2);
@@ -1240,9 +1231,8 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *pAdapter)
pMpRfd = nic_rx_pkts(pAdapter);
if (pMpRfd == NULL) {
if (pMpRfd == NULL)
break;
}
/* Do not receive any packets until a filter has been set.
* Do not receive any packets until we are at D0.
@@ -1270,12 +1260,13 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *pAdapter)
* Besides, we don't really need (at this point) the
* pending list anyway.
*/
//spin_lock_irqsave( &pAdapter->RcvPendLock, lockflags );
//list_add_tail( &pMpRfd->list_node, &pAdapter->RxRing.RecvPendingList );
//spin_unlock_irqrestore( &pAdapter->RcvPendLock, lockflags );
/* spin_lock_irqsave( &pAdapter->RcvPendLock, lockflags );
* list_add_tail( &pMpRfd->list_node, &pAdapter->RxRing.RecvPendingList );
* spin_unlock_irqrestore( &pAdapter->RcvPendLock, lockflags );
*/
/* Update the number of outstanding Recvs */
//MP_INC_RCV_REF( pAdapter );
/* MP_INC_RCV_REF( pAdapter ); */
} else {
RFDFreeArray[PacketFreeCount] = pMpRfd;
PacketFreeCount++;
drivers/staging/et131x/et1310_rx.h
+97 -97
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -64,10 +64,10 @@
#define USE_FBR0 true
#ifdef USE_FBR0
//#define FBR0_BUFFER_SIZE 256
/* #define FBR0_BUFFER_SIZE 256 */
#endif
//#define FBR1_BUFFER_SIZE 2048
/* #define FBR1_BUFFER_SIZE 2048 */
#define FBR_CHUNKS 32
@@ -95,11 +95,11 @@ typedef union _FBR_WORD2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:22; // bits 10-31
u32 bi:10; // bits 0-9(Buffer Index)
u32 reserved:22; /* bits 10-31 */
u32 bi:10; /* bits 0-9(Buffer Index) */
#else
u32 bi:10; // bits 0-9(Buffer Index)
u32 reserved:22; // bit 10-31
u32 bi:10; /* bits 0-9(Buffer Index) */
u32 reserved:22; /* bit 10-31 */
#endif
} bits;
} FBR_WORD2_t, *PFBR_WORD2_t;
@@ -115,70 +115,70 @@ typedef union _PKT_STAT_DESC_WORD0_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
// top 16 bits are from the Alcatel Status Word as enumerated in
// PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
/* top 16 bits are from the Alcatel Status Word as enumerated in */
/* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */
#if 0
u32 asw_trunc:1; // bit 31(Rx frame truncated)
u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
#endif
u32 asw_long_evt:1; // bit 31(Rx long event)
u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
u32 asw_pause_frame:1; // bit 28(is a pause frame)
u32 asw_control_frame:1; // bit 27(is a control frame)
u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
u32 asw_broadcast:1; // bit 25(has a broadcast address)
u32 asw_multicast:1; // bit 24(has a multicast address)
u32 asw_OK:1; // bit 23(valid CRC + no code error)
u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
u32 asw_CRC_err:1; // bit 20(CRC error)
u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
u32 unused:5; // bits 11-15
u32 vp:1; // bit 10(VLAN Packet)
u32 jp:1; // bit 9(Jumbo Packet)
u32 ft:1; // bit 8(Frame Truncated)
u32 drop:1; // bit 7(Drop packet)
u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
u32 wol:1; // bit 5(WOL Event)
u32 tcpp:1; // bit 4(TCP checksum pass)
u32 tcpa:1; // bit 3(TCP checksum assist)
u32 ipp:1; // bit 2(IP checksum pass)
u32 ipa:1; // bit 1(IP checksum assist)
u32 hp:1; // bit 0(hash pass)
u32 asw_long_evt:1; /* bit 31(Rx long event) */
u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
u32 asw_control_frame:1; /* bit 27(is a control frame) */
u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
u32 asw_multicast:1; /* bit 24(has a multicast address) */
u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
u32 asw_CRC_err:1; /* bit 20(CRC error) */
u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
u32 unused:5; /* bits 11-15 */
u32 vp:1; /* bit 10(VLAN Packet) */
u32 jp:1; /* bit 9(Jumbo Packet) */
u32 ft:1; /* bit 8(Frame Truncated) */
u32 drop:1; /* bit 7(Drop packet) */
u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
u32 wol:1; /* bit 5(WOL Event) */
u32 tcpp:1; /* bit 4(TCP checksum pass) */
u32 tcpa:1; /* bit 3(TCP checksum assist) */
u32 ipp:1; /* bit 2(IP checksum pass) */
u32 ipa:1; /* bit 1(IP checksum assist) */
u32 hp:1; /* bit 0(hash pass) */
#else
u32 hp:1; // bit 0(hash pass)
u32 ipa:1; // bit 1(IP checksum assist)
u32 ipp:1; // bit 2(IP checksum pass)
u32 tcpa:1; // bit 3(TCP checksum assist)
u32 tcpp:1; // bit 4(TCP checksum pass)
u32 wol:1; // bit 5(WOL Event)
u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
u32 drop:1; // bit 7(Drop packet)
u32 ft:1; // bit 8(Frame Truncated)
u32 jp:1; // bit 9(Jumbo Packet)
u32 vp:1; // bit 10(VLAN Packet)
u32 unused:5; // bits 11-15
u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
u32 asw_CRC_err:1; // bit 20(CRC error)
u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
u32 asw_OK:1; // bit 23(valid CRC + no code error)
u32 asw_multicast:1; // bit 24(has a multicast address)
u32 asw_broadcast:1; // bit 25(has a broadcast address)
u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
u32 asw_control_frame:1; // bit 27(is a control frame)
u32 asw_pause_frame:1; // bit 28(is a pause frame)
u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
u32 asw_long_evt:1; // bit 31(Rx long event)
u32 hp:1; /* bit 0(hash pass) */
u32 ipa:1; /* bit 1(IP checksum assist) */
u32 ipp:1; /* bit 2(IP checksum pass) */
u32 tcpa:1; /* bit 3(TCP checksum assist) */
u32 tcpp:1; /* bit 4(TCP checksum pass) */
u32 wol:1; /* bit 5(WOL Event) */
u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
u32 drop:1; /* bit 7(Drop packet) */
u32 ft:1; /* bit 8(Frame Truncated) */
u32 jp:1; /* bit 9(Jumbo Packet) */
u32 vp:1; /* bit 10(VLAN Packet) */
u32 unused:5; /* bits 11-15 */
u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
u32 asw_CRC_err:1; /* bit 20(CRC error) */
u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
u32 asw_multicast:1; /* bit 24(has a multicast address) */
u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
u32 asw_control_frame:1; /* bit 27(is a control frame) */
u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
u32 asw_long_evt:1; /* bit 31(Rx long event) */
#if 0
u32 asw_trunc:1; // bit 31(Rx frame truncated)
u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
#endif
#endif
} bits;
@@ -188,15 +188,15 @@ typedef union _PKT_STAT_DESC_WORD1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:4; // bits 28-31
u32 ri:2; // bits 26-27(Ring Index)
u32 bi:10; // bits 16-25(Buffer Index)
u32 length:16; // bit 0-15(length in bytes)
u32 unused:4; /* bits 28-31 */
u32 ri:2; /* bits 26-27(Ring Index) */
u32 bi:10; /* bits 16-25(Buffer Index) */
u32 length:16; /* bit 0-15(length in bytes) */
#else
u32 length:16; // bit 0-15(length in bytes)
u32 bi:10; // bits 16-25(Buffer Index)
u32 ri:2; // bits 26-27(Ring Index)
u32 unused:4; // bits 28-31
u32 length:16; /* bit 0-15(length in bytes) */
u32 bi:10; /* bits 16-25(Buffer Index) */
u32 ri:2; /* bits 26-27(Ring Index) */
u32 unused:4; /* bits 28-31 */
#endif
} bits;
} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
@@ -217,19 +217,19 @@ typedef union _rxstat_word0_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 FBR1unused:5; // bits 27-31
u32 FBR1wrap:1; // bit 26
u32 FBR1offset:10; // bits 16-25
u32 FBR0unused:5; // bits 11-15
u32 FBR0wrap:1; // bit 10
u32 FBR0offset:10; // bits 0-9
u32 FBR1unused:5; /* bits 27-31 */
u32 FBR1wrap:1; /* bit 26 */
u32 FBR1offset:10; /* bits 16-25 */
u32 FBR0unused:5; /* bits 11-15 */
u32 FBR0wrap:1; /* bit 10 */
u32 FBR0offset:10; /* bits 0-9 */
#else
u32 FBR0offset:10; // bits 0-9
u32 FBR0wrap:1; // bit 10
u32 FBR0unused:5; // bits 11-15
u32 FBR1offset:10; // bits 16-25
u32 FBR1wrap:1; // bit 26
u32 FBR1unused:5; // bits 27-31
u32 FBR0offset:10; /* bits 0-9 */
u32 FBR0wrap:1; /* bit 10 */
u32 FBR0unused:5; /* bits 11-15 */
u32 FBR1offset:10; /* bits 16-25 */
u32 FBR1wrap:1; /* bit 26 */
u32 FBR1unused:5; /* bits 27-31 */
#endif
} bits;
} RXSTAT_WORD0_t, *PRXSTAT_WORD0_t;
@@ -243,15 +243,15 @@ typedef union _rxstat_word1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 PSRunused:3; // bits 29-31
u32 PSRwrap:1; // bit 28
u32 PSRoffset:12; // bits 16-27
u32 reserved:16; // bits 0-15
u32 PSRunused:3; /* bits 29-31 */
u32 PSRwrap:1; /* bit 28 */
u32 PSRoffset:12; /* bits 16-27 */
u32 reserved:16; /* bits 0-15 */
#else
u32 reserved:16; // bits 0-15
u32 PSRoffset:12; // bits 16-27
u32 PSRwrap:1; // bit 28
u32 PSRunused:3; // bits 29-31
u32 reserved:16; /* bits 0-15 */
u32 PSRoffset:12; /* bits 16-27 */
u32 PSRwrap:1; /* bit 28 */
u32 PSRunused:3; /* bits 29-31 */
#endif
} bits;
} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
drivers/staging/et131x/et1310_tx.c
+55 -65
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -74,9 +74,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -127,7 +127,7 @@ int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
DBG_ENTER(et131x_dbginfo);
/* Allocate memory for the TCB's (Transmit Control Block) */
adapter->TxRing.MpTcbMem = (MP_TCB *) kcalloc(NUM_TCB, sizeof(MP_TCB),
adapter->TxRing.MpTcbMem = (MP_TCB *)kcalloc(NUM_TCB, sizeof(MP_TCB),
GFP_ATOMIC | GFP_DMA);
if (!adapter->TxRing.MpTcbMem) {
DBG_ERROR(et131x_dbginfo, "Cannot alloc memory for TCBs\n");
@@ -238,10 +238,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
}
/* Free the memory for MP_TCB structures */
if (adapter->TxRing.MpTcbMem) {
kfree(adapter->TxRing.MpTcbMem);
adapter->TxRing.MpTcbMem = NULL;
}
kfree(adapter->TxRing.MpTcbMem);
DBG_LEAVE(et131x_dbginfo);
}
@@ -308,7 +305,7 @@ void et131x_tx_dma_enable(struct et131x_adapter *pAdapter)
DBG_ENTER(et131x_dbginfo);
if (pAdapter->RegistryPhyLoopbk) {
/* TxDMA is disabled for loopback operation. */
/* TxDMA is disabled for loopback operation. */
writel(0x101, &pAdapter->CSRAddress->txdma.csr.value);
} else {
TXDMA_CSR_t csr = { 0 };
@@ -405,11 +402,14 @@ int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
/* We need to see if the link is up; if it's not, make the
* netif layer think we're good and drop the packet
*/
//if( MP_SHOULD_FAIL_SEND( pAdapter ) || pAdapter->DriverNoPhyAccess )
/*
* if( MP_SHOULD_FAIL_SEND( pAdapter ) ||
* pAdapter->DriverNoPhyAccess )
*/
if (MP_SHOULD_FAIL_SEND(pAdapter) || pAdapter->DriverNoPhyAccess
|| !netif_carrier_ok(netdev)) {
DBG_VERBOSE(et131x_dbginfo,
"Can't Tx, Link is DOWN; drop the packet\n");
"Can't Tx, Link is DOWN; drop the packet\n");
dev_kfree_skb_any(skb);
skb = NULL;
@@ -496,9 +496,8 @@ static int et131x_send_packet(struct sk_buff *skb,
pAdapter->TxRing.TCBReadyQueueHead = pMpTcb->Next;
if (pAdapter->TxRing.TCBReadyQueueHead == NULL) {
if (pAdapter->TxRing.TCBReadyQueueHead == NULL)
pAdapter->TxRing.TCBReadyQueueTail = NULL;
}
spin_unlock_irqrestore(&pAdapter->TCBReadyQLock, lockflags);
@@ -519,9 +518,8 @@ static int et131x_send_packet(struct sk_buff *skb,
pMpTcb->Next = NULL;
/* Call the NIC specific send handler. */
if (status == 0) {
if (status == 0)
status = nic_send_packet(pAdapter, pMpTcb);
}
if (status != 0) {
spin_lock_irqsave(&pAdapter->TCBReadyQLock, lockflags);
@@ -749,11 +747,10 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
if ((pAdapter->TxRing.txDmaReadyToSend.bits.val == 0) ||
(pAdapter->TxRing.txDmaReadyToSend.bits.val ==
NUM_DESC_PER_RING_TX)) {
if (pAdapter->TxRing.txDmaReadyToSend.bits.wrap) {
if (pAdapter->TxRing.txDmaReadyToSend.bits.wrap)
pAdapter->TxRing.txDmaReadyToSend.value = 0;
} else {
else
pAdapter->TxRing.txDmaReadyToSend.value = 0x400;
}
}
if (iRemainder) {
@@ -765,24 +762,21 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
}
if (pAdapter->TxRing.txDmaReadyToSend.bits.val == 0) {
if (pAdapter->TxRing.txDmaReadyToSend.value) {
if (pAdapter->TxRing.txDmaReadyToSend.value)
pMpTcb->WrIndex.value = NUM_DESC_PER_RING_TX - 1;
} else {
else
pMpTcb->WrIndex.value =
0x400 | (NUM_DESC_PER_RING_TX - 1);
}
} else {
} else
pMpTcb->WrIndex.value =
pAdapter->TxRing.txDmaReadyToSend.value - 1;
}
spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags2);
if (pAdapter->TxRing.CurrSendTail) {
if (pAdapter->TxRing.CurrSendTail)
pAdapter->TxRing.CurrSendTail->Next = pMpTcb;
} else {
else
pAdapter->TxRing.CurrSendHead = pMpTcb;
}
pAdapter->TxRing.CurrSendTail = pMpTcb;
@@ -870,14 +864,14 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
DBG_TX(et131x_dbginfo,
"Even number of descs, split 1st elem\n");
iSplitFirstElement = 1;
//SegmentSize = pFragList[0].size / 2;
/* SegmentSize = pFragList[0].size / 2; */
SegmentSize = (pPacket->len - pPacket->data_len) / 2;
}
} else if (FragListCount & 0x1) {
DBG_TX(et131x_dbginfo, "Odd number of descs, split 1st elem\n");
iSplitFirstElement = 1;
//SegmentSize = pFragList[0].size / 2;
/* SegmentSize = pFragList[0].size / 2; */
SegmentSize = (pPacket->len - pPacket->data_len) / 2;
}
@@ -918,9 +912,8 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
FragListCount, iSplitFirstElement, loopEnd);
for (loopIndex = 0; loopIndex < loopEnd; loopIndex++) {
if (loopIndex > iSplitFirstElement) {
if (loopIndex > iSplitFirstElement)
fragIndex++;
}
DBG_TX(et131x_dbginfo,
"In loop, loopIndex: %d\t fragIndex: %d\n", loopIndex,
@@ -935,13 +928,17 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
pPacket->len,
pAdapter->TxRing.txDmaReadyToSend.bits.serv_req);
// NOTE - Should we do a paranoia check here to make sure the fragment
// actually has a length? It's HIGHLY unlikely the fragment would
// contain no data...
/*
* NOTE - Should we do a paranoia check here to make sure the fragment
* actually has a length? It's HIGHLY unlikely the fragment would
* contain no data...
*/
if (1) {
// NOTE - Currently always getting 32-bit addrs, and dma_addr_t is
// only 32-bit, so leave "high" ptr value out for now
CurDesc.DataBufferPtrHigh = 0;
/* NOTE - Currently always getting 32-bit addrs, and
* dma_addr_t is only 32-bit, so leave "high" ptr
* value out for now
* CurDesc.DataBufferPtrHigh = 0;
*/
CurDesc.word2.value = 0;
CurDesc.word3.value = 0;
@@ -1128,7 +1125,7 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
if (pAdapter->uiDuplexMode == 0 &&
pMpTcb->PacketLength < NIC_MIN_PACKET_SIZE) {
// NOTE - Same 32/64-bit issue as above...
/* NOTE - Same 32/64-bit issue as above... */
CurDesc.DataBufferPtrHigh = 0x0;
CurDesc.DataBufferPtrLow = pAdapter->TxRing.pTxDummyBlkPa;
CurDesc.word2.value = 0;
@@ -1183,18 +1180,17 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
}
DBG_TX(et131x_dbginfo, "Padding descriptor %d by %d bytes\n",
//pAdapter->TxRing.txDmaReadyToSend.value,
/* pAdapter->TxRing.txDmaReadyToSend.value, */
pAdapter->TxRing.txDmaReadyToSend.bits.serv_req,
NIC_MIN_PACKET_SIZE - pMpTcb->PacketLength);
}
spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags2);
if (pAdapter->TxRing.CurrSendTail) {
if (pAdapter->TxRing.CurrSendTail)
pAdapter->TxRing.CurrSendTail->Next = pMpTcb;
} else {
else
pAdapter->TxRing.CurrSendHead = pMpTcb;
}
pAdapter->TxRing.CurrSendTail = pMpTcb;
@@ -1235,19 +1231,19 @@ static int nic_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
*
* Assumption - Send spinlock has been acquired
*/
__inline void et131x_free_send_packet(struct et131x_adapter *pAdapter, PMP_TCB pMpTcb)
inline void et131x_free_send_packet(struct et131x_adapter *pAdapter,
PMP_TCB pMpTcb)
{
unsigned long lockflags;
TX_DESC_ENTRY_t *desc = NULL;
struct net_device_stats *stats = &pAdapter->net_stats;
if (MP_TEST_FLAG(pMpTcb, fMP_DEST_BROAD)) {
if (MP_TEST_FLAG(pMpTcb, fMP_DEST_BROAD))
atomic_inc(&pAdapter->Stats.brdcstxmt);
} else if (MP_TEST_FLAG(pMpTcb, fMP_DEST_MULTI)) {
else if (MP_TEST_FLAG(pMpTcb, fMP_DEST_MULTI))
atomic_inc(&pAdapter->Stats.multixmt);
} else {
else
atomic_inc(&pAdapter->Stats.unixmt);
}
if (pMpTcb->Packet) {
stats->tx_bytes += pMpTcb->Packet->len;
@@ -1298,14 +1294,12 @@ __inline void et131x_free_send_packet(struct et131x_adapter *pAdapter, PMP_TCB p
if (++pMpTcb->WrIndexStart.bits.val >=
NUM_DESC_PER_RING_TX) {
if (pMpTcb->WrIndexStart.bits.wrap) {
if (pMpTcb->WrIndexStart.bits.wrap)
pMpTcb->WrIndexStart.value = 0;
} else {
else
pMpTcb->WrIndexStart.value = 0x400;
}
}
}
while (desc != (pAdapter->TxRing.pTxDescRingVa +
} while (desc != (pAdapter->TxRing.pTxDescRingVa +
pMpTcb->WrIndex.bits.val));
DBG_TX(et131x_dbginfo,
@@ -1371,9 +1365,8 @@ void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter)
pAdapter->TxRing.CurrSendHead = pNext;
if (pNext == NULL) {
if (pNext == NULL)
pAdapter->TxRing.CurrSendTail = NULL;
}
pAdapter->TxRing.nBusySend--;
@@ -1391,7 +1384,7 @@ void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter)
if (FreeCounter == NUM_TCB) {
DBG_ERROR(et131x_dbginfo,
"MpFreeBusySendPackets exitted loop for a bad reason\n");
"MpFreeBusySendPackets exitted loop for a bad reason\n");
BUG();
}
@@ -1454,9 +1447,8 @@ static void et131x_update_tcb_list(struct et131x_adapter *pAdapter)
ServiceComplete.bits.val < pMpTcb->WrIndex.bits.val) {
pAdapter->TxRing.nBusySend--;
pAdapter->TxRing.CurrSendHead = pMpTcb->Next;
if (pMpTcb->Next == NULL) {
if (pMpTcb->Next == NULL)
pAdapter->TxRing.CurrSendTail = NULL;
}
spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
MP_FREE_SEND_PACKET_FUN(pAdapter, pMpTcb);
@@ -1470,9 +1462,8 @@ static void et131x_update_tcb_list(struct et131x_adapter *pAdapter)
ServiceComplete.bits.val > pMpTcb->WrIndex.bits.val) {
pAdapter->TxRing.nBusySend--;
pAdapter->TxRing.CurrSendHead = pMpTcb->Next;
if (pMpTcb->Next == NULL) {
if (pMpTcb->Next == NULL)
pAdapter->TxRing.CurrSendTail = NULL;
}
spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
MP_FREE_SEND_PACKET_FUN(pAdapter, pMpTcb);
@@ -1483,9 +1474,8 @@ static void et131x_update_tcb_list(struct et131x_adapter *pAdapter)
}
/* Wake up the queue when we hit a low-water mark */
if (pAdapter->TxRing.nBusySend <= (NUM_TCB / 3)) {
if (pAdapter->TxRing.nBusySend <= (NUM_TCB / 3))
netif_wake_queue(pAdapter->netdev);
}
spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
}
@@ -1504,7 +1494,7 @@ static void et131x_check_send_wait_list(struct et131x_adapter *pAdapter)
spin_lock_irqsave(&pAdapter->SendWaitLock, lockflags);
while (!list_empty(&pAdapter->TxRing.SendWaitQueue) &&
MP_TCB_RESOURCES_AVAILABLE(pAdapter)) {
MP_TCB_RESOURCES_AVAILABLE(pAdapter)) {
struct list_head *pEntry;
DBG_VERBOSE(et131x_dbginfo, "Tx packets on the wait queue\n");
@@ -1514,8 +1504,8 @@ static void et131x_check_send_wait_list(struct et131x_adapter *pAdapter)
pAdapter->TxRing.nWaitSend--;
DBG_WARNING(et131x_dbginfo,
"MpHandleSendInterrupt - sent a queued pkt. Waiting %d\n",
pAdapter->TxRing.nWaitSend);
"MpHandleSendInterrupt - sent a queued pkt. Waiting %d\n",
pAdapter->TxRing.nWaitSend);
}
spin_unlock_irqrestore(&pAdapter->SendWaitLock, lockflags);
drivers/staging/et131x/et1310_tx.h
+51 -51
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -70,15 +70,15 @@ typedef union _txdesc_word2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 vlan_prio:3; // bits 29-31(VLAN priority)
u32 vlan_cfi:1; // bit 28(cfi)
u32 vlan_tag:12; // bits 16-27(VLAN tag)
u32 length_in_bytes:16; // bits 0-15(packet length)
u32 vlan_prio:3; /* bits 29-31(VLAN priority) */
u32 vlan_cfi:1; /* bit 28(cfi) */
u32 vlan_tag:12; /* bits 16-27(VLAN tag) */
u32 length_in_bytes:16; /* bits 0-15(packet length) */
#else
u32 length_in_bytes:16; // bits 0-15(packet length)
u32 vlan_tag:12; // bits 16-27(VLAN tag)
u32 vlan_cfi:1; // bit 28(cfi)
u32 vlan_prio:3; // bits 29-31(VLAN priority)
u32 length_in_bytes:16; /* bits 0-15(packet length) */
u32 vlan_tag:12; /* bits 16-27(VLAN tag) */
u32 vlan_cfi:1; /* bit 28(cfi) */
u32 vlan_prio:3; /* bits 29-31(VLAN priority) */
#endif /* _BIT_FIELDS_HTOL */
} bits;
} TXDESC_WORD2_t, *PTXDESC_WORD2_t;
@@ -91,39 +91,39 @@ typedef union _txdesc_word3_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:17; // bits 15-31
u32 udpa:1; // bit 14(UDP checksum assist)
u32 tcpa:1; // bit 13(TCP checksum assist)
u32 ipa:1; // bit 12(IP checksum assist)
u32 vlan:1; // bit 11(append VLAN tag)
u32 hp:1; // bit 10(Packet is a Huge packet)
u32 pp:1; // bit 9(pad packet)
u32 mac:1; // bit 8(MAC override)
u32 crc:1; // bit 7(append CRC)
u32 e:1; // bit 6(Tx frame has error)
u32 pf:1; // bit 5(send pause frame)
u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
u32 cw:1; // bit 3(Control word - no packet data)
u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
u32 f:1; // bit 1(first packet in the sequence)
u32 l:1; // bit 0(last packet in the sequence)
u32 unused:17; /* bits 15-31 */
u32 udpa:1; /* bit 14(UDP checksum assist) */
u32 tcpa:1; /* bit 13(TCP checksum assist) */
u32 ipa:1; /* bit 12(IP checksum assist) */
u32 vlan:1; /* bit 11(append VLAN tag) */
u32 hp:1; /* bit 10(Packet is a Huge packet) */
u32 pp:1; /* bit 9(pad packet) */
u32 mac:1; /* bit 8(MAC override) */
u32 crc:1; /* bit 7(append CRC) */
u32 e:1; /* bit 6(Tx frame has error) */
u32 pf:1; /* bit 5(send pause frame) */
u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
u32 cw:1; /* bit 3(Control word - no packet data) */
u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
u32 f:1; /* bit 1(first packet in the sequence) */
u32 l:1; /* bit 0(last packet in the sequence) */
#else
u32 l:1; // bit 0(last packet in the sequence)
u32 f:1; // bit 1(first packet in the sequence)
u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
u32 cw:1; // bit 3(Control word - no packet data)
u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
u32 pf:1; // bit 5(send pause frame)
u32 e:1; // bit 6(Tx frame has error)
u32 crc:1; // bit 7(append CRC)
u32 mac:1; // bit 8(MAC override)
u32 pp:1; // bit 9(pad packet)
u32 hp:1; // bit 10(Packet is a Huge packet)
u32 vlan:1; // bit 11(append VLAN tag)
u32 ipa:1; // bit 12(IP checksum assist)
u32 tcpa:1; // bit 13(TCP checksum assist)
u32 udpa:1; // bit 14(UDP checksum assist)
u32 unused:17; // bits 15-31
u32 l:1; /* bit 0(last packet in the sequence) */
u32 f:1; /* bit 1(first packet in the sequence) */
u32 ir:1; /* bit 2(interrupt the processor when this pkt sent) */
u32 cw:1; /* bit 3(Control word - no packet data) */
u32 bp:1; /* bit 4(Issue half-duplex backpressure (XON/XOFF) */
u32 pf:1; /* bit 5(send pause frame) */
u32 e:1; /* bit 6(Tx frame has error) */
u32 crc:1; /* bit 7(append CRC) */
u32 mac:1; /* bit 8(MAC override) */
u32 pp:1; /* bit 9(pad packet) */
u32 hp:1; /* bit 10(Packet is a Huge packet) */
u32 vlan:1; /* bit 11(append VLAN tag) */
u32 ipa:1; /* bit 12(IP checksum assist) */
u32 tcpa:1; /* bit 13(TCP checksum assist) */
u32 udpa:1; /* bit 14(UDP checksum assist) */
u32 unused:17; /* bits 15-31 */
#endif /* _BIT_FIELDS_HTOL */
} bits;
} TXDESC_WORD3_t, *PTXDESC_WORD3_t;
@@ -132,8 +132,8 @@ typedef union _txdesc_word3_t {
typedef struct _tx_desc_entry_t {
u32 DataBufferPtrHigh;
u32 DataBufferPtrLow;
TXDESC_WORD2_t word2; // control words how to xmit the
TXDESC_WORD3_t word3; // data (detailed above)
TXDESC_WORD2_t word2; /* control words how to xmit the */
TXDESC_WORD3_t word3; /* data (detailed above) */
} TX_DESC_ENTRY_t, *PTX_DESC_ENTRY_t;
@@ -147,13 +147,13 @@ typedef union _tx_status_block_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:21; // bits 11-31
u32 serv_cpl_wrap:1; // bit 10
u32 serv_cpl:10; // bits 0-9
u32 unused:21; /* bits 11-31 */
u32 serv_cpl_wrap:1; /* bit 10 */
u32 serv_cpl:10; /* bits 0-9 */
#else
u32 serv_cpl:10; // bits 0-9
u32 serv_cpl_wrap:1; // bit 10
u32 unused:21; // bits 11-31
u32 serv_cpl:10; /* bits 0-9 */
u32 serv_cpl_wrap:1; /* bit 10 */
u32 unused:21; /* bits 11-31 */
#endif
} bits;
} TX_STATUS_BLOCK_t, *PTX_STATUS_BLOCK_t;
drivers/staging/et131x/et131x_adapter.h
+36 -36
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -67,7 +67,7 @@
* Do not change these values: if changed, then change also in respective
* TXdma and Rxdma engines
*/
#define NUM_DESC_PER_RING_TX 512 // TX Do not change these values
#define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
#define NUM_TCB 64
/*
@@ -118,10 +118,10 @@
#define MP_SHOULD_FAIL_SEND(_M) ((_M)->Flags & fMP_ADAPTER_FAIL_SEND_MASK)
#define MP_IS_NOT_READY(_M) ((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
#define MP_IS_READY(_M) !((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
#define MP_IS_READY(_M) (!((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK))
#define MP_HAS_CABLE(_M) !((_M)->Flags & fMP_ADAPTER_NO_CABLE)
#define MP_LINK_DETECTED(_M) !((_M)->Flags & fMP_ADAPTER_LINK_DETECTION)
#define MP_HAS_CABLE(_M) (!((_M)->Flags & fMP_ADAPTER_NO_CABLE))
#define MP_LINK_DETECTED(_M) (!((_M)->Flags & fMP_ADAPTER_LINK_DETECTION))
/* Counters for error rate monitoring */
typedef struct _MP_ERR_COUNTERS {
@@ -136,7 +136,7 @@ typedef struct _MP_ERR_COUNTERS {
typedef struct _MP_RFD {
struct list_head list_node;
struct sk_buff *Packet;
u32 PacketSize; // total size of receive frame
u32 PacketSize; /* total size of receive frame */
u16 iBufferIndex;
u8 iRingIndex;
} MP_RFD, *PMP_RFD;
@@ -152,8 +152,8 @@ typedef enum _eflow_control_t {
/* Struct to define some device statistics */
typedef struct _ce_stats_t {
/* Link Input/Output stats */
uint64_t ipackets; // # of in packets
uint64_t opackets; // # of out packets
uint64_t ipackets; /* # of in packets */
uint64_t opackets; /* # of out packets */
/* MIB II variables
*
@@ -161,21 +161,21 @@ typedef struct _ce_stats_t {
* MUST have 32, then we'll need another way to perform atomic
* operations
*/
u32 unircv; // # multicast packets received
atomic_t unixmt; // # multicast packets for Tx
u32 multircv; // # multicast packets received
atomic_t multixmt; // # multicast packets for Tx
u32 brdcstrcv; // # broadcast packets received
atomic_t brdcstxmt; // # broadcast packets for Tx
u32 norcvbuf; // # Rx packets discarded
u32 noxmtbuf; // # Tx packets discarded
u32 unircv; /* # multicast packets received */
atomic_t unixmt; /* # multicast packets for Tx */
u32 multircv; /* # multicast packets received */
atomic_t multixmt; /* # multicast packets for Tx */
u32 brdcstrcv; /* # broadcast packets received */
atomic_t brdcstxmt; /* # broadcast packets for Tx */
u32 norcvbuf; /* # Rx packets discarded */
u32 noxmtbuf; /* # Tx packets discarded */
/* Transciever state informations. */
u8 xcvr_addr;
u32 xcvr_id;
/* Tx Statistics. */
u32 tx_uflo; // Tx Underruns
u32 tx_uflo; /* Tx Underruns */
u32 collisions;
u32 excessive_collisions;
@@ -185,7 +185,7 @@ typedef struct _ce_stats_t {
u32 tx_deferred;
/* Rx Statistics. */
u32 rx_ov_flow; // Rx Over Flow
u32 rx_ov_flow; /* Rx Over Flow */
u32 length_err;
u32 alignment_err;
@@ -268,16 +268,16 @@ struct et131x_adapter {
u32 pci_cfg_state[64 / sizeof(u32)];
/* Registry parameters */
u8 SpeedDuplex; // speed/duplex
eFLOW_CONTROL_t RegistryFlowControl; // for 802.3x flow control
u8 RegistryWOLMatch; // Enable WOL pattern-matching
u8 RegistryWOLLink; // Link state change is independant
u8 RegistryPhyComa; // Phy Coma mode enable/disable
u8 SpeedDuplex; /* speed/duplex */
eFLOW_CONTROL_t RegistryFlowControl; /* for 802.3x flow control */
u8 RegistryWOLMatch; /* Enable WOL pattern-matching */
u8 RegistryWOLLink; /* Link state change is independant */
u8 RegistryPhyComa; /* Phy Coma mode enable/disable */
u32 RegistryRxMemEnd; // Size of internal rx memory
u8 RegistryMACStat; // If set, read MACSTAT, else don't
u32 RegistryVlanTag; // 802.1q Vlan TAG
u32 RegistryJumboPacket; // Max supported ethernet packet size
u32 RegistryRxMemEnd; /* Size of internal rx memory */
u8 RegistryMACStat; /* If set, read MACSTAT, else don't */
u32 RegistryVlanTag; /* 802.1q Vlan TAG */
u32 RegistryJumboPacket; /* Max supported ethernet packet size */
u32 RegistryTxNumBuffers;
u32 RegistryTxTimeInterval;
@@ -290,12 +290,12 @@ struct et131x_adapter {
u8 RegistryNMIDisable;
u32 RegistryDMACache;
u32 RegistrySCGain;
u8 RegistryPhyLoopbk; // Enable Phy loopback
u8 RegistryPhyLoopbk; /* Enable Phy loopback */
/* Derived from the registry: */
u8 AiForceDpx; // duplex setting
u16 AiForceSpeed; // 'Speed', user over-ride of line speed
eFLOW_CONTROL_t FlowControl; // flow control validated by the far-end
u8 AiForceDpx; /* duplex setting */
u16 AiForceSpeed; /* 'Speed', user over-ride of line speed */
eFLOW_CONTROL_t FlowControl; /* flow control validated by the far-end */
enum {
NETIF_STATUS_INVALID = 0,
NETIF_STATUS_MEDIA_CONNECT,
@@ -313,7 +313,7 @@ struct et131x_adapter {
MP_POWER_MGMT PoMgmt;
INTERRUPT_t CachedMaskValue;
atomic_t RcvRefCount; // Num packets not yet returned
atomic_t RcvRefCount; /* Num packets not yet returned */
/* Xcvr status at last poll */
MI_BMSR_t Bmsr;
@@ -329,8 +329,8 @@ struct et131x_adapter {
PCI_CFG_SPACE_REGS PciCfgRegs;
/* Loopback specifics */
u8 ReplicaPhyLoopbk; // Replica Enable
u8 ReplicaPhyLoopbkPF; // Replica Enable Pass/Fail
u8 ReplicaPhyLoopbk; /* Replica Enable */
u8 ReplicaPhyLoopbkPF; /* Replica Enable Pass/Fail */
/* Stats */
CE_STATS_t Stats;
drivers/staging/et131x/et131x_config.c
+18 -20
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -74,9 +74,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -198,7 +198,7 @@ MODULE_PARM_DESC(et131x_nmi_disable, "Disable NMI (0-2) [0]");
static u32 et131x_speed_set = PARM_SPEED_DUPLEX_DEF;
module_param(et131x_speed_set, uint, 0);
MODULE_PARM_DESC(et131x_speed_set,
"Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
"Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
/**
* et131x_config_parse
@@ -242,7 +242,7 @@ void et131x_config_parse(struct et131x_adapter *pAdapter)
pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
}
// pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
/* pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF; */
pAdapter->RegistryVlanTag = PARM_VLAN_TAG_DEF;
pAdapter->RegistryFlowControl = PARM_FLOW_CTL_DEF;
@@ -259,11 +259,10 @@ void et131x_config_parse(struct et131x_adapter *pAdapter)
pAdapter->RegistrySCGain = PARM_SC_GAIN_DEF;
pAdapter->RegistryPMWOL = PARM_PM_WOL_DEF;
if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF) {
if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF)
pAdapter->RegistryNMIDisable = et131x_nmi_disable;
} else {
else
pAdapter->RegistryNMIDisable = PARM_NMI_DISABLE_DEF;
}
pAdapter->RegistryDMACache = PARM_DMA_CACHE_DEF;
pAdapter->RegistryPhyLoopbk = PARM_PHY_LOOPBK_DEF;
@@ -283,39 +282,38 @@ void et131x_config_parse(struct et131x_adapter *pAdapter)
* Set up as if we are auto negotiating always and then change if we
* go into force mode
*/
pAdapter->AiForceSpeed = 0; // Auto speed
pAdapter->AiForceDpx = 0; // Auto FDX
pAdapter->AiForceSpeed = 0; /* Auto speed */
pAdapter->AiForceDpx = 0; /* Auto FDX */
/* If we are the 10/100 device, and gigabit is somehow requested then
* knock it down to 100 full.
*/
if ((pAdapter->DeviceID == ET131X_PCI_DEVICE_ID_FAST) &&
(pAdapter->SpeedDuplex == 5)) {
if (pAdapter->DeviceID == ET131X_PCI_DEVICE_ID_FAST &&
pAdapter->SpeedDuplex == 5)
pAdapter->SpeedDuplex = 4;
}
switch (pAdapter->SpeedDuplex) {
case 1: // 10Mb Half-Duplex
case 1: /* 10Mb Half-Duplex */
pAdapter->AiForceSpeed = 10;
pAdapter->AiForceDpx = 1;
break;
case 2: // 10Mb Full-Duplex
case 2: /* 10Mb Full-Duplex */
pAdapter->AiForceSpeed = 10;
pAdapter->AiForceDpx = 2;
break;
case 3: // 100Mb Half-Duplex
case 3: /* 100Mb Half-Duplex */
pAdapter->AiForceSpeed = 100;
pAdapter->AiForceDpx = 1;
break;
case 4: // 100Mb Full-Duplex
case 4: /* 100Mb Full-Duplex */
pAdapter->AiForceSpeed = 100;
pAdapter->AiForceDpx = 2;
break;
case 5: // 1000Mb Full-Duplex
case 5: /* 1000Mb Full-Duplex */
pAdapter->AiForceSpeed = 1000;
pAdapter->AiForceDpx = 2;
break;
drivers/staging/et131x/et131x_debug.c
+6 -6
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -19,7 +19,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -40,7 +40,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -76,9 +76,9 @@
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -214,4 +214,4 @@ void DumpDeviceReg(int dbgLvl, struct et131x_adapter *pAdapter)
}
}
#endif // CONFIG_ET131X_DEBUG
#endif /* CONFIG_ET131X_DEBUG */
drivers/staging/et131x/et131x_debug.h
+12 -12
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -21,7 +21,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -42,7 +42,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -97,7 +97,7 @@
#endif /* DBG_PRINTC */
#ifndef DBG_TRAP
#define DBG_TRAP {} /* BUG() */
#define DBG_TRAP do {} while (0) /* BUG() */
#endif /* DBG_TRAP */
#define _ENTER_STR ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>"
@@ -227,16 +227,16 @@ typedef struct {
#define DBG_PRINT(S...)
#define DBG_ENTER(A)
#define DBG_LEAVE(A)
#define DBG_PARAM(A,N,F,S...)
#define DBG_ERROR(A,S...)
#define DBG_WARNING(A,S...)
#define DBG_NOTICE(A,S...)
#define DBG_TRACE(A,S...)
#define DBG_VERBOSE(A,S...)
#define DBG_RX(A,S...)
#define DBG_PARAM(A, N, F, S...)
#define DBG_ERROR(A, S...)
#define DBG_WARNING(A, S...)
#define DBG_NOTICE(A, S...)
#define DBG_TRACE(A, S...)
#define DBG_VERBOSE(A, S...)
#define DBG_RX(A, S...)
#define DBG_RX_ENTER(A)
#define DBG_RX_LEAVE(A)
#define DBG_TX(A,S...)
#define DBG_TX(A, S...)
#define DBG_TX_ENTER(A)
#define DBG_TX_LEAVE(A)
#define DBG_ASSERT(C)
drivers/staging/et131x/et131x_defs.h
+6 -6
View File
@@ -2,7 +2,7 @@
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
@@ -20,7 +20,7 @@
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
@@ -41,7 +41,7 @@
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
@@ -118,9 +118,9 @@
#define ET1310_PCI_ADVANCED_ERR 0x100
/* PCI Vendor/Product IDs */
#define ET131X_PCI_VENDOR_ID 0x11C1 // Agere Systems
#define ET131X_PCI_DEVICE_ID_GIG 0xED00 // ET1310 1000 Base-T
#define ET131X_PCI_DEVICE_ID_FAST 0xED01 // ET1310 100 Base-T
#define ET131X_PCI_VENDOR_ID 0x11C1 /* Agere Systems */
#define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
#define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
/* Define order of magnitude converter */
#define NANO_IN_A_MICRO 1000

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