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drm/nouveau/pwr: implement a simple i2c stack
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
@@ -0,0 +1,393 @@
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/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define T_TIMEOUT 2200000
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#define T_RISEFALL 1000
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#define T_HOLD 5000
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#ifdef INCLUDE_PROC
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process(PROC_I2C_, #i2c_init, #i2c_recv)
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#endif
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/******************************************************************************
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* I2C_ data segment
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*****************************************************************************/
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#ifdef INCLUDE_DATA
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i2c_scl_map:
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.b32 NV_PPWR_OUTPUT_I2C_0_SCL
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.b32 NV_PPWR_OUTPUT_I2C_1_SCL
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.b32 NV_PPWR_OUTPUT_I2C_2_SCL
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.b32 NV_PPWR_OUTPUT_I2C_3_SCL
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.b32 NV_PPWR_OUTPUT_I2C_4_SCL
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.b32 NV_PPWR_OUTPUT_I2C_5_SCL
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.b32 NV_PPWR_OUTPUT_I2C_6_SCL
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.b32 NV_PPWR_OUTPUT_I2C_7_SCL
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.b32 NV_PPWR_OUTPUT_I2C_8_SCL
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.b32 NV_PPWR_OUTPUT_I2C_9_SCL
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i2c_sda_map:
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.b32 NV_PPWR_OUTPUT_I2C_0_SDA
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.b32 NV_PPWR_OUTPUT_I2C_1_SDA
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.b32 NV_PPWR_OUTPUT_I2C_2_SDA
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.b32 NV_PPWR_OUTPUT_I2C_3_SDA
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.b32 NV_PPWR_OUTPUT_I2C_4_SDA
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.b32 NV_PPWR_OUTPUT_I2C_5_SDA
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.b32 NV_PPWR_OUTPUT_I2C_6_SDA
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.b32 NV_PPWR_OUTPUT_I2C_7_SDA
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.b32 NV_PPWR_OUTPUT_I2C_8_SDA
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.b32 NV_PPWR_OUTPUT_I2C_9_SDA
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#if NVKM_PPWR_CHIPSET < GF119
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i2c_ctrl:
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.b32 0x00e138
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.b32 0x00e150
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.b32 0x00e168
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.b32 0x00e180
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.b32 0x00e254
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.b32 0x00e274
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.b32 0x00e764
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.b32 0x00e780
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.b32 0x00e79c
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.b32 0x00e7b8
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#endif
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#endif
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/******************************************************************************
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* I2C_ code segment
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*****************************************************************************/
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#ifdef INCLUDE_CODE
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// $r3 - value
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// $r2 - sda line
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// $r1 - scl line
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// $r0 - zero
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i2c_drive_scl:
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cmp b32 $r3 0
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bra e #i2c_drive_scl_lo
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nv_iowr(NV_PPWR_OUTPUT_SET, $r1)
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ret
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i2c_drive_scl_lo:
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nv_iowr(NV_PPWR_OUTPUT_CLR, $r1)
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ret
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i2c_drive_sda:
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cmp b32 $r3 0
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bra e #i2c_drive_sda_lo
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nv_iowr(NV_PPWR_OUTPUT_SET, $r2)
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ret
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i2c_drive_sda_lo:
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nv_iowr(NV_PPWR_OUTPUT_CLR, $r2)
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ret
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i2c_sense_scl:
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bclr $flags $p1
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nv_iord($r3, NV_PPWR_INPUT)
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and $r3 $r1
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bra z #i2c_sense_scl_done
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bset $flags $p1
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i2c_sense_scl_done:
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ret
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i2c_sense_sda:
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bclr $flags $p1
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nv_iord($r3, NV_PPWR_INPUT)
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and $r3 $r2
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bra z #i2c_sense_sda_done
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bset $flags $p1
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i2c_sense_sda_done:
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ret
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#define i2c_drive_scl(v) /*
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*/ mov $r3 (v) /*
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*/ call(i2c_drive_scl)
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#define i2c_drive_sda(v) /*
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*/ mov $r3 (v) /*
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*/ call(i2c_drive_sda)
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#define i2c_sense_scl() /*
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*/ call(i2c_sense_scl)
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#define i2c_sense_sda() /*
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*/ call(i2c_sense_sda)
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#define i2c_delay(v) /*
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*/ mov $r14 (v) /*
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*/ call(nsec)
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#define i2c_trace_init() /*
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*/ imm32($r6, 0x10000000) /*
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*/ sub b32 $r7 $r6 1 /*
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*/
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#define i2c_trace_down() /*
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*/ shr b32 $r6 4 /*
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*/ push $r5 /*
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*/ shl b32 $r5 $r6 4 /*
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*/ sub b32 $r5 $r6 /*
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*/ not b32 $r5 /*
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*/ and $r7 $r5 /*
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*/ pop $r5 /*
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*/
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#define i2c_trace_exit() /*
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*/ shl b32 $r6 4 /*
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*/
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#define i2c_trace_next() /*
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*/ add b32 $r7 $r6 /*
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*/
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#define i2c_trace_call(func) /*
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*/ i2c_trace_next() /*
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*/ i2c_trace_down() /*
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*/ call(func) /*
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*/ i2c_trace_exit() /*
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*/
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i2c_raise_scl:
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push $r4
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mov $r4 (T_TIMEOUT / T_RISEFALL)
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i2c_drive_scl(1)
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i2c_raise_scl_wait:
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i2c_delay(T_RISEFALL)
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i2c_sense_scl()
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bra $p1 #i2c_raise_scl_done
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sub b32 $r4 1
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bra nz #i2c_raise_scl_wait
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i2c_raise_scl_done:
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pop $r4
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ret
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i2c_start:
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i2c_sense_scl()
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bra not $p1 #i2c_start_rep
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i2c_sense_sda()
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bra not $p1 #i2c_start_rep
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bra #i2c_start_send
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i2c_start_rep:
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i2c_drive_scl(0)
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i2c_drive_sda(1)
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i2c_trace_call(i2c_raise_scl)
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bra not $p1 #i2c_start_out
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i2c_start_send:
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i2c_drive_sda(0)
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i2c_delay(T_HOLD)
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i2c_drive_scl(0)
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i2c_delay(T_HOLD)
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i2c_start_out:
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ret
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i2c_stop:
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i2c_drive_scl(0)
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i2c_drive_sda(0)
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i2c_delay(T_RISEFALL)
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i2c_drive_scl(1)
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i2c_delay(T_HOLD)
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i2c_drive_sda(1)
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i2c_delay(T_HOLD)
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ret
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// $r3 - value
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// $r2 - sda line
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// $r1 - scl line
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// $r0 - zero
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i2c_bitw:
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call(i2c_drive_sda)
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i2c_delay(T_RISEFALL)
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i2c_trace_call(i2c_raise_scl)
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bra not $p1 #i2c_bitw_out
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i2c_delay(T_HOLD)
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i2c_drive_scl(0)
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i2c_delay(T_HOLD)
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i2c_bitw_out:
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ret
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// $r3 - value (out)
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// $r2 - sda line
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// $r1 - scl line
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// $r0 - zero
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i2c_bitr:
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i2c_drive_sda(1)
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i2c_delay(T_RISEFALL)
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i2c_trace_call(i2c_raise_scl)
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bra not $p1 #i2c_bitr_done
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i2c_sense_sda()
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i2c_drive_scl(0)
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i2c_delay(T_HOLD)
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xbit $r3 $flags $p1
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bset $flags $p1
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i2c_bitr_done:
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ret
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i2c_get_byte:
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mov $r5 0
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mov $r4 8
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i2c_get_byte_next:
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shl b32 $r5 1
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i2c_trace_call(i2c_bitr)
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bra not $p1 #i2c_get_byte_done
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or $r5 $r3
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sub b32 $r4 1
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bra nz #i2c_get_byte_next
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mov $r3 1
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i2c_trace_call(i2c_bitw)
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i2c_get_byte_done:
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ret
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i2c_put_byte:
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mov $r4 8
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i2c_put_byte_next:
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sub b32 $r4 1
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xbit $r3 $r5 $r4
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i2c_trace_call(i2c_bitw)
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bra not $p1 #i2c_put_byte_done
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cmp b32 $r4 0
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bra ne #i2c_put_byte_next
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i2c_trace_call(i2c_bitr)
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bra not $p1 #i2c_put_byte_done
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i2c_trace_next()
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cmp b32 $r3 1
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bra ne #i2c_put_byte_done
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bclr $flags $p1 // nack
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i2c_put_byte_done:
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ret
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i2c_addr:
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i2c_trace_call(i2c_start)
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bra not $p1 #i2c_addr_done
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extr $r3 $r12 I2C__MSG_DATA0_ADDR
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shl b32 $r3 1
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or $r5 $r3
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i2c_trace_call(i2c_put_byte)
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i2c_addr_done:
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ret
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i2c_acquire_addr:
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extr $r14 $r12 I2C__MSG_DATA0_PORT
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#if NVKM_PPWR_CHIPSET < GF119
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shl b32 $r14 2
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add b32 $r14 #i2c_ctrl
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ld b32 $r14 D[$r14]
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#else
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shl b32 $r14 5
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add b32 $r14 0x00d014
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#endif
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ret
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i2c_acquire:
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call(i2c_acquire_addr)
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call(rd32)
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bset $r13 3
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call(wr32)
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ret
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i2c_release:
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call(i2c_acquire_addr)
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call(rd32)
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bclr $r13 3
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call(wr32)
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ret
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// description
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//
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// $r15 - current (i2c)
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// $r14 - sender process name
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// $r13 - message
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// $r12 - data0
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// $r11 - data1
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// $r0 - zero
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i2c_recv:
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bclr $flags $p1
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extr $r1 $r12 I2C__MSG_DATA0_PORT
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shl b32 $r1 2
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cmp b32 $r1 (#i2c_sda_map - #i2c_scl_map)
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bra ge #i2c_recv_done
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add b32 $r3 $r1 #i2c_sda_map
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ld b32 $r2 D[$r3]
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add b32 $r3 $r1 #i2c_scl_map
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ld b32 $r1 D[$r3]
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bset $flags $p2
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push $r13
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push $r14
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push $r13
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i2c_trace_init()
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i2c_trace_call(i2c_acquire)
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pop $r13
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cmp b32 $r13 I2C__MSG_RD08
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bra ne #i2c_recv_not_rd08
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mov $r5 0
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i2c_trace_call(i2c_addr)
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bra not $p1 #i2c_recv_done
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extr $r5 $r12 I2C__MSG_DATA0_RD08_REG
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i2c_trace_call(i2c_put_byte)
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bra not $p1 #i2c_recv_done
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mov $r5 1
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i2c_trace_call(i2c_addr)
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bra not $p1 #i2c_recv_done
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i2c_trace_call(i2c_get_byte)
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bra not $p1 #i2c_recv_done
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ins $r11 $r5 I2C__MSG_DATA1_RD08_VAL
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i2c_trace_call(i2c_stop)
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mov b32 $r11 $r5
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clear b32 $r7
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bra #i2c_recv_done
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i2c_recv_not_rd08:
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cmp b32 $r13 I2C__MSG_WR08
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bra ne #i2c_recv_not_wr08
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mov $r5 0
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call(i2c_addr)
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bra not $p1 #i2c_recv_done
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extr $r5 $r12 I2C__MSG_DATA0_WR08_REG
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call(i2c_put_byte)
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bra not $p1 #i2c_recv_done
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mov $r5 0
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call(i2c_addr)
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bra not $p1 #i2c_recv_done
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extr $r5 $r11 I2C__MSG_DATA1_WR08_VAL
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call(i2c_put_byte)
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bra not $p1 #i2c_recv_done
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call(i2c_stop)
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clear b32 $r7
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extr $r5 $r12 I2C__MSG_DATA0_WR08_SYNC
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bra nz #i2c_recv_done
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bclr $flags $p2
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bra #i2c_recv_done
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i2c_recv_not_wr08:
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i2c_recv_done:
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extr $r14 $r12 I2C__MSG_DATA0_PORT
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call(i2c_release)
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pop $r14
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pop $r13
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bra not $p2 #i2c_recv_exit
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mov b32 $r12 $r7
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call(send)
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||||
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||||
i2c_recv_exit:
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ret
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||||
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// description
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||||
//
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||||
// $r15 - current (i2c)
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// $r0 - zero
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i2c_init:
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ret
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#endif
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@@ -83,6 +83,50 @@
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#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002
|
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#define NV_PPWR_OUTPUT 0x07c0
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#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004
|
||||
#if NVKM_PPWR_CHIPSET < GF119
|
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#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100
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#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200
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#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000
|
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#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000
|
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#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000
|
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#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000
|
||||
#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000
|
||||
#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000
|
||||
#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000
|
||||
#define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000
|
||||
#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000
|
||||
#define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000
|
||||
#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000
|
||||
#define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000
|
||||
#define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000
|
||||
#define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000
|
||||
#define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000
|
||||
#define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000
|
||||
#define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000
|
||||
#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
|
||||
#else
|
||||
#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400
|
||||
#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800
|
||||
#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000
|
||||
#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000
|
||||
#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000
|
||||
#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000
|
||||
#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000
|
||||
#define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000
|
||||
#define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000
|
||||
#define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000
|
||||
#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000
|
||||
#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000
|
||||
#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000
|
||||
#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000
|
||||
#define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000
|
||||
#define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000
|
||||
#define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000
|
||||
#define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000
|
||||
#define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000
|
||||
#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000
|
||||
#endif
|
||||
#define NV_PPWR_INPUT 0x07c4
|
||||
#define NV_PPWR_OUTPUT_SET 0x07e0
|
||||
#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004
|
||||
#define NV_PPWR_OUTPUT_CLR 0x07e4
|
||||
@@ -125,6 +169,15 @@
|
||||
*/ .b32 0 /*
|
||||
*/ .skip 64
|
||||
|
||||
#if NV_PPWR_CHIPSET < GK208
|
||||
#define imm32(reg,val) /*
|
||||
*/ movw reg ((val) & 0x0000ffff) /*
|
||||
*/ sethi reg ((val) & 0xffff0000)
|
||||
#else
|
||||
#define imm32(reg,val) /*
|
||||
*/ mov reg (val)
|
||||
#endif
|
||||
|
||||
#ifndef NVKM_FALCON_UNSHIFTED_IO
|
||||
#define nv_iord(reg,ior) /*
|
||||
*/ mov reg ior /*
|
||||
|
||||
@@ -37,6 +37,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_PROC
|
||||
@@ -46,6 +47,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_DATA
|
||||
@@ -57,6 +59,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_CODE
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -37,6 +37,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_PROC
|
||||
@@ -46,6 +47,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_DATA
|
||||
@@ -57,6 +59,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_CODE
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -37,6 +37,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_PROC
|
||||
@@ -46,6 +47,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_DATA
|
||||
@@ -57,6 +59,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_CODE
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -37,6 +37,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_PROC
|
||||
@@ -46,6 +47,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_DATA
|
||||
@@ -57,6 +59,7 @@
|
||||
#include "host.fuc"
|
||||
#include "memx.fuc"
|
||||
#include "perf.fuc"
|
||||
#include "i2c_.fuc"
|
||||
#include "test.fuc"
|
||||
#include "idle.fuc"
|
||||
#undef INCLUDE_CODE
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -7,6 +7,7 @@
|
||||
#define PROC_HOST 0x54534f48
|
||||
#define PROC_MEMX 0x584d454d
|
||||
#define PROC_PERF 0x46524550
|
||||
#define PROC_I2C_ 0x5f433249
|
||||
#define PROC_TEST 0x54534554
|
||||
|
||||
/* KERN: message identifiers */
|
||||
@@ -24,4 +25,22 @@
|
||||
#define MEMX_WAIT 3
|
||||
#define MEMX_DELAY 4
|
||||
|
||||
/* I2C_: message identifiers */
|
||||
#define I2C__MSG_RD08 0
|
||||
#define I2C__MSG_WR08 1
|
||||
|
||||
#define I2C__MSG_DATA0_PORT 24:31
|
||||
#define I2C__MSG_DATA0_ADDR 14:23
|
||||
|
||||
#define I2C__MSG_DATA0_RD08_PORT I2C__MSG_DATA0_PORT
|
||||
#define I2C__MSG_DATA0_RD08_ADDR I2C__MSG_DATA0_ADDR
|
||||
#define I2C__MSG_DATA0_RD08_REG 0:7
|
||||
#define I2C__MSG_DATA1_RD08_VAL 0:7
|
||||
|
||||
#define I2C__MSG_DATA0_WR08_PORT I2C__MSG_DATA0_PORT
|
||||
#define I2C__MSG_DATA0_WR08_ADDR I2C__MSG_DATA0_ADDR
|
||||
#define I2C__MSG_DATA0_WR08_SYNC 8:8
|
||||
#define I2C__MSG_DATA0_WR08_REG 0:7
|
||||
#define I2C__MSG_DATA1_WR08_VAL 0:7
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user