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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net into net

Browse Source 
Pull in 'net' to take in the bug fixes that didn't make it into
3.8-final.

Also, deal with the semantic conflict of the change made to
net/ipv6/xfrm6_policy.c   A missing rt6->n neighbour release
was added to 'net', but in 'net-next' we no longer cache the
neighbour entries in the ipv6 routes so that change is not
appropriate there.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2013-02-18 23:32:49 -05:00
parent 8064b3cf75 18cf0d0784
commit 6338a53a2b
60 changed files with 753 additions and 627 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/x86/boot.txt
+1
View File
@@ -390,6 +390,7 @@ Protocol: 2.00+
F Special (0xFF = undefined)
10 Reserved
11 Minimal Linux Bootloader <http://sebastian-plotz.blogspot.de>
12 OVMF UEFI virtualization stack
Please contact <hpa@zytor.com> if you need a bootloader ID
value assigned.
MAINTAINERS
+1 -1
View File
@@ -7524,7 +7524,7 @@ S: Maintained
F: drivers/media/tuners/tea5767.*
TEAM DRIVER
M: Jiri Pirko <jpirko@redhat.com>
M: Jiri Pirko <jiri@resnulli.us>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/team/
arch/arm/include/asm/smp_scu.h
+7 -1
View File
@@ -7,8 +7,14 @@
#ifndef __ASSEMBLER__
unsigned int scu_get_core_count(void __iomem *);
void scu_enable(void __iomem *);
int scu_power_mode(void __iomem *, unsigned int);
#ifdef CONFIG_SMP
void scu_enable(void __iomem *scu_base);
#else
static inline void scu_enable(void __iomem *scu_base) {}
#endif
#endif
#endif
arch/arm/kernel/smp_scu.c
+1 -1
View File
@@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
{
unsigned int val;
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
arch/arm/mach-highbank/highbank.c
+2 -1
View File
@@ -28,6 +28,7 @@
#include <asm/arch_timer.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/smp_plat.h>
#include <asm/smp_twd.h>
#include <asm/hardware/arm_timer.h>
@@ -59,7 +60,7 @@ static void __init highbank_scu_map_io(void)
void highbank_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
arch/arm/mach-highbank/sysregs.h
+2 -2
View File
@@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
static inline void highbank_set_core_pwr(void)
{
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
else
@@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
static inline void highbank_clear_core_pwr(void)
{
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
else
arch/arm/net/bpf_jit_32.c
+11 -4
View File
@@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
{
emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
/* r_dst = (r_src << 8) | (r_src >> 8) */
emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
/*
* we need to mask out the bits set in r_dst[23:16] due to
* the first shift instruction.
*
* note that 0x8ff is the encoded immediate 0x00ff0000.
*/
emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
}
#else /* ARMv6+ */
arch/m68k/include/asm/processor.h
-1
View File
@@ -130,7 +130,6 @@ extern int handle_kernel_fault(struct pt_regs *regs);
#define start_thread(_regs, _pc, _usp) \
do { \
(_regs)->pc = (_pc); \
((struct switch_stack *)(_regs))[-1].a6 = 0; \
setframeformat(_regs); \
if (current->mm) \
(_regs)->d5 = current->mm->start_data; \
arch/s390/kernel/time.c
+3
View File
@@ -120,6 +120,9 @@ static int s390_next_ktime(ktime_t expires,
nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
do_div(nsecs, 125);
S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
/* Program the maximum value if we have an overflow (== year 2042) */
if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc))
S390_lowcore.clock_comparator = -1ULL;
set_clock_comparator(S390_lowcore.clock_comparator);
return 0;
}
arch/tile/Kconfig
+2
View File
@@ -140,6 +140,8 @@ config ARCH_DEFCONFIG
source "init/Kconfig"
source "kernel/Kconfig.freezer"
menu "Tilera-specific configuration"
config NR_CPUS
arch/tile/include/asm/io.h
+5 -1
View File
@@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr)
#define iowrite32 writel
#define iowrite64 writeq
static inline void memset_io(void *dst, int val, size_t len)
#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
static inline void memset_io(volatile void *dst, int val, size_t len)
{
int x;
BUG_ON((unsigned long)dst & 0x3);
@@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
writel(*(u32 *)(src + x), dst + x);
}
#endif
/*
* The Tile architecture does not support IOPORT, even with PCI.
* Unfortunately we can't yet simply not declare these methods,
arch/tile/include/asm/irqflags.h
+10 -22
View File
@@ -18,32 +18,20 @@
#include <arch/interrupts.h>
#include <arch/chip.h>
#if !defined(__tilegx__) && defined(__ASSEMBLY__)
/*
* The set of interrupts we want to allow when interrupts are nominally
* disabled. The remainder are effectively "NMI" interrupts from
* the point of view of the generic Linux code. Note that synchronous
* interrupts (aka "non-queued") are not blocked by the mask in any case.
*/
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT)))
#endif
#else
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT)))
#endif
(~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
#if CHIP_HAS_SPLIT_INTR_MASK()
/* The same macro, but for the two 32-bit SPRs separately. */
#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
#endif
#ifndef __ASSEMBLY__
@@ -126,7 +114,7 @@
* to know our current state.
*/
DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
/* Disable interrupts. */
#define arch_local_irq_disable() \
@@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Prevent the given interrupt from being enabled next time we enable irqs. */
#define arch_local_irq_mask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
/* Prevent the given interrupt from being enabled immediately. */
#define arch_local_irq_mask_now(interrupt) do { \
@@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Allow the given interrupt to be enabled next time we enable irqs. */
#define arch_local_irq_unmask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
#define arch_local_irq_unmask_now(interrupt) do { \
@@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Disable interrupts. */
#define IRQ_DISABLE(tmp0, tmp1) \
{ \
movei tmp0, -1; \
movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
}; \
{ \
arch/tile/include/uapi/arch/interrupts_32.h
+198 -196
View File
@@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
/* Note: must handle breaking interrupts into high and low words manually. */
#define INT_MASK_LO(intno) (1 << (intno))
@@ -23,6 +24,7 @@
#ifndef __ASSEMBLER__
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@@ -92,216 +94,216 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */
arch/tile/include/uapi/arch/interrupts_64.h
+174 -172
View File
@@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
#ifdef __ASSEMBLER__
/* Note: must handle breaking interrupts into high and low words manually. */
@@ -22,6 +23,7 @@
#else
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@@ -85,192 +87,192 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */
arch/tile/kernel/intvec_64.S
+4
View File
@@ -1035,7 +1035,9 @@ handle_syscall:
/* Ensure that the syscall number is within the legal range. */
{
moveli r20, hw2(sys_call_table)
#ifdef CONFIG_COMPAT
blbs r30, .Lcompat_syscall
#endif
}
{
cmpltu r21, TREG_SYSCALL_NR_NAME, r21
@@ -1093,6 +1095,7 @@ handle_syscall:
j .Lresume_userspace /* jump into middle of interrupt_return */
}
#ifdef CONFIG_COMPAT
.Lcompat_syscall:
/*
* Load the base of the compat syscall table in r20, and
@@ -1117,6 +1120,7 @@ handle_syscall:
{ move r15, r4; addxi r4, r4, 0 }
{ move r16, r5; addxi r5, r5, 0 }
j .Lload_syscall_pointer
#endif
.Linvalid_syscall:
/* Report an invalid syscall back to the user program */
arch/tile/kernel/process.c
+1 -1
View File
@@ -159,7 +159,7 @@ static void save_arch_state(struct thread_struct *t);
int copy_thread(unsigned long clone_flags, unsigned long sp,
unsigned long arg, struct task_struct *p)
{
struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs();
struct pt_regs *childregs = task_pt_regs(p);
unsigned long ksp;
unsigned long *callee_regs;
arch/tile/kernel/reboot.c
+2
View File
@@ -16,6 +16,7 @@
#include <linux/reboot.h>
#include <linux/smp.h>
#include <linux/pm.h>
#include <linux/export.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <hv/hypervisor.h>
@@ -49,3 +50,4 @@ void machine_restart(char *cmd)
/* No interesting distinction to be made here. */
void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);
arch/tile/kernel/setup.c
+5
View File
@@ -31,6 +31,7 @@
#include <linux/timex.h>
#include <linux/hugetlb.h>
#include <linux/start_kernel.h>
#include <linux/screen_info.h>
#include <asm/setup.h>
#include <asm/sections.h>
#include <asm/cacheflush.h>
@@ -49,6 +50,10 @@ static inline int ABS(int x) { return x >= 0 ? x : -x; }
/* Chip information */
char chip_model[64] __write_once;
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
EXPORT_SYMBOL(node_data);
arch/tile/kernel/stack.c
+2 -1
View File
@@ -112,7 +112,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
p->pc, p->sp, p->ex1);
p = NULL;
}
if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0)
if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0)
return p;
return NULL;
}
@@ -484,6 +484,7 @@ void save_stack_trace(struct stack_trace *trace)
{
save_stack_trace_tsk(NULL, trace);
}
EXPORT_SYMBOL_GPL(save_stack_trace);
#endif
arch/tile/lib/cacheflush.c
+2
View File
@@ -12,6 +12,7 @@
* more details.
*/
#include <linux/export.h>
#include <asm/page.h>
#include <asm/cacheflush.h>
#include <arch/icache.h>
@@ -165,3 +166,4 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
__insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
#endif
}
EXPORT_SYMBOL_GPL(finv_buffer_remote);

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