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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson: "This is the first release where we split up the 64-bit contributions a bit more, and in particular we are having a separate DT branch for them. Contents: - New devices added to Broadcom NorthStar2 - Misc fixes for Exynos7 boards - QCOM updates for MSM8916 - Rockchip tweaks for rk3368 SoC and eval board - A series of fixes for APM X-Gene v1 and v2 - Renesas R8A7795 CPU/PSCI additions - Marvell Berlin4CT PSCI, cpuidle, watchdog portions - Freescale LS1043a SoC and dev board support + some treewide or other misc changes" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits) dts/ls2080a: Update DTSI to add support of SP805 WDT Documentation: DT: Add entry for ARM SP805-WDT arm64: dts: X-Gene v2: I2C1 clock is always on arm64: dts: X-Gene v1: I2C0 clock is always on arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms arm64: dts: hikey: add label properties to UARTs arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI arm64: dts: apq8016-sbc: enable UART0 on LS connector arm64: dts: juno: Add idle-states to device tree arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC arm64: dts: add LS1043a-RDB board support arm64: dts: add Freescale LS1043a SoC support Documentation: DT: Add entry for Freescale LS1043a-RDB board arm64: dts: uniphier: add PH1-LD10 SoC/board support arm64: renesas: r8a7795: fix SATA clock assignment arm64: dts: salvator-x: Enable SATA controller arm64: dts: r8a7795: Add SATA controller node arm64: renesas: r8a7795: add internal delay for i2c IPs arm64: renesas: salvator-x: Add board part number to DT bindings arm64: dts: r8a7795: Add pmu device nodes ...
This commit is contained in:
Linus Torvalds
@@ -131,6 +131,10 @@ Example:
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Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
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----------------------------------------------------------------
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|
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LS1043A ARMv8 based RDB Board
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Required root node properties:
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- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
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LS2080A ARMv8 based Simulator model
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Required root node properties:
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- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
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@@ -87,6 +87,10 @@ Rockchip platforms device tree bindings
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"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
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"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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- Rockchip RK3368 evb:
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Required root node properties:
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- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
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- Rockchip R88 board:
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Required root node properties:
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- compatible = "rockchip,r88", "rockchip,rk3368";
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@@ -27,6 +27,8 @@ SoCs:
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compatible = "renesas,r8a7793"
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- R-Car E2 (R8A77940)
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compatible = "renesas,r8a7794"
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- R-Car H3 (R8A77950)
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compatible = "renesas,r8a7795"
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Boards:
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@@ -57,5 +59,7 @@ Boards:
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compatible = "renesas,marzen", "renesas,r8a7779"
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- Porter (M2-LCDP)
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compatible = "renesas,porter", "renesas,r8a7791"
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- Salvator-X (RTP0RC7795SIPB0010S)
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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@@ -0,0 +1,31 @@
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* ARM SP805 Watchdog Timer (WDT) Controller
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SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
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can be used to identify the peripheral type, vendor, and revision.
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This value can be used for driver matching.
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As SP805 WDT is a primecell IP, it follows the base bindings specified in
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'arm/primecell.txt'
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Required properties:
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- compatible : Should be "arm,sp805-wdt", "arm,primecell"
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- reg : Base address and size of the watchdog timer registers.
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- clocks : From common clock binding.
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First clock is PCLK and the second is WDOGCLK.
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WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency.
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- clock-names : From common clock binding.
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Shall be "apb_pclk" for first clock and "wdog_clk" for the
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second one.
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Optional properties:
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- interrupts : Should specify WDT interrupt number.
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Examples:
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805-wdt", "arm,primecell";
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reg = <0x0 0xc000000 0x0 0x1000>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "apb_pclk", "wdog_clk";
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};
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+10
@@ -1435,6 +1435,15 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/RENESAS ARM64 ARCHITECTURE
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M: Simon Horman <horms@verge.net.au>
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M: Magnus Damm <magnus.damm@gmail.com>
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L: linux-sh@vger.kernel.org
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Q: http://patchwork.kernel.org/project/linux-sh/list/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
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S: Supported
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F: arch/arm64/boot/dts/renesas/
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ARM/RISCPC ARCHITECTURE
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M: Russell King <linux@arm.linux.org.uk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@@ -1663,6 +1672,7 @@ F: arch/arm/boot/dts/uniphier*
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F: arch/arm/include/asm/hardware/cache-uniphier.h
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F: arch/arm/mach-uniphier/
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F: arch/arm/mm/cache-uniphier.c
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F: arch/arm64/boot/dts/socionext/
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F: drivers/i2c/busses/i2c-uniphier*
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F: drivers/pinctrl/uniphier/
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F: drivers/tty/serial/8250/8250_uniphier.c
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@@ -67,6 +67,23 @@ config ARCH_SEATTLE
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_SHMOBILE
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bool
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select ARCH_SHMOBILE
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select PINCTRL
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select PM_GENERIC_DOMAINS if PM
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_R8A7795
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bool "Renesas R-Car H3 SoC Platform"
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depends on ARCH_RENESAS
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help
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This enables support for the Renesas R-Car H3 SoC.
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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@@ -10,7 +10,9 @@ dts-dirs += hisilicon
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dts-dirs += marvell
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dts-dirs += mediatek
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dts-dirs += qcom
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dts-dirs += renesas
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dts-dirs += rockchip
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dts-dirs += socionext
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dts-dirs += sprd
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dts-dirs += xilinx
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@@ -70,3 +70,15 @@
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&xgenet1 {
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status = "ok"
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};
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&mmc0 {
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status = "ok"
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};
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&i2c4 {
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rtc68: rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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status = "ok"
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};
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};
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@@ -74,3 +74,7 @@
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&xgenet {
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status = "ok"
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};
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&mmc0 {
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status = "ok"
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};
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@@ -25,6 +25,7 @@
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reg = <0x0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_0>;
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};
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cpu@001 {
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device_type = "cpu";
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@@ -32,6 +33,7 @@
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reg = <0x0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_0>;
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};
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cpu@100 {
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device_type = "cpu";
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@@ -39,6 +41,7 @@
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_1>;
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};
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cpu@101 {
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device_type = "cpu";
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@@ -46,6 +49,7 @@
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_1>;
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};
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cpu@200 {
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device_type = "cpu";
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@@ -53,6 +57,7 @@
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_2>;
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};
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cpu@201 {
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device_type = "cpu";
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@@ -60,6 +65,7 @@
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reg = <0x0 0x201>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_2>;
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};
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cpu@300 {
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device_type = "cpu";
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@@ -67,6 +73,7 @@
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_3>;
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};
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cpu@301 {
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device_type = "cpu";
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@@ -74,6 +81,19 @@
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reg = <0x0 0x301>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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next-level-cache = <&xgene_L2_3>;
|
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};
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xgene_L2_0: l2-cache-0 {
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compatible = "cache";
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};
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xgene_L2_1: l2-cache-1 {
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compatible = "cache";
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};
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xgene_L2_2: l2-cache-2 {
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compatible = "cache";
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};
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xgene_L2_3: l2-cache-3 {
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compatible = "cache";
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};
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};
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@@ -89,6 +109,86 @@
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<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
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<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
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<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
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v2m0: v2m@0x00000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x0 0x0 0x1000>;
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};
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v2m1: v2m@0x10000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x10000 0x0 0x1000>;
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};
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v2m2: v2m@0x20000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x20000 0x0 0x1000>;
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};
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v2m3: v2m@0x30000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x30000 0x0 0x1000>;
|
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};
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v2m4: v2m@0x40000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x40000 0x0 0x1000>;
|
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};
|
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v2m5: v2m@0x50000 {
|
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compatible = "arm,gic-v2m-frame";
|
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msi-controller;
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reg = <0x0 0x50000 0x0 0x1000>;
|
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};
|
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v2m6: v2m@0x60000 {
|
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compatible = "arm,gic-v2m-frame";
|
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msi-controller;
|
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reg = <0x0 0x60000 0x0 0x1000>;
|
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};
|
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v2m7: v2m@0x70000 {
|
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compatible = "arm,gic-v2m-frame";
|
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msi-controller;
|
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reg = <0x0 0x70000 0x0 0x1000>;
|
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};
|
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v2m8: v2m@0x80000 {
|
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compatible = "arm,gic-v2m-frame";
|
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msi-controller;
|
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reg = <0x0 0x80000 0x0 0x1000>;
|
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};
|
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v2m9: v2m@0x90000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
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msi-controller;
|
||||
reg = <0x0 0x90000 0x0 0x1000>;
|
||||
};
|
||||
v2m10: v2m@0xA0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xA0000 0x0 0x1000>;
|
||||
};
|
||||
v2m11: v2m@0xB0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xB0000 0x0 0x1000>;
|
||||
};
|
||||
v2m12: v2m@0xC0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xC0000 0x0 0x1000>;
|
||||
};
|
||||
v2m13: v2m@0xD0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xD0000 0x0 0x1000>;
|
||||
};
|
||||
v2m14: v2m@0xE0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xE0000 0x0 0x1000>;
|
||||
};
|
||||
v2m15: v2m@0xF0000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0xF0000 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
@@ -140,6 +240,47 @@
|
||||
clock-output-names = "socplldiv2";
|
||||
};
|
||||
|
||||
ahbclk: ahbclk@17000000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x17000000 0x0 0x2000>;
|
||||
reg-names = "div-reg";
|
||||
divider-offset = <0x164>;
|
||||
divider-width = <0x5>;
|
||||
divider-shift = <0x0>;
|
||||
clock-output-names = "ahbclk";
|
||||
};
|
||||
|
||||
sbapbclk: sbapbclk@1704c000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ahbclk 0>;
|
||||
reg = <0x0 0x1704c000 0x0 0x2000>;
|
||||
reg-names = "div-reg";
|
||||
divider-offset = <0x10>;
|
||||
divider-width = <0x2>;
|
||||
divider-shift = <0x0>;
|
||||
clock-output-names = "sbapbclk";
|
||||
};
|
||||
|
||||
sdioclk: sdioclk@1f2ac000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x1f2ac000 0x0 0x1000
|
||||
0x0 0x17000000 0x0 0x2000>;
|
||||
reg-names = "csr-reg", "div-reg";
|
||||
csr-offset = <0x0>;
|
||||
csr-mask = <0x2>;
|
||||
enable-offset = <0x8>;
|
||||
enable-mask = <0x2>;
|
||||
divider-offset = <0x178>;
|
||||
divider-width = <0x8>;
|
||||
divider-shift = <0x0>;
|
||||
clock-output-names = "sdioclk";
|
||||
};
|
||||
|
||||
pcie0clk: pcie0clk@1f2bc000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
@@ -149,6 +290,15 @@
|
||||
clock-output-names = "pcie0clk";
|
||||
};
|
||||
|
||||
pcie1clk: pcie1clk@1f2cc000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x1f2cc000 0x0 0x1000>;
|
||||
reg-names = "csr-reg";
|
||||
clock-output-names = "pcie1clk";
|
||||
};
|
||||
|
||||
xge0clk: xge0clk@1f61c000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
@@ -170,6 +320,32 @@
|
||||
csr-mask = <0x3>;
|
||||
clock-output-names = "xge1clk";
|
||||
};
|
||||
|
||||
rngpkaclk: rngpkaclk@17000000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x17000000 0x0 0x2000>;
|
||||
reg-names = "csr-reg";
|
||||
csr-offset = <0xc>;
|
||||
csr-mask = <0x10>;
|
||||
enable-offset = <0x10>;
|
||||
enable-mask = <0x10>;
|
||||
clock-output-names = "rngpkaclk";
|
||||
};
|
||||
|
||||
i2c4clk: i2c4clk@1704c000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sbapbclk 0>;
|
||||
reg = <0x0 0x1704c000 0x0 0x1000>;
|
||||
reg-names = "csr-reg";
|
||||
csr-offset = <0x0>;
|
||||
csr-mask = <0x40>;
|
||||
enable-offset = <0x8>;
|
||||
enable-mask = <0x40>;
|
||||
clock-output-names = "i2c4clk";
|
||||
};
|
||||
};
|
||||
|
||||
scu: system-clk-controller@17000000 {
|
||||
@@ -184,6 +360,99 @@
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
csw: csw@7e200000 {
|
||||
compatible = "apm,xgene-csw", "syscon";
|
||||
reg = <0x0 0x7e200000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcba: mcba@7e700000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e700000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
mcbb: mcbb@7e720000 {
|
||||
compatible = "apm,xgene-mcb", "syscon";
|
||||
reg = <0x0 0x7e720000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
efuse: efuse@1054a000 {
|
||||
compatible = "apm,xgene-efuse", "syscon";
|
||||
reg = <0x0 0x1054a000 0x0 0x20>;
|
||||
};
|
||||
|
||||
edac@78800000 {
|
||||
compatible = "apm,xgene-edac";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
regmap-csw = <&csw>;
|
||||
regmap-mcba = <&mcba>;
|
||||
regmap-mcbb = <&mcbb>;
|
||||
regmap-efuse = <&efuse>;
|
||||
reg = <0x0 0x78800000 0x0 0x100>;
|
||||
interrupts = <0x0 0x20 0x4>,
|
||||
<0x0 0x21 0x4>,
|
||||
<0x0 0x27 0x4>;
|
||||
|
||||
edacmc@7e800000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e800000 0x0 0x1000>;
|
||||
memory-controller = <0>;
|
||||
};
|
||||
|
||||
edacmc@7e840000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e840000 0x0 0x1000>;
|
||||
memory-controller = <1>;
|
||||
};
|
||||
|
||||
edacmc@7e880000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e880000 0x0 0x1000>;
|
||||
memory-controller = <2>;
|
||||
};
|
||||
|
||||
edacmc@7e8c0000 {
|
||||
compatible = "apm,xgene-edac-mc";
|
||||
reg = <0x0 0x7e8c0000 0x0 0x1000>;
|
||||
memory-controller = <3>;
|
||||
};
|
||||
|
||||
edacpmd@7c000000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c000000 0x0 0x200000>;
|
||||
pmd-controller = <0>;
|
||||
};
|
||||
|
||||
edacpmd@7c200000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c200000 0x0 0x200000>;
|
||||
pmd-controller = <1>;
|
||||
};
|
||||
|
||||
edacpmd@7c400000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c400000 0x0 0x200000>;
|
||||
pmd-controller = <2>;
|
||||
};
|
||||
|
||||
edacpmd@7c600000 {
|
||||
compatible = "apm,xgene-edac-pmd";
|
||||
reg = <0x0 0x7c600000 0x0 0x200000>;
|
||||
pmd-controller = <3>;
|
||||
};
|
||||
|
||||
edacl3@7e600000 {
|
||||
compatible = "apm,xgene-edac-l3-v2";
|
||||
reg = <0x0 0x7e600000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
edacsoc@7e930000 {
|
||||
compatible = "apm,xgene-edac-soc";
|
||||
reg = <0x0 0x7e930000 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@10600000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
@@ -194,6 +463,66 @@
|
||||
interrupts = <0x0 0x4c 0x4>;
|
||||
};
|
||||
|
||||
/* Do not change dwusb name, coded for backward compatibility */
|
||||
usb0: dwusb@19000000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x19000000 0x0 0x100000>;
|
||||
interrupts = <0x0 0x5d 0x4>;
|
||||
dma-coherent;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
|
||||
0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
msi-parent = <&v2m0>;
|
||||
};
|
||||
|
||||
pcie1: pcie@1f2c0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
|
||||
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
|
||||
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie1clk 0>;
|
||||
msi-parent = <&v2m0>;
|
||||
};
|
||||
|
||||
sata1: sata@1a000000 {
|
||||
compatible = "apm,xgene-ahci";
|
||||
reg = <0x0 0x1a000000 0x0 0x1000>,
|
||||
@@ -224,7 +553,39 @@
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sbgpio: sbgpio@17001000{
|
||||
mmc0: mmc@1c000000 {
|
||||
compatible = "arasan,sdhci-4.9a";
|
||||
reg = <0x0 0x1c000000 0x0 0x100>;
|
||||
interrupts = <0x0 0x49 0x4>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&sdioclk 0>, <&ahbclk 0>;
|
||||
};
|
||||
|
||||
gfcgpio: gpio@1f63c000 {
|
||||
compatible = "apm,xgene-gpio";
|
||||
reg = <0x0 0x1f63c000 0x0 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
dwgpio: gpio@1c024000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x1c024000 0x0 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sbgpio: gpio@17001000{
|
||||
compatible = "apm,xgene-gpio-sb";
|
||||
reg = <0x0 0x17001000 0x0 0x400>;
|
||||
#gpio-cells = <2>;
|
||||
@@ -267,5 +628,33 @@
|
||||
local-mac-address = [00 01 73 00 00 02];
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
rng: rng@10520000 {
|
||||
compatible = "apm,xgene-rng";
|
||||
reg = <0x0 0x10520000 0x0 0x100>;
|
||||
interrupts = <0x0 0x41 0x4>;
|
||||
clocks = <&rngpkaclk 0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@10511000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10511000 0x0 0x1000>;
|
||||
interrupts = <0 0x45 0x4>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&sbapbclk 0>;
|
||||
bus_num = <1>;
|
||||
};
|
||||
|
||||
i2c4: i2c@10640000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10640000 0x0 0x1000>;
|
||||
interrupts = <0 0x3A 0x4>;
|
||||
clocks = <&i2c4clk 0>;
|
||||
bus_num = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -25,6 +25,7 @@
|
||||
reg = <0x0 0x000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_0>;
|
||||
};
|
||||
cpu@001 {
|
||||
device_type = "cpu";
|
||||
@@ -32,6 +33,7 @@
|
||||
reg = <0x0 0x001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_0>;
|
||||
};
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
@@ -39,6 +41,7 @@
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_1>;
|
||||
};
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
@@ -46,6 +49,7 @@
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_1>;
|
||||
};
|
||||
cpu@200 {
|
||||
device_type = "cpu";
|
||||
@@ -53,6 +57,7 @@
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_2>;
|
||||
};
|
||||
cpu@201 {
|
||||
device_type = "cpu";
|
||||
@@ -60,6 +65,7 @@
|
||||
reg = <0x0 0x201>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_2>;
|
||||
};
|
||||
cpu@300 {
|
||||
device_type = "cpu";
|
||||
@@ -67,6 +73,7 @@
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_3>;
|
||||
};
|
||||
cpu@301 {
|
||||
device_type = "cpu";
|
||||
@@ -74,6 +81,19 @@
|
||||
reg = <0x0 0x301>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x1 0x0000fff8>;
|
||||
next-level-cache = <&xgene_L2_3>;
|
||||
};
|
||||
xgene_L2_0: l2-cache-0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
xgene_L2_1: l2-cache-1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
xgene_L2_2: l2-cache-2 {
|
||||
compatible = "cache";
|
||||
};
|
||||
xgene_L2_3: l2-cache-3 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -150,6 +170,35 @@
|
||||
clock-output-names = "socplldiv2";
|
||||
};
|
||||
|
||||
ahbclk: ahbclk@17000000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x17000000 0x0 0x2000>;
|
||||
reg-names = "div-reg";
|
||||
divider-offset = <0x164>;
|
||||
divider-width = <0x5>;
|
||||
divider-shift = <0x0>;
|
||||
clock-output-names = "ahbclk";
|
||||
};
|
||||
|
||||
sdioclk: sdioclk@1f2ac000 {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&socplldiv2 0>;
|
||||
reg = <0x0 0x1f2ac000 0x0 0x1000
|
||||
0x0 0x17000000 0x0 0x2000>;
|
||||
reg-names = "csr-reg", "div-reg";
|
||||
csr-offset = <0x0>;
|
||||
csr-mask = <0x2>;
|
||||
enable-offset = <0x8>;
|
||||
enable-mask = <0x2>;
|
||||
divider-offset = <0x178>;
|
||||
divider-width = <0x8>;
|
||||
divider-shift = <0x0>;
|
||||
clock-output-names = "sdioclk";
|
||||
};
|
||||
|
||||
qmlclk: qmlclk {
|
||||
compatible = "apm,xgene-device-clock";
|
||||
#clock-cells = <1>;
|
||||
@@ -686,6 +735,50 @@
|
||||
interrupts = <0x0 0x4f 0x4>;
|
||||
};
|
||||
|
||||
mmc0: mmc@1c000000 {
|
||||
compatible = "arasan,sdhci-4.9a";
|
||||
reg = <0x0 0x1c000000 0x0 0x100>;
|
||||
interrupts = <0x0 0x49 0x4>;
|
||||
dma-coherent;
|
||||
no-1-8-v;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&sdioclk 0>, <&ahbclk 0>;
|
||||
};
|
||||
|
||||
gfcgpio: gpio0@1701c000 {
|
||||
compatible = "apm,xgene-gpio";
|
||||
reg = <0x0 0x1701c000 0x0 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
dwgpio: gpio@1c024000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0 0x1c024000 0x0 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@10512000 {
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x10512000 0x0 0x1000>;
|
||||
interrupts = <0 0x44 0x4>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ahbclk 0>;
|
||||
bus_num = <0>;
|
||||
};
|
||||
|
||||
phy1: phy@1f21a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f21a000 0x0 0x100>;
|
||||
@@ -760,7 +853,26 @@
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
|
||||
sbgpio: sbgpio@17001000{
|
||||
/* Do not change dwusb name, coded for backward compatibility */
|
||||
usb0: dwusb@19000000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x19000000 0x0 0x100000>;
|
||||
interrupts = <0x0 0x89 0x4>;
|
||||
dma-coherent;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb1: dwusb@19800000 {
|
||||
status = "disabled";
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x19800000 0x0 0x100000>;
|
||||
interrupts = <0x0 0x8a 0x4>;
|
||||
dma-coherent;
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
sbgpio: gpio@17001000{
|
||||
compatible = "apm,xgene-gpio-sb";
|
||||
reg = <0x0 0x17001000 0x0 0x400>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
@@ -60,6 +60,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
@@ -67,6 +89,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
@@ -76,6 +99,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
@@ -85,6 +109,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
@@ -94,6 +119,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
@@ -103,6 +129,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
@@ -112,6 +139,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
|
||||
@@ -60,6 +60,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
@@ -67,6 +89,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
@@ -76,6 +99,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
@@ -85,6 +109,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
@@ -94,6 +119,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
@@ -103,6 +129,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
@@ -112,6 +139,7 @@
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
|
||||
@@ -50,10 +50,28 @@
|
||||
device_type = "memory";
|
||||
reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
uart3: serial@66130000 {
|
||||
status = "ok"
|
||||
};
|
||||
&i2c0 {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&nand {
|
||||
nandcs@0 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -31,6 +31,7 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/bcm-ns2.h>
|
||||
|
||||
/memreserve/ 0x84b00000 0x00000008;
|
||||
|
||||
@@ -44,36 +45,44 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
A57_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
A57_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
A57_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
A57_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0 3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x84b00000>;
|
||||
next-level-cache = <&CLUSTER0_L2>;
|
||||
};
|
||||
|
||||
CLUSTER0_L2: l2-cache@000 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -89,12 +98,154 @@
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A57_0>,
|
||||
<&A57_1>,
|
||||
<&A57_2>,
|
||||
<&A57_3>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
iprocmed: iprocmed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
iprocslow: iprocslow {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
|
||||
smmu: mmu@64000000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x64000000 0x40000>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
||||
mmu-masters;
|
||||
};
|
||||
|
||||
lcpll_ddr: lcpll_ddr@6501d058 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ddr";
|
||||
reg = <0x6501d058 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d04c 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
|
||||
"ddr", "ddr_ch2_unused",
|
||||
"ddr_ch3_unused", "ddr_ch4_unused",
|
||||
"ddr_ch5_unused";
|
||||
};
|
||||
|
||||
lcpll_ports: lcpll_ports@6501d078 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-lcpll-ports";
|
||||
reg = <0x6501d078 0x20>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d054 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll_ports", "wan", "rgmii",
|
||||
"ports_ch2_unused",
|
||||
"ports_ch3_unused",
|
||||
"ports_ch4_unused",
|
||||
"ports_ch5_unused";
|
||||
};
|
||||
|
||||
genpll_scr: genpll_scr@6501d098 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-scr";
|
||||
reg = <0x6501d098 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll_scr", "scr", "fs",
|
||||
"audio_ref", "scr_ch3_unused",
|
||||
"scr_ch4_unused", "scr_ch5_unused";
|
||||
};
|
||||
|
||||
genpll_sw: genpll_sw@6501d0c4 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,ns2-genpll-sw";
|
||||
reg = <0x6501d0c4 0x32>,
|
||||
<0x6501c020 0x4>,
|
||||
<0x6501d044 0x4>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll_sw", "rpe", "250", "nic",
|
||||
"chimp", "port", "sdio";
|
||||
};
|
||||
|
||||
crmu: crmu@65024000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x65024000 0x100>;
|
||||
};
|
||||
|
||||
reboot@65024000 {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&crmu>;
|
||||
offset = <0x90>;
|
||||
mask = <0xfffffffd>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@65210000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@@ -105,14 +256,53 @@
|
||||
<0x65260000 0x1000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@66080000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x66080000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@660b0000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x660b0000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@66130000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x66130000 0x100>;
|
||||
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <23961600>;
|
||||
clocks = <&osc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwrng: hwrng@66220000 {
|
||||
compatible = "brcm,iproc-rng200";
|
||||
reg = <0x66220000 0x28>;
|
||||
};
|
||||
|
||||
nand: nand@66460000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
||||
reg = <0x66460000 0x600>,
|
||||
<0x67015408 0x600>,
|
||||
<0x66460f00 0x20>;
|
||||
reg-names = "nand", "iproc-idm", "iproc-ext";
|
||||
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
brcm,nand-has-wp;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos7.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
|
||||
@@ -52,11 +53,288 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsi2c_4 {
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <200000>;
|
||||
status = "okay";
|
||||
|
||||
s2mps15_pmic@66 {
|
||||
compatible = "samsung,s2mps15-pmic";
|
||||
reg = <0x66>;
|
||||
interrupts = <2 IRQ_TYPE_NONE>;
|
||||
interrupt-parent = <&gpa0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_irq>;
|
||||
wakeup-source;
|
||||
|
||||
s2mps15_osc: clocks {
|
||||
compatible = "samsung,s2mps13-clk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "s2mps13_ap", "s2mps13_cp",
|
||||
"s2mps13_bt";
|
||||
};
|
||||
|
||||
regulators {
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "vdd_ldo1";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "vqmmc-sdcard";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "vdd_ldo3";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "vdd_ldo4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1110000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "vdd_ldo5";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "vdd_ldo6";
|
||||
regulator-min-microvolt = <2250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo7_reg: LDO7 {
|
||||
regulator-name = "vdd_ldo7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
regulator-name = "vdd_ldo8";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo9_reg: LDO9 {
|
||||
regulator-name = "vdd_ldo9";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo10_reg: LDO10 {
|
||||
regulator-name = "vdd_ldo10";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo11_reg: LDO11 {
|
||||
regulator-name = "vdd_ldo11";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo12_reg: LDO12 {
|
||||
regulator-name = "vdd_ldo12";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "vdd_ldo13";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-always-on;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo14_reg: LDO14 {
|
||||
regulator-name = "vdd_ldo14";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3375000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo17_reg: LDO17 {
|
||||
regulator-name = "vmmc-sdcard";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3375000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo18_reg: LDO18 {
|
||||
regulator-name = "vdd_ldo18";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2275000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo19_reg: LDO19 {
|
||||
regulator-name = "vdd_ldo19";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3375000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo21_reg: LDO21 {
|
||||
regulator-name = "vdd_ldo21";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3375000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo23_reg: LDO23 {
|
||||
regulator-name = "vdd_ldo23";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2275000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo25_reg: LDO25 {
|
||||
regulator-name = "vdd_ldo25";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3375000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo26_reg: LDO26 {
|
||||
regulator-name = "vdd_ldo26";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1470000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
ldo27_reg: LDO27 {
|
||||
regulator-name = "vdd_ldo27";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2275000>;
|
||||
regulator-enable-ramp-delay = <125>;
|
||||
};
|
||||
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "vdd_mif";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "vdd_atlas";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "vdd_int";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "vdd_buck5";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "vdd_g3d";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck7_reg: BUCK7 {
|
||||
regulator-name = "vdd_buck7";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck8_reg: BUCK8 {
|
||||
regulator-name = "vdd_buck8";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck9_reg: BUCK9 {
|
||||
regulator-name = "vdd_buck9";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
buck10_reg: BUCK10 {
|
||||
regulator-name = "vdd_buck10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <25000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
pmic_irq: pmic-irq {
|
||||
samsung,pins = "gpa0-2";
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc_0 {
|
||||
status = "okay";
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
card-detect-delay = <200>;
|
||||
clock-frequency = <800000000>;
|
||||
@@ -80,5 +358,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&ldo17_reg>;
|
||||
vqmmc-supply = <&ldo2_reg>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
@@ -454,6 +454,13 @@
|
||||
reg = <0x105c0000 0x5000>;
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
rtc: rtc@10590000 {
|
||||
compatible = "samsung,s3c6410-rtc";
|
||||
reg = <0x10590000 0x100>;
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
||||
@@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015, Freescale Semiconductor
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "fsl-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A RDB Board";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
adt7461a@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c512";
|
||||
reg = <0x52>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "pericom,pt7c4338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
status = "okay";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NOR, NAND Flashes and FPGA on board */
|
||||
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
|
||||
0x1 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
};
|
||||
|
||||
cpld: board-control@2,0 {
|
||||
compatible = "fsl,ls1043ardb-cpld";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user