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staging: crystalhd: remove driver
The driver hasn't had significant work done on it for a long time. Broadcom has EOLed the hardware and is no longer selling it. There are probably very few people still using it. So remove the driver. Signed-off-by: Kristina Martšenko <kristina.martsenko@gmail.com> Cc: Naren Sankar <nsankar@broadcom.com> Cc: Jarod Wilson <jarod@wilsonet.com> Cc: Scott Davilla <davilla@4pi.com> Cc: Manu Abraham <abraham.manu@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kristina Martšenko
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
895ae87657
commit
5c0ed8cdc4
@@ -8512,14 +8512,6 @@ M: H Hartley Sweeten <hsweeten@visionengravers.com>
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S: Odd Fixes
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F: drivers/staging/comedi/
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STAGING - CRYSTAL HD VIDEO DECODER
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M: Naren Sankar <nsankar@broadcom.com>
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M: Jarod Wilson <jarod@wilsonet.com>
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M: Scott Davilla <davilla@4pi.com>
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M: Manu Abraham <abraham.manu@gmail.com>
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S: Odd Fixes
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F: drivers/staging/crystalhd/
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STAGING - ECHO CANCELLER
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M: Steve Underwood <steveu@coppice.org>
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M: David Rowe <david@rowetel.com>
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@@ -80,8 +80,6 @@ source "drivers/staging/wlags49_h2/Kconfig"
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source "drivers/staging/wlags49_h25/Kconfig"
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source "drivers/staging/crystalhd/Kconfig"
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source "drivers/staging/cxt1e1/Kconfig"
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source "drivers/staging/xgifb/Kconfig"
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@@ -34,7 +34,6 @@ obj-$(CONFIG_DX_SEP) += sep/
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obj-$(CONFIG_IIO) += iio/
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obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/
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obj-$(CONFIG_WLAGS49_H25) += wlags49_h25/
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obj-$(CONFIG_CRYSTALHD) += crystalhd/
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obj-$(CONFIG_CXT1E1) += cxt1e1/
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obj-$(CONFIG_FB_XGI) += xgifb/
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obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
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@@ -1,6 +0,0 @@
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config CRYSTALHD
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tristate "Broadcom Crystal HD video decoder support"
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depends on PCI
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default n
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help
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Support for the Broadcom Crystal HD video decoder chipset
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@@ -1,6 +0,0 @@
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obj-$(CONFIG_CRYSTALHD) += crystalhd.o
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crystalhd-y := crystalhd_cmds.o \
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crystalhd_hw.o \
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crystalhd_lnx.o \
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crystalhd_misc.o
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@@ -1,15 +0,0 @@
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- Testing
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- Cleanup return codes
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- Cleanup typedefs
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- Allocate an Accelerator device class specific Major number,
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since we don't have any other open sourced accelerators, it is the only
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one in that category for now.
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A somewhat similar device is the DXR2/3
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Please send patches to:
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Greg Kroah-Hartman <greg@kroah.com>
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Naren Sankar <nsankar@broadcom.com>
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Jarod Wilson <jarod@wilsonet.com>
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Scott Davilla <davilla@4pi.com>
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Manu Abraham <abraham.manu@gmail.com>
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File diff suppressed because it is too large
Load Diff
@@ -1,300 +0,0 @@
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/********************************************************************
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* Copyright(c) 2006-2009 Broadcom Corporation.
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*
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* Name: bc_dts_glob_lnx.h
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*
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* Description: Wrapper to Windows dts_glob.h for Link-Linux usage.
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* The idea is to define additional Linux related defs
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* in this file to avoid changes to existing Windows
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* glob file.
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*
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* AU
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*
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* HISTORY:
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*
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********************************************************************
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* This header is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation, either version 2.1 of the License.
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*
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* This header is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public License
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* along with this header. If not, see <http://www.gnu.org/licenses/>.
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*******************************************************************/
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#ifndef _BC_DTS_GLOB_LNX_H_
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#define _BC_DTS_GLOB_LNX_H_
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#ifdef __LINUX_USER__
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <ctype.h>
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#include <string.h>
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#include <errno.h>
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#include <netdb.h>
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#include <sys/time.h>
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#include <time.h>
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#include <arpa/inet.h>
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#include <linux/param.h>
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#include <linux/ioctl.h>
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#include <sys/select.h>
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#define DRVIFLIB_INT_API
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#endif
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#include "crystalhd.h"
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#define CRYSTALHD_API_NAME "crystalhd"
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#define CRYSTALHD_API_DEV_NAME "/dev/crystalhd"
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/*
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* These are SW stack tunable parameters shared
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* between the driver and the application.
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*/
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enum BC_DTS_GLOBALS {
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BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */
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PCI_CFG_SIZE = 256, /* PCI config size buffer */
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BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */
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BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/
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BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */
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BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */
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BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/
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BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */
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BC_INFIFO_THRESHOLD = 0x10000,
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};
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struct BC_CMD_REG_ACC {
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uint32_t Offset;
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uint32_t Value;
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};
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struct BC_CMD_DEV_MEM {
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uint32_t StartOff;
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uint32_t NumDwords;
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uint32_t Rsrd;
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};
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/* FW Passthrough command structure */
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enum bc_fw_cmd_flags {
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BC_FW_CMD_FLAGS_NONE = 0,
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BC_FW_CMD_PIB_QS = 0x01,
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};
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struct BC_FW_CMD {
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uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ];
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uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ];
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uint32_t flags;
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uint32_t add_data;
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};
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struct BC_HW_TYPE {
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uint16_t PciDevId;
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uint16_t PciVenId;
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uint8_t HwRev;
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uint8_t Align[3];
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};
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struct BC_PCI_CFG {
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uint32_t Size;
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uint32_t Offset;
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uint8_t pci_cfg_space[PCI_CFG_SIZE];
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};
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struct BC_VERSION_INFO {
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uint8_t DriverMajor;
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uint8_t DriverMinor;
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uint16_t DriverRevision;
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};
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struct BC_START_RX_CAP {
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uint32_t Rsrd;
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uint32_t StartDeliveryThsh;
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uint32_t PauseThsh;
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uint32_t ResumeThsh;
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};
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struct BC_FLUSH_RX_CAP {
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uint32_t Rsrd;
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uint32_t bDiscardOnly;
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};
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struct BC_DTS_STATS {
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uint8_t drvRLL;
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uint8_t drvFLL;
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uint8_t eosDetected;
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uint8_t pwr_state_change;
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/* Stats from App */
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uint32_t opFrameDropped;
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uint32_t opFrameCaptured;
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uint32_t ipSampleCnt;
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uint64_t ipTotalSize;
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uint32_t reptdFrames;
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uint32_t pauseCount;
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uint32_t pibMisses;
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uint32_t discCounter;
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/* Stats from Driver */
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uint32_t TxFifoBsyCnt;
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uint32_t intCount;
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uint32_t DrvIgnIntrCnt;
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uint32_t DrvTotalFrmDropped;
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uint32_t DrvTotalHWErrs;
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uint32_t DrvTotalPIBFlushCnt;
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uint32_t DrvTotalFrmCaptured;
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uint32_t DrvPIBMisses;
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uint32_t DrvPauseTime;
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uint32_t DrvRepeatedFrms;
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uint32_t res1[13];
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};
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struct BC_PROC_INPUT {
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uint8_t *pDmaBuff;
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uint32_t BuffSz;
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uint8_t Mapped;
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uint8_t Encrypted;
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uint8_t Rsrd[2];
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uint32_t DramOffset; /* For debug use only */
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};
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struct BC_DEC_YUV_BUFFS {
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uint32_t b422Mode;
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uint8_t *YuvBuff;
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uint32_t YuvBuffSz;
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uint32_t UVbuffOffset;
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uint32_t YBuffDoneSz;
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uint32_t UVBuffDoneSz;
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uint32_t RefCnt;
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};
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enum DECOUT_COMPLETION_FLAGS {
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COMP_FLAG_NO_INFO = 0x00,
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COMP_FLAG_FMT_CHANGE = 0x01,
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COMP_FLAG_PIB_VALID = 0x02,
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COMP_FLAG_DATA_VALID = 0x04,
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COMP_FLAG_DATA_ENC = 0x08,
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COMP_FLAG_DATA_BOT = 0x10,
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};
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struct BC_DEC_OUT_BUFF {
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struct BC_DEC_YUV_BUFFS OutPutBuffs;
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struct BC_PIC_INFO_BLOCK PibInfo;
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uint32_t Flags;
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uint32_t BadFrCnt;
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};
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struct BC_NOTIFY_MODE {
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uint32_t Mode;
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uint32_t Rsvr[3];
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};
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struct BC_CLOCK {
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uint32_t clk;
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uint32_t Rsvr[3];
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};
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struct BC_IOCTL_DATA {
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enum BC_STATUS RetSts;
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uint32_t IoctlDataSz;
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uint32_t Timeout;
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union {
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struct BC_CMD_REG_ACC regAcc;
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struct BC_CMD_DEV_MEM devMem;
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struct BC_FW_CMD fwCmd;
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struct BC_HW_TYPE hwType;
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struct BC_PCI_CFG pciCfg;
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struct BC_VERSION_INFO VerInfo;
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struct BC_PROC_INPUT ProcInput;
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struct BC_DEC_YUV_BUFFS RxBuffs;
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struct BC_DEC_OUT_BUFF DecOutData;
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struct BC_START_RX_CAP RxCap;
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struct BC_FLUSH_RX_CAP FlushRxCap;
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struct BC_DTS_STATS drvStat;
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struct BC_NOTIFY_MODE NotifyMode;
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struct BC_CLOCK clockValue;
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} u;
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struct _BC_IOCTL_DATA *next;
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};
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enum BC_DRV_CMD {
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DRV_CMD_VERSION = 0, /* Get SW version */
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DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */
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DRV_CMD_REG_RD, /* Read Device Register */
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DRV_CMD_REG_WR, /* Write Device Register */
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DRV_CMD_FPGA_RD, /* Read FPGA Register */
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DRV_CMD_FPGA_WR, /* Write FPGA Register */
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DRV_CMD_MEM_RD, /* Read Device Memory */
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DRV_CMD_MEM_WR, /* Write Device Memory */
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DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */
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DRV_CMD_WR_PCI_CFG, /* Write the PCI Configuration Space*/
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DRV_CMD_FW_DOWNLOAD, /* Download Firmware */
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DRV_ISSUE_FW_CMD, /* Issue FW Cmd (pass through mode) */
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DRV_CMD_PROC_INPUT, /* Process Input Sample */
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DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */
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DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */
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DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */
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DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...
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we will enhance this later*/
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DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */
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DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */
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DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver
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in which the application is Operating*/
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DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power
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or improve performance */
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/* MUST be the last one.. */
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DRV_CMD_END, /* End of the List.. */
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};
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#define BC_IOC_BASE 'b'
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#define BC_IOC_VOID _IOC_NONE
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#define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type)
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#define BC_IOCTL_MB struct BC_IOCTL_DATA
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#define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB)
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#define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB)
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#define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB)
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#define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB)
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#define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB)
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#define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB)
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#define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB)
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#define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB)
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#define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB)
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#define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB)
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#define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB)
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#define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB)
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#define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB)
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#define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB)
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#define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB)
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#define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB)
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#define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB)
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#define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB)
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#define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB)
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#define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB)
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#define BCM_IOC_CHG_CLK BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB)
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#define BCM_IOC_END BC_IOC_VOID
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/* Wrapper for main IOCTL data */
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struct crystalhd_ioctl_data {
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struct BC_IOCTL_DATA udata; /* IOCTL from App..*/
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uint32_t u_id; /* Driver specific user ID */
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uint32_t cmd; /* Cmd ID for driver's use. */
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void *add_cdata; /* Additional command specific data..*/
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uint32_t add_cdata_sz; /* Additional command specific data size */
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struct crystalhd_ioctl_data *next; /* List/Fifo management */
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};
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enum crystalhd_kmod_ver {
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crystalhd_kmod_major = 0,
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crystalhd_kmod_minor = 9,
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crystalhd_kmod_rev = 27,
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};
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -1,13 +0,0 @@
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#ifndef _CRYSTALHD_H_
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#define _CRYSTALHD_H_
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#include "bc_dts_defs.h"
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#include "crystalhd_misc.h"
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#include "bc_dts_glob_lnx.h"
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#include "crystalhd_hw.h"
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#include "crystalhd_cmds.h"
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#include "crystalhd_lnx.h"
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#include "bcm_70012_regs.h"
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#include "crystalhd_fw_if.h"
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -1,92 +0,0 @@
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/***************************************************************************
|
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* Copyright (c) 2005-2009, Broadcom Corporation.
|
||||
*
|
||||
* Name: crystalhd_cmds . h
|
||||
*
|
||||
* Description:
|
||||
* BCM70010 Linux driver user command interfaces.
|
||||
*
|
||||
* HISTORY:
|
||||
*
|
||||
**********************************************************************
|
||||
* This file is part of the crystalhd device driver.
|
||||
*
|
||||
* This driver is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, version 2 of the License.
|
||||
*
|
||||
* This driver is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver. If not, see <http://www.gnu.org/licenses/>.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _CRYSTALHD_CMDS_H_
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#define _CRYSTALHD_CMDS_H_
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|
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/*
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||||
* NOTE:: This is the main interface file between the Linux layer
|
||||
* and the hardware layer. This file will use the definitions
|
||||
* from _dts_glob and dts_defs etc.. which are defined for
|
||||
* windows.
|
||||
*/
|
||||
|
||||
#include "crystalhd.h"
|
||||
|
||||
enum crystalhd_state {
|
||||
BC_LINK_INVALID = 0x00,
|
||||
BC_LINK_INIT = 0x01,
|
||||
BC_LINK_CAP_EN = 0x02,
|
||||
BC_LINK_FMT_CHG = 0x04,
|
||||
BC_LINK_SUSPEND = 0x10,
|
||||
BC_LINK_PAUSED = 0x20,
|
||||
BC_LINK_READY = (BC_LINK_INIT | BC_LINK_CAP_EN | BC_LINK_FMT_CHG),
|
||||
};
|
||||
|
||||
struct crystalhd_user {
|
||||
uint32_t uid;
|
||||
uint32_t in_use;
|
||||
uint32_t mode;
|
||||
};
|
||||
|
||||
#define DTS_MODE_INV (-1)
|
||||
|
||||
struct crystalhd_cmd {
|
||||
uint32_t state;
|
||||
struct crystalhd_adp *adp;
|
||||
struct crystalhd_user user[BC_LINK_MAX_OPENS];
|
||||
|
||||
spinlock_t ctx_lock;
|
||||
uint32_t tx_list_id;
|
||||
uint32_t cin_wait_exit;
|
||||
uint32_t pwr_state_change;
|
||||
struct crystalhd_hw hw_ctx;
|
||||
};
|
||||
|
||||
typedef enum BC_STATUS(*crystalhd_cmd_proc)(struct crystalhd_cmd *,
|
||||
struct crystalhd_ioctl_data *);
|
||||
|
||||
struct crystalhd_cmd_tbl {
|
||||
uint32_t cmd_id;
|
||||
const crystalhd_cmd_proc cmd_proc;
|
||||
uint32_t block_mon;
|
||||
};
|
||||
|
||||
enum BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx,
|
||||
struct crystalhd_ioctl_data *idata);
|
||||
enum BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx);
|
||||
crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx,
|
||||
uint32_t cmd, struct crystalhd_user *uc);
|
||||
enum BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx,
|
||||
struct crystalhd_user **user_ctx);
|
||||
enum BC_STATUS crystalhd_user_close(struct crystalhd_cmd *ctx,
|
||||
struct crystalhd_user *uc);
|
||||
enum BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx,
|
||||
struct crystalhd_adp *adp);
|
||||
enum BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx);
|
||||
bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx);
|
||||
|
||||
#endif
|
||||
@@ -1,370 +0,0 @@
|
||||
/***************************************************************************
|
||||
* Copyright (c) 2005-2009, Broadcom Corporation.
|
||||
*
|
||||
* Name: crystalhd_fw_if . h
|
||||
*
|
||||
* Description:
|
||||
* BCM70012 Firmware interface definitions.
|
||||
*
|
||||
* HISTORY:
|
||||
*
|
||||
**********************************************************************
|
||||
* This file is part of the crystalhd device driver.
|
||||
*
|
||||
* This driver is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, version 2 of the License.
|
||||
*
|
||||
* This driver is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver. If not, see <http://www.gnu.org/licenses/>.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _CRYSTALHD_FW_IF_H_
|
||||
#define _CRYSTALHD_FW_IF_H_
|
||||
|
||||
/* TBD: Pull in only required defs into this file.. */
|
||||
|
||||
/* User Data Header */
|
||||
struct user_data {
|
||||
struct user_data *next;
|
||||
uint32_t type;
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* MPEG Extension to the PPB *
|
||||
*------------------------------------------------------*/
|
||||
struct ppb_mpeg {
|
||||
uint32_t to_be_defined;
|
||||
uint32_t valid;
|
||||
|
||||
/* Always valid, defaults to picture size if no
|
||||
sequence display extension in the stream. */
|
||||
uint32_t display_horizontal_size;
|
||||
uint32_t display_vertical_size;
|
||||
|
||||
/* MPEG_VALID_PANSCAN
|
||||
Offsets are a copy values from the MPEG stream. */
|
||||
uint32_t offset_count;
|
||||
int32_t horizontal_offset[3];
|
||||
int32_t vertical_offset[3];
|
||||
|
||||
/* MPEG_VALID_USERDATA
|
||||
User data is in the form of a linked list. */
|
||||
int32_t userDataSize;
|
||||
struct user_data *userData;
|
||||
|
||||
};
|
||||
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* VC1 Extension to the PPB *
|
||||
*------------------------------------------------------*/
|
||||
struct ppb_vc1 {
|
||||
uint32_t to_be_defined;
|
||||
uint32_t valid;
|
||||
|
||||
/* Always valid, defaults to picture size if no
|
||||
sequence display extension in the stream. */
|
||||
uint32_t display_horizontal_size;
|
||||
uint32_t display_vertical_size;
|
||||
|
||||
/* VC1 pan scan windows */
|
||||
uint32_t num_panscan_windows;
|
||||
int32_t ps_horiz_offset[4];
|
||||
int32_t ps_vert_offset[4];
|
||||
int32_t ps_width[4];
|
||||
int32_t ps_height[4];
|
||||
|
||||
/* VC1_VALID_USERDATA
|
||||
User data is in the form of a linked list. */
|
||||
int32_t userDataSize;
|
||||
struct user_data *userData;
|
||||
|
||||
};
|
||||
|
||||
/*------------------------------------------------------*
|
||||
* H.264 Extension to the PPB *
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Film grain SEI message.
|
||||
*
|
||||
* Content of the film grain SEI message.
|
||||
*/
|
||||
|
||||
/* maximum number of model-values as for Thomson spec(standard says 5) */
|
||||
#define MAX_FGT_MODEL_VALUE (3)
|
||||
|
||||
/* maximum number of intervals(as many as 256 intervals?) */
|
||||
#define MAX_FGT_VALUE_INTERVAL (256)
|
||||
|
||||
struct fgt_sei {
|
||||
struct fgt_sei *next;
|
||||
unsigned char
|
||||
model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE];
|
||||
unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL];
|
||||
unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL];
|
||||
|
||||
unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */
|
||||
unsigned char model_id; /* Model id. */
|
||||
|
||||
/* +unused SE based on Thomson spec */
|
||||
unsigned char color_desc_flag; /* Separate color description flag. */
|
||||
unsigned char bit_depth_luma; /* Bit depth luma minus 8. */
|
||||
unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */
|
||||
unsigned char full_range_flag; /* Full range flag. */
|
||||
unsigned char color_primaries; /* Color primaries. */
|
||||
unsigned char transfer_charact; /* Transfer characteristics. */
|
||||
unsigned char matrix_coeff; /*< Matrix coefficients. */
|
||||
/* -unused SE based on Thomson spec */
|
||||
|
||||
unsigned char blending_mode_id; /* Blending mode. */
|
||||
unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */
|
||||
unsigned char comp_flag[3]; /* Components [0,2]
|
||||
parameters present flag. */
|
||||
unsigned char num_intervals_minus1[3]; /* Number of
|
||||
intensity level intervals. */
|
||||
unsigned char num_model_values[3]; /* Number of model values. */
|
||||
uint16_t repetition_period; /* Repetition period (0-16384) */
|
||||
|
||||
};
|
||||
|
||||
struct ppb_h264 {
|
||||
/* 'valid' specifies which fields (or sets of
|
||||
* fields) below are valid. If the corresponding
|
||||
* bit in 'valid' is NOT set then that field(s)
|
||||
* is (are) not initialized. */
|
||||
uint32_t valid;
|
||||
|
||||
int32_t poc_top; /* POC for Top Field/Frame */
|
||||
int32_t poc_bottom; /* POC for Bottom Field */
|
||||
uint32_t idr_pic_id;
|
||||
|
||||
/* H264_VALID_PANSCAN */
|
||||
uint32_t pan_scan_count;
|
||||
int32_t pan_scan_left[3];
|
||||
int32_t pan_scan_right[3];
|
||||
int32_t pan_scan_top[3];
|
||||
int32_t pan_scan_bottom[3];
|
||||
|
||||
/* H264_VALID_CT_TYPE */
|
||||
uint32_t ct_type_count;
|
||||
uint32_t ct_type[3];
|
||||
|
||||
/* H264_VALID_SPS_CROP */
|
||||
int32_t sps_crop_left;
|
||||
int32_t sps_crop_right;
|
||||
int32_t sps_crop_top;
|
||||
int32_t sps_crop_bottom;
|
||||
|
||||
/* H264_VALID_VUI */
|
||||
uint32_t chroma_top;
|
||||
uint32_t chroma_bottom;
|
||||
|
||||
/* H264_VALID_USER */
|
||||
uint32_t user_data_size;
|
||||
struct user_data *user_data;
|
||||
|
||||
/* H264 VALID FGT */
|
||||
struct fgt_sei *pfgt;
|
||||
|
||||
};
|
||||
|
||||
struct ppb {
|
||||
/* Common fields. */
|
||||
uint32_t picture_number; /* Ordinal display number */
|
||||
uint32_t video_buffer; /* Video (picbuf) number */
|
||||
uint32_t video_address; /* Address of picbuf Y */
|
||||
uint32_t video_address_uv; /* Address of picbuf UV */
|
||||
uint32_t video_stripe; /* Picbuf stripe */
|
||||
uint32_t video_width; /* Picbuf width */
|
||||
uint32_t video_height; /* Picbuf height */
|
||||
|
||||
uint32_t channel_id; /* Decoder channel ID */
|
||||
uint32_t status; /* reserved */
|
||||
uint32_t width; /* pixels */
|
||||
uint32_t height; /* pixels */
|
||||
uint32_t chroma_format; /* see above */
|
||||
uint32_t pulldown; /* see above */
|
||||
uint32_t flags; /* see above */
|
||||
uint32_t pts; /* 32 LSBs of PTS */
|
||||
uint32_t protocol; /* protocolXXX (above) */
|
||||
|
||||
uint32_t frame_rate; /* see above */
|
||||
uint32_t matrix_coeff; /* see above */
|
||||
uint32_t aspect_ratio; /* see above */
|
||||
uint32_t colour_primaries; /* see above */
|
||||
uint32_t transfer_char; /* see above */
|
||||
uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */
|
||||
uint32_t n_drop; /* Number of pictures to be dropped */
|
||||
|
||||
uint32_t custom_aspect_ratio_width_height;
|
||||
/* upper 16-bits is Y and lower 16-bits is X */
|
||||
|
||||
uint32_t picture_tag; /* Indexing tag from BUD packets */
|
||||
uint32_t picture_done_payload;
|
||||
uint32_t picture_meta_payload;
|
||||
uint32_t reserved[1];
|
||||
|
||||
/* Protocol-specific extensions. */
|
||||
union {
|
||||
struct ppb_h264 h264;
|
||||
struct ppb_mpeg mpeg;
|
||||
struct ppb_vc1 vc1;
|
||||
} other;
|
||||
|
||||
};
|
||||
|
||||
struct c011_pib {
|
||||
uint32_t bFormatChange;
|
||||
uint32_t resolution;
|
||||
uint32_t channelId;
|
||||
uint32_t ppbPtr;
|
||||
int32_t ptsStcOffset;
|
||||
uint32_t zeroPanscanValid;
|
||||
uint32_t dramOutBufAddr;
|
||||
uint32_t yComponent;
|
||||
struct ppb ppb;
|
||||
|
||||
};
|
||||
|
||||
struct dec_rsp_channel_start_video {
|
||||
uint32_t command;
|
||||
uint32_t sequence;
|
||||
uint32_t status;
|
||||
uint32_t picBuf;
|
||||
uint32_t picRelBuf;
|
||||
uint32_t picInfoDeliveryQ;
|
||||
uint32_t picInfoReleaseQ;
|
||||
uint32_t channelStatus;
|
||||
uint32_t userDataDeliveryQ;
|
||||
uint32_t userDataReleaseQ;
|
||||
uint32_t transportStreamCaptureAddr;
|
||||
uint32_t asyncEventQ;
|
||||
|
||||
};
|
||||
|
||||
#define eCMD_C011_CMD_BASE (0x73763000)
|
||||
|
||||
/* host commands */
|
||||
enum c011_ts_cmd {
|
||||
eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */
|
||||
eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */
|
||||
eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */
|
||||
|
||||
/* New API commands */
|
||||
/* General commands */
|
||||
eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01,
|
||||
eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02,
|
||||
eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03,
|
||||
eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04,
|
||||
eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05,
|
||||
eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06,
|
||||
|
||||
/* Decoding commands */
|
||||
eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100,
|
||||
eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101,
|
||||
eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102,
|
||||
eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103,
|
||||
eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104,
|
||||
eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105,
|
||||
eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106,
|
||||
eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107,
|
||||
eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108,
|
||||
eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109,
|
||||
eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A,
|
||||
eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B,
|
||||
eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D,
|
||||
eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E,
|
||||
eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F,
|
||||
eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110,
|
||||
eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111,
|
||||
eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112,
|
||||
eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113,
|
||||
eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114,
|
||||
eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115,
|
||||
eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116,
|
||||
eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117,
|
||||
eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118,
|
||||
eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119,
|
||||
eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A,
|
||||
eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B,
|
||||
eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C,
|
||||
eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D,
|
||||
eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E,
|
||||
eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F,
|
||||
eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120,
|
||||
eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121,
|
||||
eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122,
|
||||
eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123,
|
||||
eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124,
|
||||
eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125,
|
||||
eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126,
|
||||
eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127,
|
||||
eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128,
|
||||
eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129,
|
||||
eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A,
|
||||
eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B,
|
||||
eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C,
|
||||
eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D,
|
||||
eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E,
|
||||
eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F,
|
||||
eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130,
|
||||
eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131,
|
||||
eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE +
|
||||
0x132,
|
||||
eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133,
|
||||
eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134,
|
||||
eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135,
|
||||
eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136,
|
||||
eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137,
|
||||
eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138,
|
||||
eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139,
|
||||
eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140,
|
||||
eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141,
|
||||
eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142,
|
||||
eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143,
|
||||
eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144,
|
||||
eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145,
|
||||
eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146,
|
||||
eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE +
|
||||
0x147,
|
||||
eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148,
|
||||
eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149,
|
||||
eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST
|
||||
= eCMD_C011_CMD_BASE + 0x150,
|
||||
|
||||
/* Decoder RevD commands */
|
||||
eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color
|
||||
space conversion */
|
||||
eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181,
|
||||
eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182,
|
||||
/* Note: 0x183 not implemented yet in Rev D main */
|
||||
eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE +
|
||||
0x183,
|
||||
|
||||
/* Decoder 7412 commands (7412-only) */
|
||||
eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190,
|
||||
eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191,
|
||||
eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192,
|
||||
|
||||
eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF,
|
||||
|
||||
/* Encoding commands */
|
||||
eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200,
|
||||
eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201,
|
||||
eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202,
|
||||
eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203,
|
||||
eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204,
|
||||
|
||||
eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210,
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,407 +0,0 @@
|
||||
/***************************************************************************
|
||||
* Copyright (c) 2005-2009, Broadcom Corporation.
|
||||
*
|
||||
* Name: crystalhd_hw . h
|
||||
*
|
||||
* Description:
|
||||
* BCM70012 Linux driver hardware layer.
|
||||
*
|
||||
* HISTORY:
|
||||
*
|
||||
**********************************************************************
|
||||
* This file is part of the crystalhd device driver.
|
||||
*
|
||||
* This driver is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, version 2 of the License.
|
||||
*
|
||||
* This driver is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver. If not, see <http://www.gnu.org/licenses/>.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _CRYSTALHD_HW_H_
|
||||
#define _CRYSTALHD_HW_H_
|
||||
|
||||
#include "crystalhd.h"
|
||||
|
||||
/* HW constants..*/
|
||||
#define DMA_ENGINE_CNT 2
|
||||
#define MAX_PIB_Q_DEPTH 64
|
||||
#define MIN_PIB_Q_DEPTH 2
|
||||
#define WR_POINTER_OFF 4
|
||||
|
||||
#define ASPM_L1_ENABLE (BC_BIT(27))
|
||||
|
||||
/*************************************************
|
||||
7412 Decoder Registers.
|
||||
**************************************************/
|
||||
#define FW_CMD_BUFF_SZ 64
|
||||
#define TS_Host2CpuSnd 0x00000100
|
||||
#define Hst2CpuMbx1 0x00100F00
|
||||
#define Cpu2HstMbx1 0x00100F04
|
||||
#define MbxStat1 0x00100F08
|
||||
#define Stream2Host_Intr_Sts 0x00100F24
|
||||
#define C011_RET_SUCCESS 0x0 /* Return status of firmware command. */
|
||||
|
||||
/* TS input status register */
|
||||
#define TS_StreamAFIFOStatus 0x0010044C
|
||||
#define TS_StreamBFIFOStatus 0x0010084C
|
||||
|
||||
/*UART Selection definitions*/
|
||||
#define UartSelectA 0x00100300
|
||||
#define UartSelectB 0x00100304
|
||||
|
||||
#define BSVS_UART_DEC_NONE 0x00
|
||||
#define BSVS_UART_DEC_OUTER 0x01
|
||||
#define BSVS_UART_DEC_INNER 0x02
|
||||
#define BSVS_UART_STREAM 0x03
|
||||
|
||||
/* Code-In fifo */
|
||||
#define REG_DecCA_RegCinCTL 0xa00
|
||||
#define REG_DecCA_RegCinBase 0xa0c
|
||||
#define REG_DecCA_RegCinEnd 0xa10
|
||||
#define REG_DecCA_RegCinWrPtr 0xa04
|
||||
#define REG_DecCA_RegCinRdPtr 0xa08
|
||||
|
||||
#define REG_Dec_TsUser0Base 0x100864
|
||||
#define REG_Dec_TsUser0Rdptr 0x100868
|
||||
#define REG_Dec_TsUser0Wrptr 0x10086C
|
||||
#define REG_Dec_TsUser0End 0x100874
|
||||
|
||||
/* ASF Case ...*/
|
||||
#define REG_Dec_TsAudCDB2Base 0x10036c
|
||||
#define REG_Dec_TsAudCDB2Rdptr 0x100378
|
||||
#define REG_Dec_TsAudCDB2Wrptr 0x100374
|
||||
#define REG_Dec_TsAudCDB2End 0x100370
|
||||
|
||||
/* DRAM bringup Registers */
|
||||
#define SDRAM_PARAM 0x00040804
|
||||
#define SDRAM_PRECHARGE 0x000408B0
|
||||
#define SDRAM_EXT_MODE 0x000408A4
|
||||
#define SDRAM_MODE 0x000408A0
|
||||
#define SDRAM_REFRESH 0x00040890
|
||||
#define SDRAM_REF_PARAM 0x00040808
|
||||
|
||||
#define DecHt_PllACtl 0x34000C
|
||||
#define DecHt_PllBCtl 0x340010
|
||||
#define DecHt_PllCCtl 0x340014
|
||||
#define DecHt_PllDCtl 0x340034
|
||||
#define DecHt_PllECtl 0x340038
|
||||
#define AUD_DSP_MISC_SOFT_RESET 0x00240104
|
||||
#define AIO_MISC_PLL_RESET 0x0026000C
|
||||
#define PCIE_CLK_REQ_REG 0xDC
|
||||
#define PCI_CLK_REQ_ENABLE (BC_BIT(8))
|
||||
|
||||
/*************************************************
|
||||
F/W Copy engine definitions..
|
||||
**************************************************/
|
||||
#define BC_FWIMG_ST_ADDR 0x00000000
|
||||
/* FIXME: jarod: there's a kernel function that'll do this for us... */
|
||||
#define rotr32_1(x, n) (((x) >> n) | ((x) << (32 - n)))
|
||||
#define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
|
||||
|
||||
#define DecHt_HostSwReset 0x340000
|
||||
#define BC_DRAM_FW_CFG_ADDR 0x001c2000
|
||||
|
||||
union addr_64 {
|
||||
struct {
|
||||
uint32_t low_part;
|
||||
uint32_t high_part;
|
||||
};
|
||||
|
||||
uint64_t full_addr;
|
||||
|
||||
};
|
||||
|
||||
union intr_mask_reg {
|
||||
struct {
|
||||
uint32_t mask_tx_done:1;
|
||||
uint32_t mask_tx_err:1;
|
||||
uint32_t mask_rx_done:1;
|
||||
uint32_t mask_rx_err:1;
|
||||
uint32_t mask_pcie_err:1;
|
||||
uint32_t mask_pcie_rbusmast_err:1;
|
||||
uint32_t mask_pcie_rgr_bridge:1;
|
||||
uint32_t reserved:25;
|
||||
};
|
||||
|
||||
uint32_t whole_reg;
|
||||
|
||||
};
|
||||
|
||||
union link_misc_perst_deco_ctrl {
|
||||
struct {
|
||||
uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held
|
||||
in reset. Reset value 1.*/
|
||||
uint32_t reserved0:3; /* Reserved.No Effect*/
|
||||
uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of
|
||||
27MHz clk used to clk BCM7412*/
|
||||
uint32_t reserved1:27; /* Reserved. No Effect*/
|
||||
};
|
||||
|
||||
uint32_t whole_reg;
|
||||
|
||||
};
|
||||
|
||||
union link_misc_perst_clk_ctrl {
|
||||
struct {
|
||||
uint32_t sel_alt_clk:1; /* When set, selects a
|
||||
6.75MHz clock as the source of core_clk */
|
||||
uint32_t stop_core_clk:1; /* When set, stops the branch
|
||||
of core_clk that is not needed for low power operation */
|
||||
uint32_t pll_pwr_dn:1; /* When set, powers down the
|
||||
main PLL. The alternate clock bit should be set to
|
||||
select an alternate clock before setting this bit.*/
|
||||
uint32_t reserved0:5; /* Reserved */
|
||||
uint32_t pll_mult:8; /* This setting controls
|
||||
the multiplier for the PLL. */
|
||||
uint32_t pll_div:4; /* This setting controls
|
||||
the divider for the PLL. */
|
||||
uint32_t reserved1:12; /* Reserved */
|
||||
};
|
||||
|
||||
uint32_t whole_reg;
|
||||
|
||||
};
|
||||
|
||||
union link_misc_perst_decoder_ctrl {
|
||||
struct {
|
||||
uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held
|
||||
in reset. Reset value 1.*/
|
||||
uint32_t res0:3; /* Reserved.No Effect*/
|
||||
uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz
|
||||
clk used to clk BCM7412*/
|
||||
uint32_t res1:27; /* Reserved. No Effect */
|
||||
};
|
||||
|
||||
uint32_t whole_reg;
|
||||
|
||||
};
|
||||
|
||||
union desc_low_addr_reg {
|
||||
struct {
|
||||
uint32_t list_valid:1;
|
||||
uint32_t reserved:4;
|
||||
uint32_t low_addr:27;
|
||||
};
|
||||
|
||||
uint32_t whole_reg;
|
||||
|
||||
};
|
||||
|
||||
struct dma_descriptor { /* 8 32-bit values */
|
||||
/* 0th u32 */
|
||||
uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */
|
||||
uint32_t res0:4; /* bits 28-31: Reserved */
|
||||
|
||||
/* 1st u32 */
|
||||
uint32_t buff_addr_low; /* 1 buffer address low */
|
||||
uint32_t buff_addr_high; /* 2 buffer address high */
|
||||
|
||||
/* 3rd u32 */
|
||||
uint32_t res2:2; /* 0-1 - Reserved */
|
||||
uint32_t xfer_size:23; /* 2-24 = Xfer size in words */
|
||||
uint32_t res3:6; /* 25-30 reserved */
|
||||
uint32_t intr_enable:1; /* 31 - Interrupt After this desc */
|
||||
|
||||
/* 4th u32 */
|
||||
uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */
|
||||
uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */
|
||||
uint32_t res4:25; /* 3 - 27 Reserved bits */
|
||||
uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */
|
||||
uint32_t dma_dir:1; /* 30 bit DMA Direction */
|
||||
uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */
|
||||
|
||||
/* 5th u32 */
|
||||
uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */
|
||||
|
||||
/* 6th u32 */
|
||||
uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */
|
||||
|
||||
/* 7th u32 */
|
||||
uint32_t res8; /* Last 32bits reserved */
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* We will allocate the memory in 4K pages
|
||||
* the linked list will be a list of 32 byte descriptors.
|
||||
* The virtual address will determine what should be freed.
|
||||
*/
|
||||
struct dma_desc_mem {
|
||||
struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma
|
||||
descriptor. should be first element */
|
||||
dma_addr_t phy_addr; /* physical address
|
||||
of each DMA desc */
|
||||
uint32_t sz;
|
||||
struct _dma_desc_mem_ *Next; /* points to Next Descriptor in chain */
|
||||
|
||||
};
|
||||
|
||||
enum list_sts {
|
||||
sts_free = 0,
|
||||
|
||||
/* RX-Y Bits 0:7 */
|
||||
rx_waiting_y_intr = 0x00000001,
|
||||
rx_y_error = 0x00000004,
|
||||
|
||||
/* RX-UV Bits 8:16 */
|
||||
rx_waiting_uv_intr = 0x0000100,
|
||||
rx_uv_error = 0x0000400,
|
||||
|
||||
rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr),
|
||||
rx_sts_error = (rx_y_error|rx_uv_error),
|
||||
|
||||
rx_y_mask = 0x000000FF,
|
||||
rx_uv_mask = 0x0000FF00,
|
||||
};
|
||||
|
||||
struct tx_dma_pkt {
|
||||
struct dma_desc_mem desc_mem;
|
||||
hw_comp_callback call_back;
|
||||
struct crystalhd_dio_req *dio_req;
|
||||
wait_queue_head_t *cb_event;
|
||||
uint32_t list_tag;
|
||||
};
|
||||
|
||||
struct crystalhd_rx_dma_pkt {
|
||||
struct dma_desc_mem desc_mem;
|
||||
struct crystalhd_dio_req *dio_req;
|
||||
uint32_t pkt_tag;
|
||||
uint32_t flags;
|
||||
struct BC_PIC_INFO_BLOCK pib;
|
||||
dma_addr_t uv_phy_addr;
|
||||
struct crystalhd_rx_dma_pkt *next;
|
||||
};
|
||||
|
||||
struct crystalhd_hw_stats {
|
||||
uint32_t rx_errors;
|
||||
uint32_t tx_errors;
|
||||
uint32_t freeq_count;
|
||||
uint32_t rdyq_count;
|
||||
uint32_t num_interrupts;
|
||||
uint32_t dev_interrupts;
|
||||
uint32_t cin_busy;
|
||||
uint32_t pause_cnt;
|
||||
};
|
||||
|
||||
struct crystalhd_hw {
|
||||
struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT];
|
||||
spinlock_t lock;
|
||||
|
||||
uint32_t tx_ioq_tag_seed;
|
||||
uint32_t tx_list_post_index;
|
||||
|
||||
struct crystalhd_rx_dma_pkt *rx_pkt_pool_head;
|
||||
uint32_t rx_pkt_tag_seed;
|
||||
|
||||
bool dev_started;
|
||||
void *adp;
|
||||
|
||||
wait_queue_head_t *pfw_cmd_event;
|
||||
int fwcmd_evt_sts;
|
||||
|
||||
uint32_t pib_del_Q_addr;
|
||||
uint32_t pib_rel_Q_addr;
|
||||
|
||||
struct crystalhd_dioq *tx_freeq;
|
||||
struct crystalhd_dioq *tx_actq;
|
||||
|
||||
/* Rx DMA Engine Specific Locks */
|
||||
spinlock_t rx_lock;
|
||||
uint32_t rx_list_post_index;
|
||||
enum list_sts rx_list_sts[DMA_ENGINE_CNT];
|
||||
struct crystalhd_dioq *rx_rdyq;
|
||||
struct crystalhd_dioq *rx_freeq;
|
||||
struct crystalhd_dioq *rx_actq;
|
||||
uint32_t stop_pending;
|
||||
|
||||
/* HW counters.. */
|
||||
struct crystalhd_hw_stats stats;
|
||||
|
||||
/* Core clock in MHz */
|
||||
uint32_t core_clock_mhz;
|
||||
uint32_t prev_n;
|
||||
uint32_t pwr_lock;
|
||||
};
|
||||
|
||||
/* Clock defines for power control */
|
||||
#define CLOCK_PRESET 175
|
||||
|
||||
/* DMA engine register BIT mask wrappers.. */
|
||||
#define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
|
||||
|
||||
#define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \
|
||||
INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
|
||||
|
||||
#define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
|
||||
|
||||
#define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
|
||||
|
||||
#define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
|
||||
MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
|
||||
|
||||
#define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \
|
||||
MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
|
||||
|
||||
|
||||
/**** API Exposed to the other layers ****/
|
||||
enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
|
||||
void *buffer, uint32_t sz);
|
||||
enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw,
|
||||
struct BC_FW_CMD *fw_cmd);
|
||||
bool crystalhd_hw_interrupt(struct crystalhd_adp *adp,
|
||||
struct crystalhd_hw *hw);
|
||||
enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *,
|
||||
struct crystalhd_adp *);
|
||||
enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
|
||||
enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
|
||||
enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
|
||||
|
||||
|
||||
enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw,
|
||||
struct crystalhd_dio_req *ioreq,
|
||||
hw_comp_callback call_back,
|
||||
wait_queue_head_t *cb_event,
|
||||
uint32_t *list_id, uint8_t data_flags);
|
||||
|
||||
enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
|
||||
enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
|
||||
enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
|
||||
enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw,
|
||||
uint32_t list_id);
|
||||
enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
|
||||
struct crystalhd_dio_req *ioreq, bool en_post);
|
||||
enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
|
||||
struct BC_PIC_INFO_BLOCK *pib,
|
||||
struct crystalhd_dio_req **ioreq);
|
||||
enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
|
||||
enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
|
||||
void crystalhd_hw_stats(struct crystalhd_hw *hw,
|
||||
struct crystalhd_hw_stats *stats);
|
||||
|
||||
/* API to program the core clock on the decoder */
|
||||
enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,93 +0,0 @@
|
||||
/***************************************************************************
|
||||
* Copyright (c) 2005-2009, Broadcom Corporation.
|
||||
*
|
||||
* Name: crystalhd_lnx . h
|
||||
*
|
||||
* Description:
|
||||
* BCM70012 Linux driver
|
||||
*
|
||||
* HISTORY:
|
||||
*
|
||||
**********************************************************************
|
||||
* This file is part of the crystalhd device driver.
|
||||
*
|
||||
* This driver is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, version 2 of the License.
|
||||
*
|
||||
* This driver is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver. If not, see <http://www.gnu.org/licenses/>.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _CRYSTALHD_LNX_H_
|
||||
#define _CRYSTALHD_LNX_H_
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include "crystalhd.h"
|
||||
|
||||
#define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder (BCM70012) Driver"
|
||||
|
||||
/* OS specific PCI information structure and adapter information. */
|
||||
struct crystalhd_adp {
|
||||
/* Hardware board/PCI specifics */
|
||||
char name[32];
|
||||
struct pci_dev *pdev;
|
||||
|
||||
unsigned long pci_mem_start;
|
||||
uint32_t pci_mem_len;
|
||||
void __iomem *addr;
|
||||
|
||||
unsigned long pci_i2o_start;
|
||||
uint32_t pci_i2o_len;
|
||||
void __iomem *i2o_addr;
|
||||
|
||||
unsigned int drv_data;
|
||||
unsigned int dmabits; /* 32 | 64 */
|
||||
unsigned int registered;
|
||||
unsigned int present;
|
||||
unsigned int msi;
|
||||
|
||||
spinlock_t lock;
|
||||
|
||||
/* API Related */
|
||||
int chd_dec_major;
|
||||
unsigned int cfg_users;
|
||||
|
||||
struct crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */
|
||||
struct crystalhd_elem *elem_pool_head; /* Queue element pool */
|
||||
|
||||
struct crystalhd_cmd cmds;
|
||||
|
||||
struct crystalhd_dio_req *ua_map_free_head;
|
||||
struct pci_pool *fill_byte_pool;
|
||||
};
|
||||
|
||||
|
||||
struct crystalhd_adp *chd_get_adp(void);
|
||||
void chd_set_log_level(struct crystalhd_adp *adp, char *arg);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,232 +0,0 @@
|
||||
/***************************************************************************
|
||||
* Copyright (c) 2005-2009, Broadcom Corporation.
|
||||
*
|
||||
* Name: crystalhd_misc . h
|
||||
*
|
||||
* Description:
|
||||
* BCM70012 Linux driver general purpose routines.
|
||||
* Includes reg/mem read and write routines.
|
||||
*
|
||||
* HISTORY:
|
||||
*
|
||||
**********************************************************************
|
||||
* This file is part of the crystalhd device driver.
|
||||
*
|
||||
* This driver is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, version 2 of the License.
|
||||
*
|
||||
* This driver is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this driver. If not, see <http://www.gnu.org/licenses/>.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _CRYSTALHD_MISC_H_
|
||||
#define _CRYSTALHD_MISC_H_
|
||||
|
||||
#include "crystalhd.h"
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/sched.h>
|
||||
#include "bc_dts_glob_lnx.h"
|
||||
|
||||
/* Global log level variable defined in crystal_misc.c file */
|
||||
extern uint32_t g_linklog_level;
|
||||
|
||||
/* Global element pool for all Queue management.
|
||||
* TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT.
|
||||
* RX: Free = BC_RX_LIST_CNT, Active = 2
|
||||
* FW-CMD: 4
|
||||
*/
|
||||
#define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4)
|
||||
|
||||
/* Driver's IODATA pool count */
|
||||
#define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS)
|
||||
|
||||
/* Scatter Gather memory pool size for Tx and Rx */
|
||||
#define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT)
|
||||
|
||||
enum crystalhd_dio_sig {
|
||||
crystalhd_dio_inv = 0,
|
||||
crystalhd_dio_locked,
|
||||
crystalhd_dio_sg_mapped,
|
||||
};
|
||||
|
||||
struct crystalhd_dio_user_info {
|
||||
void *xfr_buff;
|
||||
uint32_t xfr_len;
|
||||
uint32_t uv_offset;
|
||||
bool dir_tx;
|
||||
|
||||
uint32_t uv_sg_ix;
|
||||
uint32_t uv_sg_off;
|
||||
int comp_sts;
|
||||
int ev_sts;
|
||||
uint32_t y_done_sz;
|
||||
uint32_t uv_done_sz;
|
||||
uint32_t comp_flags;
|
||||
bool b422mode;
|
||||
};
|
||||
|
||||
struct crystalhd_dio_req {
|
||||
uint32_t sig;
|
||||
uint32_t max_pages;
|
||||
struct page **pages;
|
||||
struct scatterlist *sg;
|
||||
int sg_cnt;
|
||||
int page_cnt;
|
||||
int direction;
|
||||
struct crystalhd_dio_user_info uinfo;
|
||||
void *fb_va;
|
||||
uint32_t fb_size;
|
||||
dma_addr_t fb_pa;
|
||||
struct crystalhd_dio_req *next;
|
||||
};
|
||||
|
||||
#define BC_LINK_DIOQ_SIG (0x09223280)
|
||||
|
||||
struct crystalhd_elem {
|
||||
struct crystalhd_elem *flink;
|
||||
struct crystalhd_elem *blink;
|
||||
void *data;
|
||||
uint32_t tag;
|
||||
};
|
||||
|
||||
typedef void (*crystalhd_data_free_cb)(void *context, void *data);
|
||||
|
||||
struct crystalhd_dioq {
|
||||
uint32_t sig;
|
||||
struct crystalhd_adp *adp;
|
||||
struct crystalhd_elem *head;
|
||||
struct crystalhd_elem *tail;
|
||||
uint32_t count;
|
||||
spinlock_t lock;
|
||||
wait_queue_head_t event;
|
||||
crystalhd_data_free_cb data_rel_cb;
|
||||
void *cb_context;
|
||||
};
|
||||
|
||||
typedef void (*hw_comp_callback)(struct crystalhd_dio_req *,
|
||||
wait_queue_head_t *event, enum BC_STATUS sts);
|
||||
|
||||
/*========= Decoder (7412) register access routines.================= */
|
||||
uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t);
|
||||
void bc_dec_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t);
|
||||
|
||||
/*========= Link (70012) register access routines.. =================*/
|
||||
uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t);
|
||||
void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t);
|
||||
|
||||
/*========= Decoder (7412) memory access routines..=================*/
|
||||
enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *,
|
||||
uint32_t, uint32_t, uint32_t *);
|
||||
enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *,
|
||||
uint32_t, uint32_t, uint32_t *);
|
||||
|
||||
/*==========Link (70012) PCIe Config access routines.================*/
|
||||
enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *,
|
||||
uint32_t, uint32_t, uint32_t *);
|
||||
enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *,
|
||||
uint32_t, uint32_t, uint32_t);
|
||||
|
||||
/*========= Linux Kernel Interface routines. ======================= */
|
||||
void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *);
|
||||
void bc_kern_dma_free(struct crystalhd_adp *, uint32_t,
|
||||
void *, dma_addr_t);
|
||||
#define crystalhd_create_event(_ev) init_waitqueue_head(_ev)
|
||||
#define crystalhd_set_event(_ev) wake_up_interruptible(_ev)
|
||||
#define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \
|
||||
do { \
|
||||
DECLARE_WAITQUEUE(entry, current); \
|
||||
unsigned long end = jiffies + ((timeout * HZ) / 1000); \
|
||||
ret = 0; \
|
||||
add_wait_queue(ev, &entry); \
|
||||
for (;;) { \
|
||||
__set_current_state(TASK_INTERRUPTIBLE); \
|
||||
if (condition) { \
|
||||
break; \
|
||||
} \
|
||||
if (time_after_eq(jiffies, end)) { \
|
||||
ret = -EBUSY; \
|
||||
break; \
|
||||
} \
|
||||
schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \
|
||||
if (!nosig && signal_pending(current)) { \
|
||||
ret = -EINTR; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
__set_current_state(TASK_RUNNING); \
|
||||
remove_wait_queue(ev, &entry); \
|
||||
} while (0)
|
||||
|
||||
/*================ Direct IO mapping routines ==================*/
|
||||
extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t);
|
||||
extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *);
|
||||
extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *,
|
||||
uint32_t, uint32_t, bool, bool, struct crystalhd_dio_req**);
|
||||
|
||||
extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *,
|
||||
struct crystalhd_dio_req*);
|
||||
#define crystalhd_get_sgle_paddr(_dio, _ix) (sg_dma_address(&_dio->sg[_ix]))
|
||||
#define crystalhd_get_sgle_len(_dio, _ix) (sg_dma_len(&_dio->sg[_ix]))
|
||||
|
||||
/*================ General Purpose Queues ==================*/
|
||||
extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *,
|
||||
struct crystalhd_dioq **, crystalhd_data_free_cb , void *);
|
||||
extern void crystalhd_delete_dioq(struct crystalhd_adp *,
|
||||
struct crystalhd_dioq *);
|
||||
extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq,
|
||||
void *data, bool wake, uint32_t tag);
|
||||
extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq);
|
||||
extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq,
|
||||
uint32_t tag);
|
||||
extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq,
|
||||
uint32_t to_secs, uint32_t *sig_pend);
|
||||
|
||||
#define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0)
|
||||
|
||||
extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t);
|
||||
extern void crystalhd_delete_elem_pool(struct crystalhd_adp *);
|
||||
|
||||
|
||||
/*================ Debug routines/macros .. ================================*/
|
||||
extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff,
|
||||
uint32_t dwcount);
|
||||
|
||||
enum _chd_log_levels {
|
||||
BCMLOG_ERROR = 0x80000000, /* Don't disable this option */
|
||||
BCMLOG_DATA = 0x40000000, /* Data, enable by default */
|
||||
BCMLOG_SPINLOCK = 0x20000000, /* Special case for Spin locks*/
|
||||
|
||||
/* Following are allowed only in debug mode */
|
||||
BCMLOG_INFO = 0x00000001, /* Generic informational */
|
||||
BCMLOG_DBG = 0x00000002, /* First level Debug info */
|
||||
BCMLOG_SSTEP = 0x00000004, /* Stepping information */
|
||||
};
|
||||
|
||||
|
||||
#define BCMLOG(trace, fmt, args...) \
|
||||
do { \
|
||||
if (g_linklog_level & trace) \
|
||||
printk(fmt, ##args); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define BCMLOG_ERR(fmt, args...) \
|
||||
do { \
|
||||
if (g_linklog_level & BCMLOG_ERROR) \
|
||||
pr_err("*ERR*:%s:%d: "fmt, \
|
||||
__FILE__, __LINE__, ##args); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user