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Merge git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci
This commit is contained in:
James Bottomley
@@ -830,6 +830,19 @@ config SCSI_GDTH
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To compile this driver as a module, choose M here: the
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module will be called gdth.
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config SCSI_ISCI
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tristate "Intel(R) C600 Series Chipset SAS Controller"
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depends on PCI && SCSI
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depends on X86
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# (temporary): known alpha quality driver
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depends on EXPERIMENTAL
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select SCSI_SAS_LIBSAS
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---help---
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This driver supports the 6Gb/s SAS capabilities of the storage
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control unit found in the Intel(R) C600 series chipset.
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The experimental tag will be removed after the driver exits alpha
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config SCSI_GENERIC_NCR5380
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tristate "Generic NCR5380/53c400 SCSI PIO support"
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depends on ISA && SCSI
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@@ -73,6 +73,7 @@ obj-$(CONFIG_SCSI_AACRAID) += aacraid/
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obj-$(CONFIG_SCSI_AIC7XXX_OLD) += aic7xxx_old.o
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obj-$(CONFIG_SCSI_AIC94XX) += aic94xx/
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obj-$(CONFIG_SCSI_PM8001) += pm8001/
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obj-$(CONFIG_SCSI_ISCI) += isci/
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obj-$(CONFIG_SCSI_IPS) += ips.o
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obj-$(CONFIG_SCSI_FD_MCS) += fd_mcs.o
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obj-$(CONFIG_SCSI_FUTURE_DOMAIN)+= fdomain.o
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@@ -0,0 +1,8 @@
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obj-$(CONFIG_SCSI_ISCI) += isci.o
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isci-objs := init.o phy.o request.o \
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remote_device.o port.o \
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host.o task.o probe_roms.o \
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remote_node_context.o \
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remote_node_table.o \
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unsolicited_frame_control.o \
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port_config.o \
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@@ -0,0 +1,19 @@
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# Makefile for create_fw
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#
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CC=gcc
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CFLAGS=-c -Wall -O2 -g
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LDFLAGS=
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SOURCES=create_fw.c
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OBJECTS=$(SOURCES:.cpp=.o)
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EXECUTABLE=create_fw
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all: $(SOURCES) $(EXECUTABLE)
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$(EXECUTABLE): $(OBJECTS)
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$(CC) $(LDFLAGS) $(OBJECTS) -o $@
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.c.o:
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$(CC) $(CFLAGS) $< -O $@
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clean:
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rm -f *.o $(EXECUTABLE)
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@@ -0,0 +1,36 @@
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This defines the temporary binary blow we are to pass to the SCU
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driver to emulate the binary firmware that we will eventually be
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able to access via NVRAM on the SCU controller.
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The current size of the binary blob is expected to be 149 bytes or larger
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Header Types:
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0x1: Phy Masks
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0x2: Phy Gens
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0x3: SAS Addrs
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0xff: End of Data
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ID string - u8[12]: "#SCU MAGIC#\0"
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Version - u8: 1
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SubVersion - u8: 0
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Header Type - u8: 0x1
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Size - u8: 8
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Phy Mask - u32[8]
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Header Type - u8: 0x2
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Size - u8: 8
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Phy Gen - u32[8]
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Header Type - u8: 0x3
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Size - u8: 8
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Sas Addr - u64[8]
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Header Type - u8: 0xf
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==============================================================================
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Place isci_firmware.bin in /lib/firmware
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Be sure to recreate the initramfs image to include the firmware.
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@@ -0,0 +1,99 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <string.h>
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#include <errno.h>
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#include <asm/types.h>
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#include <strings.h>
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#include <stdint.h>
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#include "create_fw.h"
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#include "../probe_roms.h"
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int write_blob(struct isci_orom *isci_orom)
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{
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FILE *fd;
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int err;
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size_t count;
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fd = fopen(blob_name, "w+");
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if (!fd) {
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perror("Open file for write failed");
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fclose(fd);
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return -EIO;
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}
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count = fwrite(isci_orom, sizeof(struct isci_orom), 1, fd);
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if (count != 1) {
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perror("Write data failed");
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fclose(fd);
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return -EIO;
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}
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fclose(fd);
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return 0;
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}
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void set_binary_values(struct isci_orom *isci_orom)
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{
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int ctrl_idx, phy_idx, port_idx;
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/* setting OROM signature */
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strncpy(isci_orom->hdr.signature, sig, strlen(sig));
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isci_orom->hdr.version = version;
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isci_orom->hdr.total_block_length = sizeof(struct isci_orom);
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isci_orom->hdr.hdr_length = sizeof(struct sci_bios_oem_param_block_hdr);
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isci_orom->hdr.num_elements = num_elements;
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for (ctrl_idx = 0; ctrl_idx < 2; ctrl_idx++) {
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isci_orom->ctrl[ctrl_idx].controller.mode_type = mode_type;
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isci_orom->ctrl[ctrl_idx].controller.max_concurrent_dev_spin_up =
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max_num_concurrent_dev_spin_up;
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isci_orom->ctrl[ctrl_idx].controller.do_enable_ssc =
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enable_ssc;
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for (port_idx = 0; port_idx < 4; port_idx++)
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isci_orom->ctrl[ctrl_idx].ports[port_idx].phy_mask =
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phy_mask[ctrl_idx][port_idx];
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for (phy_idx = 0; phy_idx < 4; phy_idx++) {
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.high =
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(__u32)(sas_addr[ctrl_idx][phy_idx] >> 32);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.low =
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(__u32)(sas_addr[ctrl_idx][phy_idx]);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control0 =
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afe_tx_amp_control0;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control1 =
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afe_tx_amp_control1;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control2 =
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afe_tx_amp_control2;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control3 =
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afe_tx_amp_control3;
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}
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}
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}
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int main(void)
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{
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int err;
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struct isci_orom *isci_orom;
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isci_orom = malloc(sizeof(struct isci_orom));
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memset(isci_orom, 0, sizeof(struct isci_orom));
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set_binary_values(isci_orom);
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err = write_blob(isci_orom);
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if (err < 0) {
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free(isci_orom);
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return err;
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}
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free(isci_orom);
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return 0;
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}
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@@ -0,0 +1,77 @@
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#ifndef _CREATE_FW_H_
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#define _CREATE_FW_H_
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#include "../probe_roms.h"
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/* we are configuring for 2 SCUs */
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static const int num_elements = 2;
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/*
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* For all defined arrays:
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* elements 0-3 are for SCU0, ports 0-3
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* elements 4-7 are for SCU1, ports 0-3
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*
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* valid configurations for one SCU are:
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* P0 P1 P2 P3
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* ----------------
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* 0xF,0x0,0x0,0x0 # 1 x4 port
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* 0x3,0x0,0x4,0x8 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are each x1
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* # ports
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* 0x1,0x2,0xC,0x0 # Phys 0 and 1 are each x1 ports, phy 2 and phy 3 are a x2
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* # port
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* 0x3,0x0,0xC,0x0 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are a x2 port
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* 0x1,0x2,0x4,0x8 # Each phy is a x1 port (this is the default configuration)
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*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value assigned to UNINIT_PARAM (255).
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*/
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/* discovery mode type (port auto config mode by default ) */
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/*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value "0000000000000000". SAS address of zero's is
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* considered invalid and will not be used.
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*/
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#ifdef MPC
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static const int mode_type = SCIC_PORT_MANUAL_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4] = { {1, 2, 4, 8},
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{1, 2, 4, 8} };
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFFF0000001ULL,
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0x5FCFFFFFF0000002ULL,
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0x5FCFFFFFF0000003ULL,
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0x5FCFFFFFF0000004ULL },
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{ 0x5FCFFFFFF0000005ULL,
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0x5FCFFFFFF0000006ULL,
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0x5FCFFFFFF0000007ULL,
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0x5FCFFFFFF0000008ULL } };
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#else /* APC (default) */
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static const int mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4];
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL },
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{ 0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL } };
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#endif
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/* Maximum number of concurrent device spin up */
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static const int max_num_concurrent_dev_spin_up = 1;
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/* enable of ssc operation */
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static const int enable_ssc;
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/* AFE_TX_AMP_CONTROL */
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static const unsigned int afe_tx_amp_control0 = 0x000bdd08;
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static const unsigned int afe_tx_amp_control1 = 0x000ffc00;
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static const unsigned int afe_tx_amp_control2 = 0x000b7c09;
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static const unsigned int afe_tx_amp_control3 = 0x000afc6e;
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static const char blob_name[] = "isci_firmware.bin";
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static const char sig[] = "ISCUOEMB";
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static const unsigned char version = 0x10;
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,306 @@
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/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _ISCI_PORT_H_
|
||||
#define _ISCI_PORT_H_
|
||||
|
||||
#include <scsi/libsas.h>
|
||||
#include "isci.h"
|
||||
#include "sas.h"
|
||||
#include "phy.h"
|
||||
|
||||
#define SCIC_SDS_DUMMY_PORT 0xFF
|
||||
|
||||
struct isci_phy;
|
||||
struct isci_host;
|
||||
|
||||
enum isci_status {
|
||||
isci_freed = 0x00,
|
||||
isci_starting = 0x01,
|
||||
isci_ready = 0x02,
|
||||
isci_ready_for_io = 0x03,
|
||||
isci_stopping = 0x04,
|
||||
isci_stopped = 0x05,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct isci_port - isci direct attached sas port object
|
||||
* @event: counts bcns and port stop events (for bcn filtering)
|
||||
* @ready_exit: several states constitute 'ready'. When exiting ready we
|
||||
* need to take extra port-teardown actions that are
|
||||
* skipped when exiting to another 'ready' state.
|
||||
* @logical_port_index: software port index
|
||||
* @physical_port_index: hardware port index
|
||||
* @active_phy_mask: identifies phy members
|
||||
* @reserved_tag:
|
||||
* @reserved_rni: reserver for port task scheduler workaround
|
||||
* @started_request_count: reference count for outstanding commands
|
||||
* @not_ready_reason: set during state transitions and notified
|
||||
* @timer: timeout start/stop operations
|
||||
*/
|
||||
struct isci_port {
|
||||
enum isci_status status;
|
||||
#define IPORT_BCN_BLOCKED 0
|
||||
#define IPORT_BCN_PENDING 1
|
||||
unsigned long flags;
|
||||
atomic_t event;
|
||||
struct isci_host *isci_host;
|
||||
struct asd_sas_port sas_port;
|
||||
struct list_head remote_dev_list;
|
||||
spinlock_t state_lock;
|
||||
struct list_head domain_dev_list;
|
||||
struct completion start_complete;
|
||||
struct completion hard_reset_complete;
|
||||
enum sci_status hard_reset_status;
|
||||
struct sci_base_state_machine sm;
|
||||
bool ready_exit;
|
||||
u8 logical_port_index;
|
||||
u8 physical_port_index;
|
||||
u8 active_phy_mask;
|
||||
u16 reserved_rni;
|
||||
u16 reserved_tag;
|
||||
u32 started_request_count;
|
||||
u32 assigned_device_count;
|
||||
u32 not_ready_reason;
|
||||
struct isci_phy *phy_table[SCI_MAX_PHYS];
|
||||
struct isci_host *owning_controller;
|
||||
struct sci_timer timer;
|
||||
struct scu_port_task_scheduler_registers __iomem *port_task_scheduler_registers;
|
||||
/* XXX rework: only one register, no need to replicate per-port */
|
||||
u32 __iomem *port_pe_configuration_register;
|
||||
struct scu_viit_entry __iomem *viit_registers;
|
||||
};
|
||||
|
||||
enum sci_port_not_ready_reason_code {
|
||||
SCIC_PORT_NOT_READY_NO_ACTIVE_PHYS,
|
||||
SCIC_PORT_NOT_READY_HARD_RESET_REQUESTED,
|
||||
SCIC_PORT_NOT_READY_INVALID_PORT_CONFIGURATION,
|
||||
SCIC_PORT_NOT_READY_RECONFIGURING,
|
||||
|
||||
SCIC_PORT_NOT_READY_REASON_CODE_MAX
|
||||
};
|
||||
|
||||
struct sci_port_end_point_properties {
|
||||
struct sci_sas_address sas_address;
|
||||
struct sci_phy_proto protocols;
|
||||
};
|
||||
|
||||
struct sci_port_properties {
|
||||
u32 index;
|
||||
struct sci_port_end_point_properties local;
|
||||
struct sci_port_end_point_properties remote;
|
||||
u32 phy_mask;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum sci_port_states - This enumeration depicts all the states for the
|
||||
* common port state machine.
|
||||
*
|
||||
*
|
||||
*/
|
||||
enum sci_port_states {
|
||||
/**
|
||||
* This state indicates that the port has successfully been stopped.
|
||||
* In this state no new IO operations are permitted.
|
||||
* This state is entered from the STOPPING state.
|
||||
*/
|
||||
SCI_PORT_STOPPED,
|
||||
|
||||
/**
|
||||
* This state indicates that the port is in the process of stopping.
|
||||
* In this state no new IO operations are permitted, but existing IO
|
||||
* operations are allowed to complete.
|
||||
* This state is entered from the READY state.
|
||||
*/
|
||||
SCI_PORT_STOPPING,
|
||||
|
||||
/**
|
||||
* This state indicates the port is now ready. Thus, the user is
|
||||
* able to perform IO operations on this port.
|
||||
* This state is entered from the STARTING state.
|
||||
*/
|
||||
SCI_PORT_READY,
|
||||
|
||||
/**
|
||||
* The substate where the port is started and ready but has no
|
||||
* active phys.
|
||||
*/
|
||||
SCI_PORT_SUB_WAITING,
|
||||
|
||||
/**
|
||||
* The substate where the port is started and ready and there is
|
||||
* at least one phy operational.
|
||||
*/
|
||||
SCI_PORT_SUB_OPERATIONAL,
|
||||
|
||||
/**
|
||||
* The substate where the port is started and there was an
|
||||
* add/remove phy event. This state is only used in Automatic
|
||||
* Port Configuration Mode (APC)
|
||||
*/
|
||||
SCI_PORT_SUB_CONFIGURING,
|
||||
|
||||
/**
|
||||
* This state indicates the port is in the process of performing a hard
|
||||
* reset. Thus, the user is unable to perform IO operations on this
|
||||
* port.
|
||||
* This state is entered from the READY state.
|
||||
*/
|
||||
SCI_PORT_RESETTING,
|
||||
|
||||
/**
|
||||
* This state indicates the port has failed a reset request. This state
|
||||
* is entered when a port reset request times out.
|
||||
* This state is entered from the RESETTING state.
|
||||
*/
|
||||
SCI_PORT_FAILED,
|
||||
|
||||
|
||||
};
|
||||
|
||||
static inline void sci_port_decrement_request_count(struct isci_port *iport)
|
||||
{
|
||||
if (WARN_ONCE(iport->started_request_count == 0,
|
||||
"%s: tried to decrement started_request_count past 0!?",
|
||||
__func__))
|
||||
/* pass */;
|
||||
else
|
||||
iport->started_request_count--;
|
||||
}
|
||||
|
||||
#define sci_port_active_phy(port, phy) \
|
||||
(((port)->active_phy_mask & (1 << (phy)->phy_index)) != 0)
|
||||
|
||||
void sci_port_construct(
|
||||
struct isci_port *iport,
|
||||
u8 port_index,
|
||||
struct isci_host *ihost);
|
||||
|
||||
enum sci_status sci_port_start(struct isci_port *iport);
|
||||
enum sci_status sci_port_stop(struct isci_port *iport);
|
||||
|
||||
enum sci_status sci_port_add_phy(
|
||||
struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
|
||||
enum sci_status sci_port_remove_phy(
|
||||
struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
|
||||
void sci_port_setup_transports(
|
||||
struct isci_port *iport,
|
||||
u32 device_id);
|
||||
|
||||
void isci_port_bcn_enable(struct isci_host *, struct isci_port *);
|
||||
|
||||
void sci_port_deactivate_phy(
|
||||
struct isci_port *iport,
|
||||
struct isci_phy *iphy,
|
||||
bool do_notify_user);
|
||||
|
||||
bool sci_port_link_detected(
|
||||
struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
|
||||
enum sci_status sci_port_link_up(struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
enum sci_status sci_port_link_down(struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
|
||||
struct isci_request;
|
||||
struct isci_remote_device;
|
||||
enum sci_status sci_port_start_io(
|
||||
struct isci_port *iport,
|
||||
struct isci_remote_device *idev,
|
||||
struct isci_request *ireq);
|
||||
|
||||
enum sci_status sci_port_complete_io(
|
||||
struct isci_port *iport,
|
||||
struct isci_remote_device *idev,
|
||||
struct isci_request *ireq);
|
||||
|
||||
enum sas_linkrate sci_port_get_max_allowed_speed(
|
||||
struct isci_port *iport);
|
||||
|
||||
void sci_port_broadcast_change_received(
|
||||
struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
|
||||
bool sci_port_is_valid_phy_assignment(
|
||||
struct isci_port *iport,
|
||||
u32 phy_index);
|
||||
|
||||
void sci_port_get_sas_address(
|
||||
struct isci_port *iport,
|
||||
struct sci_sas_address *sas_address);
|
||||
|
||||
void sci_port_get_attached_sas_address(
|
||||
struct isci_port *iport,
|
||||
struct sci_sas_address *sas_address);
|
||||
|
||||
enum isci_status isci_port_get_state(
|
||||
struct isci_port *isci_port);
|
||||
|
||||
void isci_port_formed(struct asd_sas_phy *);
|
||||
void isci_port_deformed(struct asd_sas_phy *);
|
||||
|
||||
void isci_port_init(
|
||||
struct isci_port *port,
|
||||
struct isci_host *host,
|
||||
int index);
|
||||
|
||||
int isci_port_perform_hard_reset(struct isci_host *ihost, struct isci_port *iport,
|
||||
struct isci_phy *iphy);
|
||||
#endif /* !defined(_ISCI_PORT_H_) */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*/
|
||||
|
||||
/* probe_roms - scan for oem parameters */
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/efi.h>
|
||||
#include <asm/probe_roms.h>
|
||||
|
||||
#include "isci.h"
|
||||
#include "task.h"
|
||||
#include "probe_roms.h"
|
||||
|
||||
static efi_char16_t isci_efivar_name[] =
|
||||
{'R', 's', 't', 'S', 'c', 'u', 'O'};
|
||||
|
||||
struct isci_orom *isci_request_oprom(struct pci_dev *pdev)
|
||||
{
|
||||
void __iomem *oprom = pci_map_biosrom(pdev);
|
||||
struct isci_orom *rom = NULL;
|
||||
size_t len, i;
|
||||
int j;
|
||||
char oem_sig[4];
|
||||
struct isci_oem_hdr oem_hdr;
|
||||
u8 *tmp, sum;
|
||||
|
||||
if (!oprom)
|
||||
return NULL;
|
||||
|
||||
len = pci_biosrom_size(pdev);
|
||||
rom = devm_kzalloc(&pdev->dev, sizeof(*rom), GFP_KERNEL);
|
||||
if (!rom) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Unable to allocate memory for orom\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < len && rom; i += ISCI_OEM_SIG_SIZE) {
|
||||
memcpy_fromio(oem_sig, oprom + i, ISCI_OEM_SIG_SIZE);
|
||||
|
||||
/* we think we found the OEM table */
|
||||
if (memcmp(oem_sig, ISCI_OEM_SIG, ISCI_OEM_SIG_SIZE) == 0) {
|
||||
size_t copy_len;
|
||||
|
||||
memcpy_fromio(&oem_hdr, oprom + i, sizeof(oem_hdr));
|
||||
|
||||
copy_len = min(oem_hdr.len - sizeof(oem_hdr),
|
||||
sizeof(*rom));
|
||||
|
||||
memcpy_fromio(rom,
|
||||
oprom + i + sizeof(oem_hdr),
|
||||
copy_len);
|
||||
|
||||
/* calculate checksum */
|
||||
tmp = (u8 *)&oem_hdr;
|
||||
for (j = 0, sum = 0; j < sizeof(oem_hdr); j++, tmp++)
|
||||
sum += *tmp;
|
||||
|
||||
tmp = (u8 *)rom;
|
||||
for (j = 0; j < sizeof(*rom); j++, tmp++)
|
||||
sum += *tmp;
|
||||
|
||||
if (sum != 0) {
|
||||
dev_warn(&pdev->dev,
|
||||
"OEM table checksum failed\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
/* keep going if that's not the oem param table */
|
||||
if (memcmp(rom->hdr.signature,
|
||||
ISCI_ROM_SIG,
|
||||
ISCI_ROM_SIG_SIZE) != 0)
|
||||
continue;
|
||||
|
||||
dev_info(&pdev->dev,
|
||||
"OEM parameter table found in OROM\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i >= len) {
|
||||
dev_err(&pdev->dev, "oprom parse error\n");
|
||||
devm_kfree(&pdev->dev, rom);
|
||||
rom = NULL;
|
||||
}
|
||||
pci_unmap_biosrom(oprom);
|
||||
|
||||
return rom;
|
||||
}
|
||||
|
||||
enum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem,
|
||||
struct isci_orom *orom, int scu_index)
|
||||
{
|
||||
/* check for valid inputs */
|
||||
if (scu_index < 0 || scu_index >= SCI_MAX_CONTROLLERS ||
|
||||
scu_index > orom->hdr.num_elements || !oem)
|
||||
return -EINVAL;
|
||||
|
||||
*oem = orom->ctrl[scu_index];
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw)
|
||||
{
|
||||
struct isci_orom *orom = NULL, *data;
|
||||
int i, j;
|
||||
|
||||
if (request_firmware(&fw, ISCI_FW_NAME, &pdev->dev) != 0)
|
||||
return NULL;
|
||||
|
||||
if (fw->size < sizeof(*orom))
|
||||
goto out;
|
||||
|
||||
data = (struct isci_orom *)fw->data;
|
||||
|
||||
if (strncmp(ISCI_ROM_SIG, data->hdr.signature,
|
||||
strlen(ISCI_ROM_SIG)) != 0)
|
||||
goto out;
|
||||
|
||||
orom = devm_kzalloc(&pdev->dev, fw->size, GFP_KERNEL);
|
||||
if (!orom)
|
||||
goto out;
|
||||
|
||||
memcpy(orom, fw->data, fw->size);
|
||||
|
||||
if (is_c0(pdev))
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* deprecated: override default amp_control for pre-preproduction
|
||||
* silicon revisions
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(orom->ctrl); i++)
|
||||
for (j = 0; j < ARRAY_SIZE(orom->ctrl[i].phys); j++) {
|
||||
orom->ctrl[i].phys[j].afe_tx_amp_control0 = 0xe7c03;
|
||||
orom->ctrl[i].phys[j].afe_tx_amp_control1 = 0xe7c03;
|
||||
orom->ctrl[i].phys[j].afe_tx_amp_control2 = 0xe7c03;
|
||||
orom->ctrl[i].phys[j].afe_tx_amp_control3 = 0xe7c03;
|
||||
}
|
||||
out:
|
||||
release_firmware(fw);
|
||||
|
||||
return orom;
|
||||
}
|
||||
|
||||
static struct efi *get_efi(void)
|
||||
{
|
||||
#ifdef CONFIG_EFI
|
||||
return &efi;
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
struct isci_orom *isci_get_efi_var(struct pci_dev *pdev)
|
||||
{
|
||||
efi_status_t status;
|
||||
struct isci_orom *rom;
|
||||
struct isci_oem_hdr *oem_hdr;
|
||||
u8 *tmp, sum;
|
||||
int j;
|
||||
ssize_t data_len;
|
||||
u8 *efi_data;
|
||||
u32 efi_attrib = 0;
|
||||
|
||||
data_len = 1024;
|
||||
efi_data = devm_kzalloc(&pdev->dev, data_len, GFP_KERNEL);
|
||||
if (!efi_data) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Unable to allocate memory for EFI data\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
rom = (struct isci_orom *)(efi_data + sizeof(struct isci_oem_hdr));
|
||||
|
||||
if (get_efi())
|
||||
status = get_efi()->get_variable(isci_efivar_name,
|
||||
&ISCI_EFI_VENDOR_GUID,
|
||||
&efi_attrib,
|
||||
&data_len,
|
||||
efi_data);
|
||||
else
|
||||
status = EFI_NOT_FOUND;
|
||||
|
||||
if (status != EFI_SUCCESS) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Unable to obtain EFI var data for OEM parms\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
oem_hdr = (struct isci_oem_hdr *)efi_data;
|
||||
|
||||
if (memcmp(oem_hdr->sig, ISCI_OEM_SIG, ISCI_OEM_SIG_SIZE) != 0) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Invalid OEM header signature\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* calculate checksum */
|
||||
tmp = (u8 *)efi_data;
|
||||
for (j = 0, sum = 0; j < (sizeof(*oem_hdr) + sizeof(*rom)); j++, tmp++)
|
||||
sum += *tmp;
|
||||
|
||||
if (sum != 0) {
|
||||
dev_warn(&pdev->dev,
|
||||
"OEM table checksum failed\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (memcmp(rom->hdr.signature,
|
||||
ISCI_ROM_SIG,
|
||||
ISCI_ROM_SIG_SIZE) != 0) {
|
||||
dev_warn(&pdev->dev,
|
||||
"Invalid OEM table signature\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return rom;
|
||||
}
|
||||
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _ISCI_PROBE_ROMS_H_
|
||||
#define _ISCI_PROBE_ROMS_H_
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/efi.h>
|
||||
#include "isci.h"
|
||||
|
||||
#define SCIC_SDS_PARM_NO_SPEED 0
|
||||
|
||||
/* generation 1 (i.e. 1.5 Gb/s) */
|
||||
#define SCIC_SDS_PARM_GEN1_SPEED 1
|
||||
|
||||
/* generation 2 (i.e. 3.0 Gb/s) */
|
||||
#define SCIC_SDS_PARM_GEN2_SPEED 2
|
||||
|
||||
/* generation 3 (i.e. 6.0 Gb/s) */
|
||||
#define SCIC_SDS_PARM_GEN3_SPEED 3
|
||||
#define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
|
||||
|
||||
/* parameters that can be set by module parameters */
|
||||
struct sci_user_parameters {
|
||||
struct sci_phy_user_params {
|
||||
/**
|
||||
* This field specifies the NOTIFY (ENABLE SPIN UP) primitive
|
||||
* insertion frequency for this phy index.
|
||||
*/
|
||||
u32 notify_enable_spin_up_insertion_frequency;
|
||||
|
||||
/**
|
||||
* This method specifies the number of transmitted DWORDs within which
|
||||
* to transmit a single ALIGN primitive. This value applies regardless
|
||||
* of what type of device is attached or connection state. A value of
|
||||
* 0 indicates that no ALIGN primitives will be inserted.
|
||||
*/
|
||||
u16 align_insertion_frequency;
|
||||
|
||||
/**
|
||||
* This method specifies the number of transmitted DWORDs within which
|
||||
* to transmit 2 ALIGN primitives. This applies for SAS connections
|
||||
* only. A minimum value of 3 is required for this field.
|
||||
*/
|
||||
u16 in_connection_align_insertion_frequency;
|
||||
|
||||
/**
|
||||
* This field indicates the maximum speed generation to be utilized
|
||||
* by phys in the supplied port.
|
||||
* - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
|
||||
* - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
|
||||
* - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
|
||||
*/
|
||||
u8 max_speed_generation;
|
||||
|
||||
} phys[SCI_MAX_PHYS];
|
||||
|
||||
/**
|
||||
* This field specifies the maximum number of direct attached devices
|
||||
* that can have power supplied to them simultaneously.
|
||||
*/
|
||||
u8 max_number_concurrent_device_spin_up;
|
||||
|
||||
/**
|
||||
* This field specifies the number of seconds to allow a phy to consume
|
||||
* power before yielding to another phy.
|
||||
*
|
||||
*/
|
||||
u8 phy_spin_up_delay_interval;
|
||||
|
||||
/**
|
||||
* These timer values specifies how long a link will remain open with no
|
||||
* activity in increments of a microsecond, it can be in increments of
|
||||
* 100 microseconds if the upper most bit is set.
|
||||
*
|
||||
*/
|
||||
u16 stp_inactivity_timeout;
|
||||
u16 ssp_inactivity_timeout;
|
||||
|
||||
/**
|
||||
* These timer values specifies how long a link will remain open in increments
|
||||
* of 100 microseconds.
|
||||
*
|
||||
*/
|
||||
u16 stp_max_occupancy_timeout;
|
||||
u16 ssp_max_occupancy_timeout;
|
||||
|
||||
/**
|
||||
* This timer value specifies how long a link will remain open with no
|
||||
* outbound traffic in increments of a microsecond.
|
||||
*
|
||||
*/
|
||||
u8 no_outbound_task_timeout;
|
||||
|
||||
};
|
||||
|
||||
#define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
|
||||
#define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
|
||||
#define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
|
||||
|
||||
struct sci_oem_params;
|
||||
int sci_oem_parameters_validate(struct sci_oem_params *oem);
|
||||
|
||||
struct isci_orom;
|
||||
struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
|
||||
enum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem,
|
||||
struct isci_orom *orom, int scu_index);
|
||||
struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
|
||||
struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
|
||||
|
||||
struct isci_oem_hdr {
|
||||
u8 sig[4];
|
||||
u8 rev_major;
|
||||
u8 rev_minor;
|
||||
u16 len;
|
||||
u8 checksum;
|
||||
u8 reserved1;
|
||||
u16 reserved2;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#else
|
||||
#define SCI_MAX_PORTS 4
|
||||
#define SCI_MAX_PHYS 4
|
||||
#define SCI_MAX_CONTROLLERS 2
|
||||
#endif
|
||||
|
||||
#define ISCI_FW_NAME "isci/isci_firmware.bin"
|
||||
|
||||
#define ROMSIGNATURE 0xaa55
|
||||
|
||||
#define ISCI_OEM_SIG "$OEM"
|
||||
#define ISCI_OEM_SIG_SIZE 4
|
||||
#define ISCI_ROM_SIG "ISCUOEMB"
|
||||
#define ISCI_ROM_SIG_SIZE 8
|
||||
|
||||
#define ISCI_EFI_VENDOR_GUID \
|
||||
EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
|
||||
0x1a, 0x04, 0xc6)
|
||||
#define ISCI_EFI_VAR_NAME "RstScuO"
|
||||
|
||||
/* Allowed PORT configuration modes APC Automatic PORT configuration mode is
|
||||
* defined by the OEM configuration parameters providing no PHY_MASK parameters
|
||||
* for any PORT. i.e. There are no phys assigned to any of the ports at start.
|
||||
* MPC Manual PORT configuration mode is defined by the OEM configuration
|
||||
* parameters providing a PHY_MASK value for any PORT. It is assumed that any
|
||||
* PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
|
||||
* A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
|
||||
* being assigned is sufficient to declare manual PORT configuration.
|
||||
*/
|
||||
enum sci_port_configuration_mode {
|
||||
SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0,
|
||||
SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1
|
||||
};
|
||||
|
||||
struct sci_bios_oem_param_block_hdr {
|
||||
uint8_t signature[ISCI_ROM_SIG_SIZE];
|
||||
uint16_t total_block_length;
|
||||
uint8_t hdr_length;
|
||||
uint8_t version;
|
||||
uint8_t preboot_source;
|
||||
uint8_t num_elements;
|
||||
uint16_t element_length;
|
||||
uint8_t reserved[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct sci_oem_params {
|
||||
struct {
|
||||
uint8_t mode_type;
|
||||
uint8_t max_concurrent_dev_spin_up;
|
||||
uint8_t do_enable_ssc;
|
||||
uint8_t reserved;
|
||||
} controller;
|
||||
|
||||
struct {
|
||||
uint8_t phy_mask;
|
||||
} ports[SCI_MAX_PORTS];
|
||||
|
||||
struct sci_phy_oem_params {
|
||||
struct {
|
||||
uint32_t high;
|
||||
uint32_t low;
|
||||
} sas_address;
|
||||
|
||||
uint32_t afe_tx_amp_control0;
|
||||
uint32_t afe_tx_amp_control1;
|
||||
uint32_t afe_tx_amp_control2;
|
||||
uint32_t afe_tx_amp_control3;
|
||||
} phys[SCI_MAX_PHYS];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct isci_orom {
|
||||
struct sci_bios_oem_param_block_hdr hdr;
|
||||
struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user