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Merge branch 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim: AS I commented, this makes <mach/*.h> local so that they could be removed. * 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (26 commits) ARM: S3C64XX: Fix missing header error with CONFIG_CPU_IDLE enabled ARM: S3C64XX: make regs-syscon-power.h local ARM: S3C64XX: make regs-sys.h local ARM: S3C64XX: make regs-srom.h local ARM: S3C64XX: make regs-modem.h local ARM: S3C64XX: make regs-gpio-memport.h local ARM: S3C64XX: make crag6410.h local ARM: S3C24XX: remove dsc.c and make regs-dsc.h local ARM: S3C24XX: remove idle.h ARM: S3C2412: cleanup regs-s3c2412.h ARM: S3C2416: remove regs-s3c2416-mem.h and regs-s3c2416.h ARM: S3C24XX: make vr1000-cpld.h, vr1000-irq.h and vr1000-map.h local ARM: S3C24XX: make otom-map.h local ARM: S3C24XX: make osiris-cpld.h and osiris-map.h local ARM: S3C24XX: make h1940.h and h1940-latch.h local ARM: S3C24XX: make gta02.h local ARM: S3C24XX: make bast-cpld.h, bast-irq.h and bast-map.h local ARM: S3C24XX: make anubis-cpld, anubis-irq and anubis-map local ARM: SAMSUNG: cleanup mach/gpio-fns.h gpio-track.h and gpio-nrs.h ARM: SAMSUNG: cleanup mach/regs-audss.h file ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -36,7 +36,6 @@
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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#include <mach/regs-gpio.h>
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#include <mach/pmu.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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@@ -64,4 +64,24 @@ extern struct smp_operations exynos_smp_ops;
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extern void exynos_cpu_die(unsigned int cpu);
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/* PMU(Power Management Unit) support */
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#define PMU_TABLE_END NULL
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enum sys_powerdown {
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SYS_AFTR,
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SYS_LPA,
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SYS_SLEEP,
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NUM_SYS_POWERDOWN,
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};
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extern unsigned long l2x0_regs_phys;
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struct exynos_pmu_conf {
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void __iomem *reg;
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unsigned int val[NUM_SYS_POWERDOWN];
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};
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extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
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extern void s3c_cpu_resume(void);
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#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
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@@ -23,10 +23,11 @@
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#include <asm/cpuidle.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <mach/pmu.h>
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#include <plat/cpu.h>
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#include "common.h"
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#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
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@@ -21,7 +21,8 @@
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#include <mach/map.h>
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#include <mach/dma.h>
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#include <mach/irqs.h>
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#include <mach/regs-audss.h>
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#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
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static int exynos4_cfg_i2s(struct platform_device *pdev)
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{
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@@ -1,34 +0,0 @@
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/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS4210 - PMU(Power Management Unit) support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_PMU_H
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#define __ASM_ARCH_PMU_H __FILE__
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#define PMU_TABLE_END NULL
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enum sys_powerdown {
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SYS_AFTR,
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SYS_LPA,
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SYS_SLEEP,
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NUM_SYS_POWERDOWN,
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};
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extern unsigned long l2x0_regs_phys;
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struct exynos_pmu_conf {
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void __iomem *reg;
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unsigned int val[NUM_SYS_POWERDOWN];
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};
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extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
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extern void s3c_cpu_resume(void);
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#endif /* __ASM_ARCH_PMU_H */
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@@ -1,18 +0,0 @@
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/* arch/arm/mach-exynos4/include/mach/regs-audss.h
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*
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* Copyright (c) 2011 Samsung Electronics
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* http://www.samsung.com
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*
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* Exynos4 Audio SubSystem clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_REGS_AUDSS_H
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#define __PLAT_REGS_AUDSS_H __FILE__
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#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
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#endif /* _PLAT_REGS_AUDSS_H */
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@@ -34,7 +34,8 @@
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <mach/pm-core.h>
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#include <mach/pmu.h>
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#include "common.h"
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static struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
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@@ -14,7 +14,8 @@
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#include <linux/bug.h>
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#include <mach/regs-clock.h>
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#include <mach/pmu.h>
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#include "common.h"
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static struct exynos_pmu_conf *exynos_pmu_config;
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@@ -9,8 +9,6 @@ obj-m :=
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obj-n :=
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obj- :=
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obj-$(CONFIG_CPU_S3C2440) += dsc.o
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obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
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obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
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@@ -1,54 +0,0 @@
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/* linux/arch/arm/mach-s3c2440/dsc.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C2440 Drive Strength Control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-dsc.h>
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#include <plat/cpu.h>
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#include <plat/s3c244x.h>
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int s3c2440_set_dsc(unsigned int pin, unsigned int value)
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{
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void __iomem *base;
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unsigned long val;
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unsigned long flags;
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unsigned long mask;
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base = (pin & S3C2440_SELECT_DSC1) ? S3C2440_DSC1 : S3C2440_DSC0;
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mask = 3 << S3C2440_DSC_GETSHIFT(pin);
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local_irq_save(flags);
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val = __raw_readl(base);
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val &= ~mask;
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val |= value & mask;
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__raw_writel(val, base);
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(s3c2440_set_dsc);
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@@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2005 Simtec Electronics
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* http://www.simtec.co.uk/products/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ANUBIS - CPLD control constants
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* ANUBIS - IRQ Number definitions
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* ANUBIS - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_S3C24XX_ANUBIS_H
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#define __MACH_S3C24XX_ANUBIS_H __FILE__
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/* CTRL2 - NAND WP control, IDE Reset assert/check */
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#define ANUBIS_CTRL1_NANDSEL (0x3)
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/* IDREG - revision */
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#define ANUBIS_IDREG_REVMASK (0x7)
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/* irq */
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#define ANUBIS_IRQ_IDE0 IRQ_EINT2
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#define ANUBIS_IRQ_IDE1 IRQ_EINT3
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#define ANUBIS_IRQ_ASIX IRQ_EINT1
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/* map */
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/* start peripherals off after the S3C2410 */
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#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
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#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
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/* we put the CPLD registers next, to get them out of the way */
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#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
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#define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD
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#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
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#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23))
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#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
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#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
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#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
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#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
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#endif /* __MACH_S3C24XX_ANUBIS_H */
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@@ -25,8 +25,8 @@
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#include <asm/mach/irq.h>
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#include <mach/map.h>
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#include <mach/bast-map.h>
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#include <mach/bast-irq.h>
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#include "bast.h"
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/* IDE ports */
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@@ -34,12 +34,10 @@ static struct pata_platform_info bast_ide_platdata = {
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.ioport_shift = 5,
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};
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#define IDE_CS S3C2410_CS5
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static struct resource bast_ide0_resource[] = {
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[0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
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[1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
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[2] = DEFINE_RES_IRQ(IRQ_IDE0),
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[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
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[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
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[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE0),
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};
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static struct platform_device bast_device_ide0 = {
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@@ -55,9 +53,9 @@ static struct platform_device bast_device_ide0 = {
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};
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static struct resource bast_ide1_resource[] = {
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[0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
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[1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
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[2] = DEFINE_RES_IRQ(IRQ_IDE1),
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[0] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
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[1] = DEFINE_RES_MEM(BAST_IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
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[2] = DEFINE_RES_IRQ(BAST_IRQ_IDE1),
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};
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static struct platform_device bast_device_ide1 = {
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@@ -27,27 +27,20 @@
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#include <linux/device.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <mach/regs-irq.h>
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#include <mach/bast-map.h>
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#include <mach/bast-irq.h>
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#include <plat/irq.h>
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#if 0
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#include <asm/debug-ll.h>
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#endif
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#include "bast.h"
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#define irqdbf(x...)
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#define irqdbf2(x...)
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/* handle PC104 ISA interrupts from the system CPLD */
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/* table of ISA irq nos to the relevant mask... zero means
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@@ -87,7 +80,7 @@ bast_pc104_mask(struct irq_data *data)
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static void
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bast_pc104_maskack(struct irq_data *data)
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{
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struct irq_desc *desc = irq_desc + IRQ_ISA;
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struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
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bast_pc104_mask(data);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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@@ -122,7 +115,7 @@ bast_irq_pc104_demux(unsigned int irq,
|
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if (unlikely(stat == 0)) {
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/* ack if we get an irq with nothing (ie, startup) */
|
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desc = irq_desc + IRQ_ISA;
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desc = irq_desc + BAST_IRQ_ISA;
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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} else {
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/* handle the IRQ */
|
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@@ -147,7 +140,7 @@ static __init int bast_irq_init(void)
|
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|
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__raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
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irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
|
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irq_set_chained_handler(BAST_IRQ_ISA, bast_irq_pc104_demux);
|
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|
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/* register our IRQs */
|
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|
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|
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@@ -0,0 +1,197 @@
|
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/*
|
||||
* Copyright (c) 2003-2004 Simtec Electronics
|
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* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* BAST - CPLD control constants
|
||||
* BAST - IRQ Number definitions
|
||||
* BAST - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
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#ifndef __MACH_S3C24XX_BAST_H
|
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#define __MACH_S3C24XX_BAST_H __FILE__
|
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|
||||
/* CTRL1 - Audio LR routing */
|
||||
|
||||
#define BAST_CPLD_CTRL1_LRCOFF (0x00)
|
||||
#define BAST_CPLD_CTRL1_LRCADC (0x01)
|
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#define BAST_CPLD_CTRL1_LRCDAC (0x02)
|
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#define BAST_CPLD_CTRL1_LRCARM (0x03)
|
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#define BAST_CPLD_CTRL1_LRMASK (0x03)
|
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|
||||
/* CTRL2 - NAND WP control, IDE Reset assert/check */
|
||||
|
||||
#define BAST_CPLD_CTRL2_WNAND (0x04)
|
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#define BAST_CPLD_CTLR2_IDERST (0x08)
|
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|
||||
/* CTRL3 - rom write control, CPLD identity */
|
||||
|
||||
#define BAST_CPLD_CTRL3_IDMASK (0x0e)
|
||||
#define BAST_CPLD_CTRL3_ROMWEN (0x01)
|
||||
|
||||
/* CTRL4 - 8bit LCD interface control/status */
|
||||
|
||||
#define BAST_CPLD_CTRL4_LLAT (0x01)
|
||||
#define BAST_CPLD_CTRL4_LCDRW (0x02)
|
||||
#define BAST_CPLD_CTRL4_LCDCMD (0x04)
|
||||
#define BAST_CPLD_CTRL4_LCDE2 (0x01)
|
||||
|
||||
/* CTRL5 - DMA routing */
|
||||
|
||||
#define BAST_CPLD_DMA0_PRIIDE (0)
|
||||
#define BAST_CPLD_DMA0_SECIDE (1)
|
||||
#define BAST_CPLD_DMA0_ISA15 (2)
|
||||
#define BAST_CPLD_DMA0_ISA36 (3)
|
||||
|
||||
#define BAST_CPLD_DMA1_PRIIDE (0 << 2)
|
||||
#define BAST_CPLD_DMA1_SECIDE (1 << 2)
|
||||
#define BAST_CPLD_DMA1_ISA15 (2 << 2)
|
||||
#define BAST_CPLD_DMA1_ISA36 (3 << 2)
|
||||
|
||||
/* irq numbers to onboard peripherals */
|
||||
|
||||
#define BAST_IRQ_USBOC IRQ_EINT18
|
||||
#define BAST_IRQ_IDE0 IRQ_EINT16
|
||||
#define BAST_IRQ_IDE1 IRQ_EINT17
|
||||
#define BAST_IRQ_PCSERIAL1 IRQ_EINT15
|
||||
#define BAST_IRQ_PCSERIAL2 IRQ_EINT14
|
||||
#define BAST_IRQ_PCPARALLEL IRQ_EINT13
|
||||
#define BAST_IRQ_ASIX IRQ_EINT11
|
||||
#define BAST_IRQ_DM9000 IRQ_EINT10
|
||||
#define BAST_IRQ_ISA IRQ_EINT9
|
||||
#define BAST_IRQ_SMALERT IRQ_EINT8
|
||||
|
||||
/* map */
|
||||
|
||||
/*
|
||||
* ok, we've used up to 0x13000000, now we need to find space for the
|
||||
* peripherals that live in the nGCS[x] areas, which are quite numerous
|
||||
* in their space. We also have the board's CPLD to find register space
|
||||
* for.
|
||||
*/
|
||||
|
||||
#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
|
||||
|
||||
/* we put the CPLD registers next, to get them out of the way */
|
||||
|
||||
#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
|
||||
#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
|
||||
|
||||
#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
|
||||
#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
|
||||
|
||||
#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
|
||||
#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
|
||||
|
||||
#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
|
||||
#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
|
||||
|
||||
/* next, we have the PC104 ISA interrupt registers */
|
||||
|
||||
#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
|
||||
#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
|
||||
|
||||
#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
|
||||
#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
|
||||
|
||||
#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
|
||||
#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
|
||||
|
||||
#define BAST_PA_LCD_RCMD1 (0x8800000)
|
||||
#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
|
||||
|
||||
#define BAST_PA_LCD_WCMD1 (0x8000000)
|
||||
#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
|
||||
|
||||
#define BAST_PA_LCD_RDATA1 (0x9800000)
|
||||
#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
|
||||
|
||||
#define BAST_PA_LCD_WDATA1 (0x9000000)
|
||||
#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
|
||||
|
||||
#define BAST_PA_LCD_RCMD2 (0xA800000)
|
||||
#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
|
||||
|
||||
#define BAST_PA_LCD_WCMD2 (0xA000000)
|
||||
#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
|
||||
|
||||
#define BAST_PA_LCD_RDATA2 (0xB800000)
|
||||
#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
|
||||
|
||||
#define BAST_PA_LCD_WDATA2 (0xB000000)
|
||||
#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
|
||||
|
||||
|
||||
/*
|
||||
* 0xE0000000 contains the IO space that is split by speed and
|
||||
* whether the access is for 8 or 16bit IO... this ensures that
|
||||
* the correct access is made
|
||||
*
|
||||
* 0x10000000 of space, partitioned as so:
|
||||
*
|
||||
* 0x00000000 to 0x04000000 8bit, slow
|
||||
* 0x04000000 to 0x08000000 16bit, slow
|
||||
* 0x08000000 to 0x0C000000 16bit, net
|
||||
* 0x0C000000 to 0x10000000 16bit, fast
|
||||
*
|
||||
* each of these spaces has the following in:
|
||||
*
|
||||
* 0x00000000 to 0x01000000 16MB ISA IO space
|
||||
* 0x01000000 to 0x02000000 16MB ISA memory space
|
||||
* 0x02000000 to 0x02100000 1MB IDE primary channel
|
||||
* 0x02100000 to 0x02200000 1MB IDE primary channel aux
|
||||
* 0x02200000 to 0x02400000 1MB IDE secondary channel
|
||||
* 0x02300000 to 0x02400000 1MB IDE secondary channel aux
|
||||
* 0x02400000 to 0x02500000 1MB ASIX ethernet controller
|
||||
* 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
|
||||
* 0x02600000 to 0x02700000 1MB PC SuperIO controller
|
||||
*
|
||||
* the phyiscal layout of the zones are:
|
||||
* nGCS2 - 8bit, slow
|
||||
* nGCS3 - 16bit, slow
|
||||
* nGCS4 - 16bit, net
|
||||
* nGCS5 - 16bit, fast
|
||||
*/
|
||||
|
||||
#define BAST_VA_MULTISPACE (0xE0000000)
|
||||
|
||||
#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
|
||||
#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
|
||||
#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
|
||||
#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
|
||||
#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
|
||||
#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
|
||||
#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
|
||||
#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
|
||||
#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
|
||||
|
||||
#define BAST_VAM_CS2 (0x00000000)
|
||||
#define BAST_VAM_CS3 (0x04000000)
|
||||
#define BAST_VAM_CS4 (0x08000000)
|
||||
#define BAST_VAM_CS5 (0x0C000000)
|
||||
|
||||
/* physical offset addresses for the peripherals */
|
||||
|
||||
#define BAST_PA_ISAIO (0x00000000)
|
||||
#define BAST_PA_ASIXNET (0x01000000)
|
||||
#define BAST_PA_SUPERIO (0x01800000)
|
||||
#define BAST_PA_IDEPRI (0x02000000)
|
||||
#define BAST_PA_IDEPRIAUX (0x02800000)
|
||||
#define BAST_PA_IDESEC (0x03000000)
|
||||
#define BAST_PA_IDESECAUX (0x03800000)
|
||||
#define BAST_PA_ISAMEM (0x04000000)
|
||||
#define BAST_PA_DM9000 (0x05000000)
|
||||
|
||||
/* some configurations for the peripherals */
|
||||
|
||||
#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
|
||||
|
||||
#define BAST_ASIXNET_CS BAST_VAM_CS5
|
||||
#define BAST_DM9000_CS BAST_VAM_CS4
|
||||
|
||||
#define BAST_IDE_CS S3C2410_CS5
|
||||
|
||||
#endif /* __MACH_S3C24XX_BAST_H */
|
||||
@@ -1,5 +1,13 @@
|
||||
#ifndef _GTA02_H
|
||||
#define _GTA02_H
|
||||
/*
|
||||
* GTA02 header
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_S3C24XX_GTA02_H
|
||||
#define __MACH_S3C24XX_GTA02_H __FILE__
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
@@ -12,4 +20,4 @@
|
||||
|
||||
#define GTA02_IRQ_PCF50633 IRQ_EINT9
|
||||
|
||||
#endif /* _GTA02_H */
|
||||
#endif /* __MACH_S3C24XX_GTA02_H */
|
||||
@@ -19,10 +19,10 @@
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/rfkill.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/h1940-latch.h>
|
||||
#include <mach/h1940.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include "h1940.h"
|
||||
|
||||
#define DRV_NAME "h1940-bt"
|
||||
|
||||
|
||||
@@ -1,20 +1,30 @@
|
||||
/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
|
||||
/*
|
||||
* Copyright 2006 Ben Dooks <ben-linux@fluff.org>
|
||||
*
|
||||
* Copyright (c) 2005 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* iPAQ H1940 series - latch definitions
|
||||
* iPAQ H1940 series definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_H1940_LATCH_H
|
||||
#define __ASM_ARCH_H1940_LATCH_H
|
||||
#ifndef __MACH_S3C24XX_H1940_H
|
||||
#define __MACH_S3C24XX_H1940_H __FILE__
|
||||
|
||||
#include <asm/gpio.h>
|
||||
#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
|
||||
#define H1940_SUSPEND_RESUMEAT (0x30081000)
|
||||
#define H1940_SUSPEND_CHECK (0x30080000)
|
||||
|
||||
extern void h1940_pm_return(void);
|
||||
extern int h1940_led_blink_set(unsigned gpio, int state,
|
||||
unsigned long *delay_on,
|
||||
unsigned long *delay_off);
|
||||
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
|
||||
|
||||
@@ -40,4 +50,4 @@
|
||||
#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
|
||||
#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
|
||||
|
||||
#endif /* __ASM_ARCH_H1940_LATCH_H */
|
||||
#endif /* __MACH_S3C24XX_H1940_H */
|
||||
@@ -1,25 +0,0 @@
|
||||
/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
|
||||
*
|
||||
* Copyright (c) 2005 Simtec Electronics
|
||||
* http://www.simtec.co.uk/products/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* ANUBIS - CPLD control constants
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_ANUBISCPLD_H
|
||||
#define __ASM_ARCH_ANUBISCPLD_H
|
||||
|
||||
/* CTRL2 - NAND WP control, IDE Reset assert/check */
|
||||
|
||||
#define ANUBIS_CTRL1_NANDSEL (0x3)
|
||||
|
||||
/* IDREG - revision */
|
||||
|
||||
#define ANUBIS_IDREG_REVMASK (0x7)
|
||||
|
||||
#endif /* __ASM_ARCH_ANUBISCPLD_H */
|
||||
@@ -1,21 +0,0 @@
|
||||
/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
|
||||
*
|
||||
* Copyright (c) 2005 Simtec Electronics
|
||||
* http://www.simtec.co.uk/products/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* ANUBIS - IRQ Number definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_ANUBISIRQ_H
|
||||
#define __ASM_ARCH_ANUBISIRQ_H
|
||||
|
||||
#define IRQ_IDE0 IRQ_EINT2
|
||||
#define IRQ_IDE1 IRQ_EINT3
|
||||
#define IRQ_ASIX IRQ_EINT1
|
||||
|
||||
#endif /* __ASM_ARCH_ANUBISIRQ_H */
|
||||
@@ -1,38 +0,0 @@
|
||||
/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
|
||||
*
|
||||
* Copyright (c) 2005 Simtec Electronics
|
||||
* http://www.simtec.co.uk/products/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* ANUBIS - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* needs arch/map.h including with this */
|
||||
|
||||
#ifndef __ASM_ARCH_ANUBISMAP_H
|
||||
#define __ASM_ARCH_ANUBISMAP_H
|
||||
|
||||
/* start peripherals off after the S3C2410 */
|
||||
|
||||
#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
|
||||
|
||||
#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
|
||||
|
||||
/* we put the CPLD registers next, to get them out of the way */
|
||||
|
||||
#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
|
||||
#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
|
||||
|
||||
#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
|
||||
#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23))
|
||||
|
||||
#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
|
||||
#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
|
||||
#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
|
||||
#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
|
||||
|
||||
#endif /* __ASM_ARCH_ANUBISMAP_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user