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Add 85xx CDS to arch/powerpc
This patch adds support for 85xx CDS support to arch/powerpc Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Andy Fleming
Kumar Gala
File diff suppressed because it is too large
Load Diff
@@ -11,13 +11,20 @@ config MPC8540_ADS
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help
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This option enables support for the MPC 8540 ADS board
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config MPC85xx_CDS
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bool "Freescale MPC85xx CDS"
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select DEFAULT_UIMAGE
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select PPC_I8259 if PCI
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help
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This option enables support for the MPC85xx CDS board
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endchoice
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config MPC8540
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bool
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select PPC_UDBG_16550
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select PPC_INDIRECT_PCI
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default y if MPC8540_ADS
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default y if MPC8540_ADS || MPC85xx_CDS
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config PPC_INDIRECT_PCI_BE
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bool
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@@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_PPC_85xx) += misc.o pci.o
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obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
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obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
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@@ -0,0 +1,359 @@
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/*
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* MPC85xx setup and early boot code plus other random bits.
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*
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* Maintained by Kumar Gala (see MAINTAINERS for contact information)
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/module.h>
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#include <linux/fsl_devices.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ipic.h>
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#include <asm/bootinfo.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/i8259.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc85xx.h"
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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static int cds_pci_slot = 2;
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static volatile u8 *cadmus;
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/*
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* Internal interrupts are all Level Sensitive, and Positive Polarity
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*
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* Note: Likely, this table and the following function should be
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* obtained and derived from the OF Device Tree.
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*/
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static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
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MPC85XX_INTERNAL_IRQ_SENSES,
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#if defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */
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#else
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0x0, /* External 0: */
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0x0, /* External 1: */
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0x0, /* External 2: */
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0x0, /* External 3: */
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#endif
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
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0x0, /* External 6: */
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0x0, /* External 7: */
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0x0, /* External 8: */
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0x0, /* External 9: */
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0x0, /* External 10: */
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#ifdef CONFIG_PCI
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2 slot 0 */
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#else
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0x0, /* External 11: */
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#endif
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};
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#ifdef CONFIG_PCI
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/*
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* interrupt routing
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*/
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int
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mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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if (!hose->index)
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{
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/* Handle PCI1 interrupts */
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char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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/* Note IRQ assignment for slots is based on which slot the elysium is
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* in -- in this setup elysium is in slot #2 (this PIRQA as first
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* interrupt on slot */
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{
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{ 0, 1, 2, 3 }, /* 16 - PMC */
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{ 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
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{ 0, 1, 2, 3 }, /* 18 - Slot 1 */
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{ 1, 2, 3, 0 }, /* 19 - Slot 2 */
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{ 2, 3, 0, 1 }, /* 20 - Slot 3 */
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{ 3, 0, 1, 2 }, /* 21 - Slot 4 */
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};
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const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
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int i, j;
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for (i = 0; i < 6; i++)
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for (j = 0; j < 4; j++)
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pci_irq_table[i][j] =
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((pci_irq_table[i][j] + 5 -
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cds_pci_slot) & 0x3) + PIRQ0A;
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return PCI_IRQ_TABLE_LOOKUP;
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} else {
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/* Handle PCI2 interrupts (if we have one) */
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char pci_irq_table[][4] =
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{
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/*
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* We only have one slot and one interrupt
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* going to PIRQA - PIRQD */
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{ PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
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};
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const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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}
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#define ARCADIA_HOST_BRIDGE_IDSEL 17
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#define ARCADIA_2ND_BRIDGE_IDSEL 3
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extern int mpc85xx_pci2_busno;
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int
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mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (mpc85xx_pci2_busno)
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if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* We explicitly do not go past the Tundra 320 Bridge */
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if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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void __init
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mpc85xx_cds_pcibios_fixup(void)
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{
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struct pci_dev *dev;
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u_char c;
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
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/*
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* U-Boot does not set the enable bits
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* for the IDE device. Force them on here.
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*/
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pci_read_config_byte(dev, 0x40, &c);
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c |= 0x03; /* IDE: Chip Enable Bits */
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pci_write_config_byte(dev, 0x40, c);
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/*
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* Since only primary interface works, force the
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* IDE function to standard primary IDE interrupt
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* w/ 8259 offset
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*/
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dev->irq = 14;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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pci_dev_put(dev);
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}
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/*
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* Force legacy USB interrupt routing
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*/
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
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dev->irq = 10;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
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pci_dev_put(dev);
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}
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if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_82C586_2, dev))) {
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dev->irq = 11;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
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pci_dev_put(dev);
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}
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}
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#endif /* CONFIG_PCI */
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void __init mpc85xx_cds_pic_init(void)
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{
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struct mpic *mpic1;
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phys_addr_t OpenPIC_PAddr;
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/* Determine the Physical Address of the OpenPIC regs */
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OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
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mpic1 = mpic_alloc(OpenPIC_PAddr,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
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mpc85xx_cds_openpic_initsenses,
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sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC ");
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BUG_ON(mpic1 == NULL);
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mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
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mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
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mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
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mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
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mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
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mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
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mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
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mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
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/* dummy mappings to get to 48 */
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mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
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mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
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mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
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mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
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/* External ints */
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mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
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mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
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mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
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mpic_init(mpic1);
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#ifdef CONFIG_PCI
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mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL);
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i8259_init(0,0);
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#endif
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}
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/*
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* Setup the architecture
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*/
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static void __init
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mpc85xx_cds_setup_arch(void)
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{
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struct device_node *cpu;
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
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cpu = of_find_node_by_type(NULL, "cpu");
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if (cpu != 0) {
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unsigned int *fp;
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fp = (int *)get_property(cpu, "clock-frequency", NULL);
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if (fp != 0)
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loops_per_jiffy = *fp / HZ;
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else
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loops_per_jiffy = 500000000 / HZ;
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of_node_put(cpu);
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}
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cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
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cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
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if (ppc_md.progress) {
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char buf[40];
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snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
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cadmus[CM_VER], cds_pci_slot);
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ppc_md.progress(buf, 0);
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}
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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add_bridge(np);
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ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mpc85xx_map_irq;
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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}
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void
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mpc85xx_cds_show_cpuinfo(struct seq_file *m)
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{
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uint pvid, svid, phid1;
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uint memsize = total_memory;
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pvid = mfspr(SPRN_PVR);
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svid = mfspr(SPRN_SVR);
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
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seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
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seq_printf(m, "SVR\t\t: 0x%x\n", svid);
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/* Display cpu Pll setting */
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phid1 = mfspr(SPRN_HID1);
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seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
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/* Display the amount of memory */
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc85xx_cds_probe(void)
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{
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/* We always match for now, eventually we should look at
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* the flat dev tree to ensure this is the board we are
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* supposed to run on
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*/
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return 1;
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}
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define_machine(mpc85xx_cds) {
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.name = "MPC85xx CDS",
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.probe = mpc85xx_cds_probe,
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.setup_arch = mpc85xx_cds_setup_arch,
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.init_IRQ = mpc85xx_cds_pic_init,
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.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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@@ -0,0 +1,43 @@
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/*
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* arch/ppc/platforms/85xx/mpc85xx_cds_common.h
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*
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* MPC85xx CDS board definitions
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __MACH_MPC85XX_CDS_H__
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#define __MACH_MPC85XX_CDS_H__
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/* CADMUS info */
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#define CADMUS_BASE (0xf8004000)
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#define CADMUS_SIZE (256)
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#define CM_VER (0)
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#define CM_CSR (1)
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#define CM_RST (2)
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/* CDS NVRAM/RTC */
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#define CDS_RTC_ADDR (0xf8000000)
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#define CDS_RTC_SIZE (8 * 1024)
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/* PCI interrupt controller */
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#define PIRQ0A MPC85xx_IRQ_EXT0
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#define PIRQ0B MPC85xx_IRQ_EXT1
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#define PIRQ0C MPC85xx_IRQ_EXT2
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#define PIRQ0D MPC85xx_IRQ_EXT3
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#define PIRQ1A MPC85xx_IRQ_EXT11
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#define NR_8259_INTS 16
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#define CPM_IRQ_OFFSET NR_8259_INTS
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#define MPC85xx_OPENPIC_IRQ_OFFSET 80
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#endif /* __MACH_MPC85XX_CDS_H__ */
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@@ -28,6 +28,9 @@
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#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
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#include <platforms/85xx/mpc8555_cds.h>
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#endif
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#ifdef CONFIG_MPC85xx_CDS
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#include <platforms/85xx/mpc85xx_cds.h>
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#endif
|
||||
#ifdef CONFIG_MPC8560_ADS
|
||||
#include <platforms/85xx/mpc8560_ads.h>
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user