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bnx2x: Supporting BCM8726 PHY
Also adding the ability to recognize the optic module and disable it if it is not authorized for safety reasons - since this feature might upset some users which are willing to take the risk, it is optional and can be disabled by setting an nvram bit (or a trivial driver patch to set this bit). This dual port PHY requires special handling if the ports are swapped. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
committed by
David S. Miller
David S. Miller
parent
4acac6a53a
commit
589abe3a0f
+12
-1
@@ -245,7 +245,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
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#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
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@@ -299,6 +299,12 @@ struct shared_feat_cfg { /* NVRAM Offset */
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u32 config; /* 0x450 */
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#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
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/* Use the values from options 47 and 48 instead of the HW default
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values */
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#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
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#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
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#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
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};
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@@ -352,6 +358,11 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
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#define PORT_FEATURE_MBA_ENABLED 0x02000000
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#define PORT_FEATURE_MFW_ENABLED 0x04000000
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/* Check the optic vendor via i2c before allowing it to be used by
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SW */
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED 0x00000000
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#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED 0x08000000
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u32 wol_config;
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/* Default is used when driver sets to "auto" mode */
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#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
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+738
-54
File diff suppressed because it is too large
Load Diff
@@ -89,6 +89,9 @@ struct link_params {
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/* phy_addr populated by the CLC */
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u8 phy_addr;
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u32 feature_config_flags;
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#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0)
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/* Device pointer passed to all callback functions */
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struct bnx2x *bp;
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};
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@@ -125,8 +128,11 @@ struct link_vars {
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/* Initialize the phy */
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u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
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/* Reset the link. Should be called when driver or interface goes down */
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u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars);
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/* Reset the link. Should be called when driver or interface goes down
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Before calling phy firmware upgrade, the reset_ext_phy should be set
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to 0 */
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u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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u8 reset_ext_phy);
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/* bnx2x_link_update should be called upon link interrupt */
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u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
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@@ -163,6 +169,10 @@ u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
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u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
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u8 driver_loaded, char data[], u32 size);
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/* bnx2x_handle_module_detect_int should be called upon module detection
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interrupt */
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void bnx2x_handle_module_detect_int(struct link_params *params);
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/* Get the actual link status. In case it returns 0, link is up,
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otherwise link is down*/
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u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
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+85
-25
@@ -2112,7 +2112,7 @@ static void bnx2x__link_reset(struct bnx2x *bp)
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{
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if (!BP_NOMCP(bp)) {
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bnx2x_acquire_phy_lock(bp);
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bnx2x_link_reset(&bp->link_params, &bp->link_vars);
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bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
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bnx2x_release_phy_lock(bp);
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} else
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BNX2X_ERR("Bootcode is missing -not resetting link\n");
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@@ -2613,6 +2613,13 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
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}
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}
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if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
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AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
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bnx2x_acquire_phy_lock(bp);
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bnx2x_handle_module_detect_int(&bp->link_params);
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bnx2x_release_phy_lock(bp);
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}
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if (attn & HW_INTERRUT_ASSERT_SET_0) {
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val = REG_RD(bp, reg_offset);
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@@ -5905,6 +5912,37 @@ static int bnx2x_init_port(struct bnx2x *bp)
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/* Port DMAE comes here */
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switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
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{
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u32 swap_val, swap_override, aeu_gpio_mask, offset;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
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/* The GPIO should be swapped if the swap register is
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set and active */
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swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
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swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
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/* Select function upon port-swap configuration */
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if (port == 0) {
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offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
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aeu_gpio_mask = (swap_val && swap_override) ?
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AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
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AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
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} else {
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offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
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aeu_gpio_mask = (swap_val && swap_override) ?
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AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
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AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
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}
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val = REG_RD(bp, offset);
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/* add GPIO3 to group */
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val |= aeu_gpio_mask;
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REG_WR(bp, offset, val);
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}
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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/* add SPIO 5 to group 0 */
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val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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@@ -7623,27 +7661,6 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
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ext_phy_type);
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@@ -7669,6 +7686,39 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
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ext_phy_type);
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bp->port.supported |= (SUPPORTED_10000baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_Autoneg |
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SUPPORTED_FIBRE |
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SUPPORTED_Pause |
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SUPPORTED_Asym_Pause);
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break;
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
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BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
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ext_phy_type);
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@@ -7905,6 +7955,7 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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u32 val, val2;
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u32 config;
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bp->link_params.bp = bp;
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bp->link_params.port = port;
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@@ -7923,6 +7974,14 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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bp->port.link_config =
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SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
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config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
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if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
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bp->link_params.feature_config_flags |=
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FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
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else
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bp->link_params.feature_config_flags &=
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~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
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BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
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KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
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" link_config 0x%08x\n",
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@@ -8121,10 +8180,11 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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switch (ext_phy_type) {
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
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case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
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cmd->port = PORT_FIBRE;
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break;
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@@ -8807,7 +8867,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
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if ((bp->state == BNX2X_STATE_OPEN) ||
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(bp->state == BNX2X_STATE_DISABLED)) {
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rc |= bnx2x_link_reset(&bp->link_params,
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&bp->link_vars);
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&bp->link_vars, 1);
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rc |= bnx2x_phy_init(&bp->link_params,
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&bp->link_vars);
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}
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@@ -5800,9 +5800,25 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_PMA_REG_ROM_VER2 0xca1a
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#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
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#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
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#define MDIO_PMA_REG_MISC_CTRL0 0xca23
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#define MDIO_PMA_REG_LRM_MODE 0xca3f
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#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
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#define MDIO_PMA_REG_MISC_CTRL1 0xca85
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#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000
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#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
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#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c
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#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002
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#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003
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#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
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#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
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#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
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#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
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#define MDIO_PMA_REG_7101_RESET 0xc000
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#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
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#define MDIO_PMA_REG_7101_VER1 0xc026
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@@ -5832,6 +5848,12 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_XS_PLL_SEQUENCER 0x8000
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#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
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#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
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#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
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#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
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#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
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#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
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#define MDIO_AN_DEVAD 0x7
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/*ieee*/
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#define MDIO_AN_REG_CTRL 0x0000
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