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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"New and/or improved SoC support for this release:
Marvell Berlin:
- Enable standard DT-based cpufreq
- Add CPU hotplug support
Freescale:
- Ethernet init for i.MX7D
- Suspend/resume support for i.MX6UL
Allwinner:
- Support for R8 chipset (used on NTC's $9 C.H.I.P board)
Mediatek:
- SMP support for some platforms
Uniphier:
- L2 support
- Cleaned up SMP support, etc.
plus a handful of other patches around above functionality, and a few
other smaller changes"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
ARM: uniphier: rework SMP operations to use trampoline code
ARM: uniphier: add outer cache support
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helper
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
ARM: sunxi: Add R8 support
ARM: digicolor: select pinctrl/gpio driver
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
...
This commit is contained in:
Linus Torvalds
@@ -19,7 +19,7 @@ executing kernel.
|
||||
Address: sysram_ns_base_addr
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Offset Value Purpose
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=============================================================================
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0x08 exynos_cpu_resume_ns System suspend
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0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
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0x0c 0x00000bad (Magic cookie) System suspend
|
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0x1c exynos4_secondary_startup Secondary CPU boot
|
||||
0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
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@@ -56,7 +56,8 @@ Offset Value Purpose
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Address: pmu_base_addr
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Offset Value Purpose
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=============================================================================
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0x0908 Non-zero (only Exynos3250) Secondary CPU boot up indicator
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0x0908 Non-zero Secondary CPU boot up indicator
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on Exynos3250 and Exynos542x
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|
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4. Glossary
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@@ -0,0 +1,56 @@
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* Texas Instruments Keystone Navigator Queue Management SubSystem driver
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Driver source code path
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drivers/soc/ti/knav_qmss.c
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drivers/soc/ti/knav_qmss_acc.c
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The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
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the main hardware sub system which forms the backbone of the Keystone
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multi-core Navigator. QMSS consist of queue managers, packed-data structure
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processors(PDSP), linking RAM, descriptor pools and infrastructure
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Packet DMA.
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The Queue Manager is a hardware module that is responsible for accelerating
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management of the packet queues. Packets are queued/de-queued by writing or
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reading descriptor address to a particular memory mapped location. The PDSPs
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perform QMSS related functions like accumulation, QoS, or event management.
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Linking RAM registers are used to link the descriptors which are stored in
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descriptor RAM. Descriptor RAM is configurable as internal or external memory.
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The QMSS driver manages the PDSP setups, linking RAM regions,
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queue pool management (allocation, push, pop and notify) and descriptor
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pool management.
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knav qmss driver provides a set of APIs to drivers to open/close qmss queues,
|
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allocate descriptor pools, map the descriptors, push/pop to queues etc. For
|
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details of the available APIs, please refers to include/linux/soc/ti/knav_qmss.h
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DT documentation is available at
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Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
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Accumulator QMSS queues using PDSP firmware
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============================================
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The QMSS PDSP firmware support accumulator channel that can monitor a single
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queue or multiple contiguous queues. drivers/soc/ti/knav_qmss_acc.c is the
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driver that interface with the accumulator PDSP. This configures
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accumulator channels defined in DTS (example in DT documentation) to monitor
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1 or 32 queues per channel. More description on the firmware is available in
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CPPI/QMSS Low Level Driver document (docs/CPPI_QMSS_LLD_SDS.pdf) at
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git://git.ti.com/keystone-rtos/qmss-lld.git
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k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports upto 48 accumulator
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channels. This firmware is available under ti-keystone folder of
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firmware.git at
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git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
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To use copy the firmware image to lib/firmware folder of the initramfs or
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ubifs file system and provide a sym link to k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin
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in the file system and boot up the kernel. User would see
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"firmware file ks2_qmss_pdsp_acc48.bin downloaded for PDSP"
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in the boot up log if loading of firmware to PDSP is successful.
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Use of accumulated queues requires the firmware image to be present in the
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file system. The driver doesn't acc queues to the supported queue range if
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PDSP is not running in the SoC. The API call fails if there is a queue open
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request to an acc queue and PDSP is not running. So make sure to copy firmware
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to file system before using these queue types.
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@@ -25,7 +25,7 @@ SunXi family
|
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+ Datasheet
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http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
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|
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- Allwinner A13 (sun5i)
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- Allwinner A13 / R8 (sun5i)
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+ Datasheet
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http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
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+ User Manual
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||||
|
||||
@@ -27,6 +27,11 @@ Required properties:
|
||||
* For "marvell,armada-380-coherency-fabric", only one pair is needed
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||||
for the per-CPU fabric registers.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- broken-idle: boolean to set when the Idle mode is not supported by the
|
||||
hardware.
|
||||
|
||||
Examples:
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||||
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coherency-fabric@d0020200 {
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||||
|
||||
@@ -0,0 +1,20 @@
|
||||
MVEBU CPU Config registers
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||||
--------------------------
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||||
|
||||
MVEBU (Marvell SOCs: Armada 370/XP)
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|
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Required properties:
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|
||||
- compatible: one of:
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- "marvell,armada-370-cpu-config"
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- "marvell,armada-xp-cpu-config"
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||||
|
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- reg: Should contain CPU config registers location and length, in
|
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their per-CPU variant
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||||
|
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Example:
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
|
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};
|
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@@ -6,6 +6,7 @@ using one of the following compatible strings:
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allwinner,sun4i-a10
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allwinner,sun5i-a10s
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allwinner,sun5i-a13
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allwinner,sun5i-r8
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||||
allwinner,sun6i-a31
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||||
allwinner,sun7i-a20
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||||
allwinner,sun8i-a23
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||||
|
||||
@@ -0,0 +1,60 @@
|
||||
UniPhier outer cache controller
|
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|
||||
UniPhier SoCs are integrated with a full-custom outer cache controller system.
|
||||
All of them have a level 2 cache controller, and some have a level 3 cache
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controller as well.
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|
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Required properties:
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- compatible: should be "socionext,uniphier-system-cache"
|
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- reg: offsets and lengths of the register sets for the device. It should
|
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contain 3 regions: control register, revision register, operation register,
|
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in this order.
|
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- cache-unified: specifies the cache is a unified cache.
|
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- cache-size: specifies the size in bytes of the cache
|
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- cache-sets: specifies the number of associativity sets of the cache
|
||||
- cache-line-size: specifies the line size in bytes
|
||||
- cache-level: specifies the level in the cache hierarchy. The value should
|
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be 2 for L2 cache, 3 for L3 cache, etc.
|
||||
|
||||
Optional properties:
|
||||
- next-level-cache: phandle to the next level cache if present. The next level
|
||||
cache should be also compatible with "socionext,uniphier-system-cache".
|
||||
|
||||
The L2 cache must exist to use the L3 cache; the cache hierarchy must be
|
||||
indicated correctly with "next-level-cache" properties.
|
||||
|
||||
Example 1 (system with L2):
|
||||
l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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||||
<0x506c0000 0x400>;
|
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cache-unified;
|
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cache-size = <0x80000>;
|
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cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
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Example 2 (system with L2 and L3):
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
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cache-level = <2>;
|
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next-level-cache = <&l3>;
|
||||
};
|
||||
|
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l3: l3-cache@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
|
||||
<0x506c8000 0x400>;
|
||||
cache-unified;
|
||||
cache-size = <0x400000>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
@@ -221,7 +221,6 @@ qmss: qmss@2a40000 {
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
pdsp0@0x2a10000 {
|
||||
firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
|
||||
reg = <0x2a10000 0x1000>,
|
||||
<0x2a0f000 0x100>,
|
||||
<0x2a0c000 0x3c8>,
|
||||
|
||||
+3
-1
@@ -920,7 +920,7 @@ M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
|
||||
S: Maintained
|
||||
F: arch/arm/mach-alpine/
|
||||
|
||||
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
|
||||
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
|
||||
M: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
|
||||
M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
|
||||
@@ -1630,7 +1630,9 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/uniphier*
|
||||
F: arch/arm/include/asm/hardware/cache-uniphier.h
|
||||
F: arch/arm/mach-uniphier/
|
||||
F: arch/arm/mm/cache-uniphier.c
|
||||
F: drivers/i2c/busses/i2c-uniphier*
|
||||
F: drivers/pinctrl/uniphier/
|
||||
F: drivers/tty/serial/8250/8250_uniphier.c
|
||||
|
||||
+16
-25
@@ -123,29 +123,23 @@ choice
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||||
0x80020000 | 0xf0020000 | UART8
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0x80024000 | 0xf0024000 | UART9
|
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|
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config AT91_DEBUG_LL_DBGU0
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bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10, 9rl, 9x5, 9n12"
|
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select DEBUG_AT91_UART
|
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config DEBUG_AT91_UART
|
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bool "Kernel low-level debugging on Atmel SoCs"
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_AT91RM9200 || SOC_AT91SAM9
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on atmel devices.
|
||||
|
||||
config AT91_DEBUG_LL_DBGU1
|
||||
bool "Kernel low-level debugging on 9263, 9g45 and sama5d3"
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_AT91SAM9 || SOC_SAMA5
|
||||
SOC DEBUG_UART_PHYS DEBUG_UART_VIRT PORT
|
||||
rm9200, 9260/9g20, 0xfffff200 0xfefff200 DBGU
|
||||
9261/9g10, 9rl
|
||||
9263, 9g45, sama5d3 0xffffee00 0xfeffee00 DBGU
|
||||
sama5d4 0xfc00c000 0xfb00c000 USART3
|
||||
sama5d4 0xfc069000 0xfb069000 DBGU
|
||||
sama5d2 0xf8020000 0xf7020000 UART1
|
||||
|
||||
config AT91_DEBUG_LL_DBGU2
|
||||
bool "Kernel low-level debugging on sama5d4"
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_SAMA5
|
||||
|
||||
config AT91_DEBUG_LL_DBGU3
|
||||
bool "Kernel low-level debugging on sama5d2"
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_SAMA5
|
||||
Please adjust DEBUG_UART_PHYS configuration options based on
|
||||
your needs.
|
||||
|
||||
config DEBUG_BCM2835
|
||||
bool "Kernel low-level debugging on BCM2835 PL011 UART"
|
||||
@@ -1249,10 +1243,6 @@ choice
|
||||
|
||||
endchoice
|
||||
|
||||
config DEBUG_AT91_UART
|
||||
bool
|
||||
depends on ARCH_AT91
|
||||
|
||||
config DEBUG_EXYNOS_UART
|
||||
bool
|
||||
|
||||
@@ -1485,7 +1475,8 @@ config DEBUG_UART_PHYS
|
||||
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
|
||||
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
|
||||
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
|
||||
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
|
||||
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
|
||||
DEBUG_AT91_UART
|
||||
|
||||
config DEBUG_UART_VIRT
|
||||
hex "Virtual base address of debug UART"
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CACHE_UNIPHIER_H
|
||||
#define __CACHE_UNIPHIER_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifdef CONFIG_CACHE_UNIPHIER
|
||||
int uniphier_cache_init(void);
|
||||
int uniphier_cache_l2_is_enabled(void);
|
||||
void uniphier_cache_l2_touch_range(unsigned long start, unsigned long end);
|
||||
void uniphier_cache_l2_set_locked_ways(u32 way_mask);
|
||||
#else
|
||||
static inline int uniphier_cache_init(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int uniphier_cache_l2_is_enabled(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void uniphier_cache_l2_touch_range(unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void uniphier_cache_l2_set_locked_ways(u32 way_mask)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CACHE_UNIPHIER_H */
|
||||
@@ -9,32 +9,22 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
|
||||
#define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */
|
||||
#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
|
||||
#define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */
|
||||
#elif defined(CONFIG_AT91_DEBUG_LL_DBGU2)
|
||||
/* On sama5d4, use USART3 as low level serial console */
|
||||
#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
|
||||
#else
|
||||
/* On sama5d2, use UART1 as low level serial console */
|
||||
#define AT91_DBGU 0xf8020000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
#define AT91_IO_P2V(x) ((x) - 0x01000000)
|
||||
#else
|
||||
#define AT91_IO_P2V(x) (x)
|
||||
#endif
|
||||
|
||||
#define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)
|
||||
|
||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
|
||||
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, =AT91_DBGU @ System peripherals (phys address)
|
||||
ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
|
||||
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
|
||||
ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
|
||||
@@ -39,6 +39,7 @@
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/cache-uniphier.h>
|
||||
#include <asm/outercache.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -97,6 +98,8 @@ void __init init_IRQ(void)
|
||||
if (ret)
|
||||
pr_err("L2C: failed to init: %d\n", ret);
|
||||
}
|
||||
|
||||
uniphier_cache_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MULTI_IRQ_HANDLER
|
||||
|
||||
@@ -80,6 +80,8 @@ tmp2 .req r5
|
||||
* @r2: base address of second SDRAM Controller or 0 if not present
|
||||
* @r3: pm information
|
||||
*/
|
||||
/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
|
||||
.align 3
|
||||
ENTRY(at91_pm_suspend_in_sram)
|
||||
/* Save registers on stack */
|
||||
stmfd sp!, {r4 - r12, lr}
|
||||
|
||||
@@ -35,6 +35,20 @@ config ARCH_BCM_CYGNUS
|
||||
BCM11300, BCM11320, BCM11350, BCM11360,
|
||||
BCM58300, BCM58302, BCM58303, BCM58305.
|
||||
|
||||
config ARCH_BCM_NSP
|
||||
bool "Broadcom Northstar Plus SoC Support" if ARCH_MULTI_V7
|
||||
select ARCH_BCM_IPROC
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_775420
|
||||
help
|
||||
Support for Broadcom Northstar Plus SoC.
|
||||
Broadcom Northstar Plus family of SoCs are used for switching control
|
||||
and management applications as well as residential router/gateway
|
||||
applications. The SoC features dual core Cortex A9 ARM CPUs,
|
||||
integrating several peripheral interfaces including multiple Gigabit
|
||||
Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and
|
||||
NAND flash, SATA and several other IO controllers.
|
||||
|
||||
config ARCH_BCM_5301X
|
||||
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
|
||||
select ARCH_BCM_IPROC
|
||||
@@ -147,6 +161,7 @@ config ARCH_BRCMSTB
|
||||
select BCM7120_L2_IRQ
|
||||
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select SOC_BRCMSTB
|
||||
help
|
||||
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
|
||||
chipset.
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#
|
||||
# Copyright (C) 2012-2014 Broadcom Corporation
|
||||
# Copyright (C) 2012-2015 Broadcom Corporation
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
@@ -13,6 +13,9 @@
|
||||
# Cygnus
|
||||
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
|
||||
|
||||
# Northstar Plus
|
||||
obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
|
||||
|
||||
# BCM281XX
|
||||
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
|
||||
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static const char *const bcm_nsp_dt_compat[] __initconst = {
|
||||
"brcm,nsp",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(NSP_DT, "Broadcom Northstar Plus SoC")
|
||||
.l2c_aux_val = 0,
|
||||
.l2c_aux_mask = ~0,
|
||||
.dt_compat = bcm_nsp_dt_compat,
|
||||
MACHINE_END
|
||||
@@ -12,11 +12,19 @@
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/soc/brcmstb/brcmstb.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static void __init brcmstb_init_irq(void)
|
||||
{
|
||||
irqchip_init();
|
||||
brcmstb_biuctrl_init();
|
||||
}
|
||||
|
||||
static const char *const brcmstb_match[] __initconst = {
|
||||
"brcm,bcm7445",
|
||||
"brcm,brcmstb",
|
||||
@@ -25,4 +33,5 @@ static const char *const brcmstb_match[] __initconst = {
|
||||
|
||||
DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
|
||||
.dt_compat = brcmstb_match,
|
||||
.init_irq = brcmstb_init_irq,
|
||||
MACHINE_END
|
||||
|
||||
@@ -18,6 +18,11 @@
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static void __init berlin_init_late(void)
|
||||
{
|
||||
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static const char * const berlin_dt_compat[] = {
|
||||
"marvell,berlin",
|
||||
NULL,
|
||||
@@ -25,6 +30,7 @@ static const char * const berlin_dt_compat[] = {
|
||||
|
||||
DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
|
||||
.dt_compat = berlin_dt_compat,
|
||||
.init_late = berlin_init_late,
|
||||
/*
|
||||
* with DT probing for L2CCs, berlin_init_machine can be removed.
|
||||
* Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
|
||||
|
||||
@@ -14,10 +14,16 @@
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#define CPU_RESET 0x00
|
||||
/*
|
||||
* There are two reset registers, one with self-clearing (SC)
|
||||
* reset and one with non-self-clearing reset (NON_SC).
|
||||
*/
|
||||
#define CPU_RESET_SC 0x00
|
||||
#define CPU_RESET_NON_SC 0x20
|
||||
|
||||
#define RESET_VECT 0x00
|
||||
#define SW_RESET_ADDR 0x94
|
||||
@@ -30,9 +36,11 @@ static inline void berlin_perform_reset_cpu(unsigned int cpu)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(cpu_ctrl + CPU_RESET);
|
||||
val = readl(cpu_ctrl + CPU_RESET_NON_SC);
|
||||
val &= ~BIT(cpu_logical_map(cpu));
|
||||
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
|
||||
val |= BIT(cpu_logical_map(cpu));
|
||||
writel(val, cpu_ctrl + CPU_RESET);
|
||||
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
|
||||
}
|
||||
|
||||
static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
@@ -91,8 +99,32 @@ unmap_scu:
|
||||
iounmap(scu_base);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static void berlin_cpu_die(unsigned int cpu)
|
||||
{
|
||||
v7_exit_coherency_flush(louis);
|
||||
while (1)
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static int berlin_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(cpu_ctrl + CPU_RESET_NON_SC);
|
||||
val &= ~BIT(cpu_logical_map(cpu));
|
||||
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct smp_operations berlin_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = berlin_smp_prepare_cpus,
|
||||
.smp_boot_secondary = berlin_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = berlin_cpu_die,
|
||||
.cpu_kill = berlin_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
CPU_METHOD_OF_DECLARE(berlin_smp, "marvell,berlin-smp", &berlin_smp_ops);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user