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Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into devel

Browse Source 
Conflicts:
	arch/arm/mm/Kconfig

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2009-03-26 23:10:11 +00:00
committed by Russell King
parent e8b374bb6c 839e642f3d
commit 542f869f18
37 changed files with 2162 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
MAINTAINERS
+13
View File
@@ -502,6 +502,13 @@ P: Richard Purdie
M: rpurdie@rpsys.net
S: Maintained
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
P: Paulius Zaleckas
M: paulius.zaleckas@teltonika.lt
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
T: git gitorious.org/linux-gemini/mainline.git
S: Maintained
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
P: Daniel Ribeiro
M: drwyrm@gmail.com
@@ -513,6 +520,12 @@ L: openezx-devel@lists.openezx.org (subscribers-only)
W: http://www.openezx.org/
S: Maintained
ARM/FARADAY FA526 PORT
P: Paulius Zaleckas
M: paulius.zaleckas@teltonika.lt
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
P: Sascha Hauer
M: kernel@pengutronix.de
arch/arm/Kconfig
+10
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@@ -276,6 +276,14 @@ config ARCH_EP93XX
help
This enables support for the Cirrus EP93xx series of CPUs.
config ARCH_GEMINI
bool "Cortina Systems Gemini"
select CPU_FA526
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
Support for the Cortina Systems Gemini family SoCs
config ARCH_FOOTBRIDGE
bool "FootBridge"
select CPU_SA110
@@ -616,6 +624,8 @@ source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
arch/arm/Makefile
+2
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@@ -72,6 +72,7 @@ tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_FA526) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
@@ -113,6 +114,7 @@ endif
plat-$(CONFIG_PLAT_PXA) := pxa
machine-$(CONFIG_ARCH_L7200) := l7200
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
machine-$(CONFIG_ARCH_GEMINI) := gemini
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_IOP32X) := iop32x
arch/arm/boot/compressed/head.S
+26
View File
@@ -465,6 +465,20 @@ __armv7_mmu_cache_on:
mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
__fa526_cache_on:
mov r12, lr
bl __setup_mmu
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
mrc p15, 0, r0, c1, c0, 0 @ read control reg
orr r0, r0, #0x1000 @ I-cache enable
bl __common_mmu_cache_on
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
mov pc, r12
__arm6_mmu_cache_on:
mov r12, lr
bl __setup_mmu
@@ -654,6 +668,12 @@ proc_types:
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
.word 0x66015261 @ FA526
.word 0xff01fff1
b __fa526_cache_on
b __armv4_mmu_cache_off
b __fa526_cache_flush
@ These match on the architecture ID
.word 0x00020000 @ ARMv4T
@@ -793,6 +813,12 @@ __armv4_mpu_cache_flush:
mcr p15, 0, ip, c7, c10, 4 @ drain WB
mov pc, lr
__fa526_cache_flush:
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
mcr p15, 0, r1, c7, c5, 0 @ flush I cache
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
__armv6_mmu_cache_flush:
mov r1, #0
arch/arm/include/asm/cacheflush.h
+8
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@@ -46,6 +46,14 @@
# define MULTI_CACHE 1
#endif
#if defined(CONFIG_CPU_FA526)
# ifdef _CACHE
# define MULTI_CACHE 1
# else
# define _CACHE fa
# endif
#endif
#if defined(CONFIG_CPU_ARM926T)
# ifdef _CACHE
# define MULTI_CACHE 1
arch/arm/include/asm/page.h
+8
View File
@@ -76,6 +76,14 @@
# endif
#endif
#ifdef CONFIG_CPU_COPY_FA
# ifdef _USER
# define MULTI_USER 1
# else
# define _USER fa
# endif
#endif
#ifdef CONFIG_CPU_SA1100
# ifdef _USER
# define MULTI_USER 1
arch/arm/include/asm/proc-fns.h
+8
View File
@@ -89,6 +89,14 @@
# define CPU_NAME cpu_arm922
# endif
# endif
# ifdef CONFIG_CPU_FA526
# ifdef CPU_NAME
# undef MULTI_CPU
# define MULTI_CPU
# else
# define CPU_NAME cpu_fa526
# endif
# endif
# ifdef CONFIG_CPU_ARM925T
# ifdef CPU_NAME
# undef MULTI_CPU
arch/arm/include/asm/system.h
+6
View File
@@ -125,6 +125,12 @@ extern unsigned int user_debug;
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
: : "r" (0) : "memory")
#elif defined(CONFIG_CPU_FA526)
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#else
#define isb() __asm__ __volatile__ ("" : : : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
arch/arm/include/asm/tlbflush.h
+25 -13
View File
@@ -39,6 +39,7 @@
#define TLB_V6_D_ASID (1 << 17)
#define TLB_V6_I_ASID (1 << 18)
#define TLB_BTB (1 << 28)
#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
#define TLB_DCLEAN (1 << 30)
#define TLB_WB (1 << 31)
@@ -53,6 +54,7 @@
* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
* fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
* fa - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB))
* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
* v7wbi - identical to v6wbi
*/
@@ -89,6 +91,22 @@
# define v4_always_flags (-1UL)
#endif
#define fa_tlb_flags (TLB_WB | TLB_BTB | TLB_DCLEAN | \
TLB_V4_U_FULL | TLB_V4_U_PAGE)
#ifdef CONFIG_CPU_TLB_FA
# define fa_possible_flags fa_tlb_flags
# define fa_always_flags fa_tlb_flags
# ifdef _TLB
# define MULTI_TLB 1
# else
# define _TLB fa
# endif
#else
# define fa_possible_flags 0
# define fa_always_flags (-1UL)
#endif
#define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
TLB_V4_I_FULL | TLB_V4_D_FULL | \
TLB_V4_I_PAGE | TLB_V4_D_PAGE)
@@ -140,7 +158,7 @@
# define v4wb_always_flags (-1UL)
#endif
#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
TLB_V6_I_FULL | TLB_V6_D_FULL | \
TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
TLB_V6_I_ASID | TLB_V6_D_ASID)
@@ -267,6 +285,7 @@ extern struct cpu_tlb_fns cpu_tlb;
v4wbi_possible_flags | \
fr_possible_flags | \
v4wb_possible_flags | \
fa_possible_flags | \
v6wbi_possible_flags | \
v7wbi_possible_flags)
@@ -275,6 +294,7 @@ extern struct cpu_tlb_fns cpu_tlb;
v4wbi_always_flags & \
fr_always_flags & \
v4wb_always_flags & \
fa_always_flags & \
v6wbi_always_flags & \
v7wbi_always_flags)
@@ -297,9 +317,7 @@ static inline void local_flush_tlb_all(void)
if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
TLB_V6_I_PAGE | TLB_V6_D_PAGE |
TLB_V6_I_ASID | TLB_V6_D_ASID)) {
if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
dsb();
@@ -334,9 +352,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
if (tlb_flag(TLB_V6_I_ASID))
asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
TLB_V6_I_PAGE | TLB_V6_D_PAGE |
TLB_V6_I_ASID | TLB_V6_D_ASID)) {
if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
dsb();
@@ -374,9 +390,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
TLB_V6_I_PAGE | TLB_V6_D_PAGE |
TLB_V6_I_ASID | TLB_V6_D_ASID)) {
if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
dsb();
@@ -411,9 +425,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
TLB_V6_I_PAGE | TLB_V6_D_PAGE |
TLB_V6_I_ASID | TLB_V6_D_ASID)) {
if (tlb_flag(TLB_BTB)) {
/* flush the branch target cache */
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
dsb();
arch/arm/mach-gemini/Kconfig
+19
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@@ -0,0 +1,19 @@
if ARCH_GEMINI
menu "Cortina Systems Gemini Implementations"
config MACH_RUT100
bool "Teltonika RUT100"
select GEMINI_MEM_SWAP
help
Say Y here if you intend to run this kernel on a
Teltonika 3G Router RUT100.
endmenu
config GEMINI_MEM_SWAP
bool "Gemini memory is swapped"
help
Say Y here if Gemini memory is swapped by bootloader.
endif
arch/arm/mach-gemini/Makefile
+10
View File
@@ -0,0 +1,10 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := irq.o mm.o time.o devices.o gpio.o
# Board-specific support
obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o
arch/arm/mach-gemini/Makefile.boot
+9
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@@ -0,0 +1,9 @@
ifeq ($(CONFIG_GEMINI_MEM_SWAP),y)
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
else
zreladdr-y := 0x10008000
params_phys-y := 0x10000100
initrd_phys-y := 0x10800000
endif
arch/arm/mach-gemini/board-rut1xx.c
+95
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@@ -0,0 +1,95 @@
/*
* Support for Teltonika RUT1xx
*
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
static struct gpio_keys_button rut1xx_keys[] = {
{
.code = KEY_SETUP,
.gpio = 60,
.active_low = 1,
.desc = "Reset to defaults",
.type = EV_KEY,
},
};
static struct gpio_keys_platform_data rut1xx_keys_data = {
.buttons = rut1xx_keys,
.nbuttons = ARRAY_SIZE(rut1xx_keys),
};
static struct platform_device rut1xx_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &rut1xx_keys_data,
},
};
static struct gpio_led rut100_leds[] = {
{
.name = "Power",
.default_trigger = "heartbeat",
.gpio = 17,
},
{
.name = "GSM",
.default_trigger = "default-on",
.gpio = 7,
.active_low = 1,
},
};
static struct gpio_led_platform_data rut100_leds_data = {
.num_leds = ARRAY_SIZE(rut100_leds),
.leds = rut100_leds,
};
static struct platform_device rut1xx_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &rut100_leds_data,
},
};
static struct sys_timer rut1xx_timer = {
.init = gemini_timer_init,
};
static void __init rut1xx_init(void)
{
gemini_gpio_init();
platform_register_uart();
platform_register_pflash(SZ_8M, NULL, 0);
platform_device_register(&rut1xx_leds);
platform_device_register(&rut1xx_keys_device);
}
MACHINE_START(RUT100, "Teltonika RUT100")
.phys_io = 0x7fffc000,
.io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
.boot_params = 0x100,
.map_io = gemini_map_io,
.init_irq = gemini_init_irq,
.timer = &rut1xx_timer,
.init_machine = rut1xx_init,
MACHINE_END
arch/arm/mach-gemini/common.h
+28
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@@ -0,0 +1,28 @@
/*
* Common Gemini architecture functions
*
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __GEMINI_COMMON_H__
#define __GEMINI_COMMON_H__
struct mtd_partition;
extern void gemini_map_io(void);
extern void gemini_init_irq(void);
extern void gemini_timer_init(void);
extern void gemini_gpio_init(void);
/* Common platform devices registration functions */
extern int platform_register_uart(void);
extern int platform_register_pflash(unsigned int size,
struct mtd_partition *parts,
unsigned int nr_parts);
#endif /* __GEMINI_COMMON_H__ */
arch/arm/mach-gemini/devices.c
+92
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@@ -0,0 +1,92 @@
/*
* Common devices definition for Gemini
*
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mtd/physmap.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/global_reg.h>
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
.mapbase = GEMINI_UART_BASE,
.irq = IRQ_UART,
.uartclk = UART_CLK,
.regshift = 2,
.iotype = UPIO_MEM,
.type = PORT_16550A,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE,
},
{},
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
int platform_register_uart(void)
{
return platform_device_register(&serial_device);
}
static struct resource flash_resource = {
.start = GEMINI_FLASH_BASE,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data pflash_platform_data = {};
static struct platform_device pflash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &pflash_platform_data,
},
.resource = &flash_resource,
.num_resources = 1,
};
int platform_register_pflash(unsigned int size, struct mtd_partition *parts,
unsigned int nr_parts)
{
unsigned int reg;
reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS);
if ((reg & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL)
return -ENXIO;
if (reg & FLASH_WIDTH_16BIT)
pflash_platform_data.width = 2;
else
pflash_platform_data.width = 1;
/* enable parallel flash pins and disable others */
reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
reg &= ~PFLASH_PADS_DISABLE;
reg |= SFLASH_PADS_DISABLE | NAND_PADS_DISABLE;
__raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
flash_resource.end = flash_resource.start + size - 1;
pflash_platform_data.parts = parts;
pflash_platform_data.nr_parts = nr_parts;
return platform_device_register(&pflash_device);
}
arch/arm/mach-gemini/gpio.c
+232
View File
@@ -0,0 +1,232 @@
/*
* Gemini gpiochip and interrupt routines
*
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* Based on plat-mxc/gpio.c:
* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
/* GPIO registers definition */
#define GPIO_DATA_OUT 0x0
#define GPIO_DATA_IN 0x4
#define GPIO_DIR 0x8
#define GPIO_DATA_SET 0x10
#define GPIO_DATA_CLR 0x14
#define GPIO_PULL_EN 0x18
#define GPIO_PULL_TYPE 0x1C
#define GPIO_INT_EN 0x20
#define GPIO_INT_STAT 0x24
#define GPIO_INT_MASK 0x2C
#define GPIO_INT_CLR 0x30
#define GPIO_INT_TYPE 0x34
#define GPIO_INT_BOTH_EDGE 0x38
#define GPIO_INT_LEVEL 0x3C
#define GPIO_DEBOUNCE_EN 0x40
#define GPIO_DEBOUNCE_PRESCALE 0x44
#define GPIO_PORT_NUM 3
static void _set_gpio_irqenable(unsigned int base, unsigned int index,
int enable)
{
unsigned int reg;
reg = __raw_readl(base + GPIO_INT_EN);
reg = (reg & (~(1 << index))) | (!!enable << index);
__raw_writel(reg, base + GPIO_INT_EN);
}
static void gpio_ack_irq(unsigned int irq)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int base = GPIO_BASE(gpio / 32);
__raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
}
static void gpio_mask_irq(unsigned int irq)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 0);
}
static void gpio_unmask_irq(unsigned int irq)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 1);
}
static int gpio_set_irq_type(unsigned int irq, unsigned int type)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int gpio_mask = 1 << (gpio % 32);
unsigned int base = GPIO_BASE(gpio / 32);
unsigned int reg_both, reg_level, reg_type;
reg_type = __raw_readl(base + GPIO_INT_TYPE);
reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE);
reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
reg_type &= ~gpio_mask;
reg_both |= gpio_mask;
break;
case IRQ_TYPE_EDGE_RISING:
reg_type &= ~gpio_mask;
reg_both &= ~gpio_mask;
reg_level &= ~gpio_mask;
break;
case IRQ_TYPE_EDGE_FALLING:
reg_type &= ~gpio_mask;
reg_both &= ~gpio_mask;
reg_level |= gpio_mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
reg_type |= gpio_mask;
reg_level &= ~gpio_mask;
break;
case IRQ_TYPE_LEVEL_LOW:
reg_type |= gpio_mask;
reg_level |= gpio_mask;
break;
default:
return -EINVAL;
}
__raw_writel(reg_type, base + GPIO_INT_TYPE);
__raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE);
__raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
gpio_ack_irq(irq);
return 0;
}
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int gpio_irq_no, irq_stat;
unsigned int port = (unsigned int)get_irq_data(irq);
irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
gpio_irq_no = GPIO_IRQ_BASE + port * 32;
for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
if ((irq_stat & 1) == 0)
continue;
BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
&irq_desc[gpio_irq_no]);
}
}
static struct irq_chip gpio_irq_chip = {
.name = "GPIO",
.ack = gpio_ack_irq,
.mask = gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_set_irq_type,
};
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
int dir)
{
unsigned int base = GPIO_BASE(offset / 32);
unsigned int reg;
reg = __raw_readl(base + GPIO_DIR);
if (dir)
reg |= 1 << (offset % 32);
else
reg &= ~(1 << (offset % 32));
__raw_writel(reg, base + GPIO_DIR);
}
static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
unsigned int base = GPIO_BASE(offset / 32);
if (value)
__raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
else
__raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR);
}
static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
{
unsigned int base = GPIO_BASE(offset / 32);
return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
}
static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
_set_gpio_direction(chip, offset, 0);
return 0;
}
static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
_set_gpio_direction(chip, offset, 1);
gemini_gpio_set(chip, offset, value);
return 0;
}
static struct gpio_chip gemini_gpio_chip = {
.label = "Gemini",
.direction_input = gemini_gpio_direction_input,
.get = gemini_gpio_get,
.direction_output = gemini_gpio_direction_output,
.set = gemini_gpio_set,
.base = 0,
.ngpio = GPIO_PORT_NUM * 32,
};
void __init gemini_gpio_init(void)
{
int i, j;
for (i = 0; i < GPIO_PORT_NUM; i++) {
/* disable, unmask and clear all interrupts */
__raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN);
__raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK);
__raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR);
for (j = GPIO_IRQ_BASE + i * 32;
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_edge_irq);
set_irq_flags(j, IRQF_VALID);
}
set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
set_irq_data(IRQ_GPIO(i), (void *)i);
}
BUG_ON(gpiochip_add(&gemini_gpio_chip));
}
arch/arm/mach-gemini/include/mach/debug-macro.S
+23
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/*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Copyright (C) 2001-2006 Storlink, Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =GEMINI_UART_BASE @ physical
ldrne \rx, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual
.endm
#define UART_SHIFT 2
#define FLOW_CONTROL
#include <asm/hardware/debug-8250.S>
arch/arm/mach-gemini/include/mach/entry-macro.S
+39
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@@ -0,0 +1,39 @@
/*
* Low-level IRQ helper macros for Gemini platform.
*
* Copyright (C) 2001-2006 Storlink, Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#define IRQ_STATUS 0x14
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
ldr \irqnr, [\irqstat]
cmp \irqnr, #0
beq 2313f
mov \tmp, \irqnr
mov \irqnr, #0
2312:
tst \tmp, #1
bne 2313f
add \irqnr, \irqnr, #1
mov \tmp, \tmp, lsr #1
cmp \irqnr, #31
bcc 2312b
2313:
.endm
arch/arm/mach-gemini/include/mach/global_reg.h
+278
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/*
* This file contains the hardware definitions for Gemini.
*
* Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __MACH_GLOBAL_REG_H
#define __MACH_GLOBAL_REG_H
/* Global Word ID Register*/
#define GLOBAL_ID 0x00
#define CHIP_ID(reg) ((reg) >> 8)
#define CHIP_REVISION(reg) ((reg) & 0xFF)
/* Global Status Register */
#define GLOBAL_STATUS 0x04
#define CPU_BIG_ENDIAN (1 << 31)
#define PLL_OSC_30M (1 << 30) /* else 60MHz */
#define OPERATION_MODE_MASK (0xF << 26)
#define OPM_IDDQ (0xF << 26)
#define OPM_NAND (0xE << 26)
#define OPM_RING (0xD << 26)
#define OPM_DIRECT_BOOT (0xC << 26)
#define OPM_USB1_PHY_TEST (0xB << 26)
#define OPM_USB0_PHY_TEST (0xA << 26)
#define OPM_SATA1_PHY_TEST (0x9 << 26)
#define OPM_SATA0_PHY_TEST (0x8 << 26)
#define OPM_ICE_ARM (0x7 << 26)
#define OPM_ICE_FARADAY (0x6 << 26)
#define OPM_PLL_BYPASS (0x5 << 26)
#define OPM_DEBUG (0x4 << 26)
#define OPM_BURN_IN (0x3 << 26)
#define OPM_MBIST (0x2 << 26)
#define OPM_SCAN (0x1 << 26)
#define OPM_REAL (0x0 << 26)
#define FLASH_TYPE_MASK (0x3 << 24)
#define FLASH_TYPE_NAND_2K (0x3 << 24)
#define FLASH_TYPE_NAND_512 (0x2 << 24)
#define FLASH_TYPE_PARALLEL (0x1 << 24)
#define FLASH_TYPE_SERIAL (0x0 << 24)
/* if parallel */
#define FLASH_WIDTH_16BIT (1 << 23) /* else 8 bit */
/* if serial */
#define FLASH_ATMEL (1 << 23) /* else STM */
#define FLASH_SIZE_MASK (0x3 << 21)
#define NAND_256M (0x3 << 21) /* and more */
#define NAND_128M (0x2 << 21)
#define NAND_64M (0x1 << 21)
#define NAND_32M (0x0 << 21)
#define ATMEL_16M (0x3 << 21) /* and more */
#define ATMEL_8M (0x2 << 21)
#define ATMEL_4M_2M (0x1 << 21)
#define ATMEL_1M (0x0 << 21) /* and less */
#define STM_32M (1 << 22) /* and more */
#define STM_16M (0 << 22) /* and less */
#define FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */
#define CPU_AHB_RATIO_MASK (0x3 << 18)
#define CPU_AHB_1_1 (0x0 << 18)
#define CPU_AHB_3_2 (0x1 << 18)
#define CPU_AHB_24_13 (0x2 << 18)
#define CPU_AHB_2_1 (0x3 << 18)
#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
#define AHB_SPEED_TO_REG(x) ((((x - 130)) / 10) << 15)
/* it is posible to override some settings, use >> OVERRIDE_xxxx_SHIFT */
#define OVERRIDE_FLASH_TYPE_SHIFT 16
#define OVERRIDE_FLASH_WIDTH_SHIFT 16
#define OVERRIDE_FLASH_SIZE_SHIFT 16
#define OVERRIDE_CPU_AHB_RATIO_SHIFT 15
#define OVERRIDE_AHB_SPEED_SHIFT 15
/* Global PLL Control Register */
#define GLOBAL_PLL_CTRL 0x08
#define PLL_BYPASS (1 << 31)
#define PLL_POWER_DOWN (1 << 8)
#define PLL_CONTROL_Q (0x1F << 0)
/* Global Soft Reset Control Register */
#define GLOBAL_RESET 0x0C
#define RESET_GLOBAL (1 << 31)
#define RESET_CPU1 (1 << 30)
#define RESET_TVE (1 << 28)
#define RESET_SATA1 (1 << 27)
#define RESET_SATA0 (1 << 26)
#define RESET_CIR (1 << 25)
#define RESET_EXT_DEV (1 << 24)
#define RESET_WD (1 << 23)
#define RESET_GPIO2 (1 << 22)
#define RESET_GPIO1 (1 << 21)
#define RESET_GPIO0 (1 << 20)
#define RESET_SSP (1 << 19)
#define RESET_UART (1 << 18)
#define RESET_TIMER (1 << 17)
#define RESET_RTC (1 << 16)
#define RESET_INT1 (1 << 15)
#define RESET_INT0 (1 << 14)
#define RESET_LCD (1 << 13)
#define RESET_LPC (1 << 12)
#define RESET_APB (1 << 11)
#define RESET_DMA (1 << 10)
#define RESET_USB1 (1 << 9)
#define RESET_USB0 (1 << 8)
#define RESET_PCI (1 << 7)
#define RESET_GMAC1 (1 << 6)
#define RESET_GMAC0 (1 << 5)
#define RESET_SECURITY (1 << 4)
#define RESET_RAID (1 << 3)
#define RESET_IDE (1 << 2)
#define RESET_FLASH (1 << 1)
#define RESET_DRAM (1 << 0)
/* Global IO Pad Driving Capability Control Register */
#define GLOBAL_IO_DRIVING_CTRL 0x10
#define DRIVING_CURRENT_MASK 0x3
/* here 00-4mA, 01-8mA, 10-12mA, 11-16mA */
#define GPIO1_PADS_31_28_SHIFT 28
#define GPIO0_PADS_31_16_SHIFT 26
#define GPIO0_PADS_15_0_SHIFT 24
#define PCI_AND_EXT_RESET_PADS_SHIFT 22
#define IDE_PADS_SHIFT 20
#define GMAC1_PADS_SHIFT 18
#define GMAC0_PADS_SHIFT 16
/* DRAM is not in mA and poorly documented */
#define DRAM_CLOCK_PADS_SHIFT 8
#define DRAM_DATA_PADS_SHIFT 4
#define DRAM_CONTROL_PADS_SHIFT 0
/* Global IO Pad Slew Rate Control Register */
#define GLOBAL_IO_SLEW_RATE_CTRL 0x14
#define GPIO1_PADS_31_28_SLOW (1 << 10)
#define GPIO0_PADS_31_16_SLOW (1 << 9)
#define GPIO0_PADS_15_0_SLOW (1 << 8)
#define PCI_PADS_SLOW (1 << 7)
#define IDE_PADS_SLOW (1 << 6)
#define GMAC1_PADS_SLOW (1 << 5)
#define GMAC0_PADS_SLOW (1 << 4)
#define DRAM_CLOCK_PADS_SLOW (1 << 1)
#define DRAM_IO_PADS_SLOW (1 << 0)
/*
* General skew control defines
* 16 steps, each step is around 0.2ns
*/
#define SKEW_MASK 0xF
/* Global IDE PAD Skew Control Register */
#define GLOBAL_IDE_SKEW_CTRL 0x18
#define IDE1_HOST_STROBE_DELAY_SHIFT 28
#define IDE1_DEVICE_STROBE_DELAY_SHIFT 24
#define IDE1_OUTPUT_IO_SKEW_SHIFT 20
#define IDE1_INPUT_IO_SKEW_SHIFT 16
#define IDE0_HOST_STROBE_DELAY_SHIFT 12
#define IDE0_DEVICE_STROBE_DELAY_SHIFT 8
#define IDE0_OUTPUT_IO_SKEW_SHIFT 4
#define IDE0_INPUT_IO_SKEW_SHIFT 0
/* Global GMAC Control Pad Skew Control Register */
#define GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C
#define GMAC1_TXC_SKEW_SHIFT 28
#define GMAC1_TXEN_SKEW_SHIFT 24
#define GMAC1_RXC_SKEW_SHIFT 20
#define GMAC1_RXDV_SKEW_SHIFT 16
#define GMAC0_TXC_SKEW_SHIFT 12
#define GMAC0_TXEN_SKEW_SHIFT 8
#define GMAC0_RXC_SKEW_SHIFT 4
#define GMAC0_RXDV_SKEW_SHIFT 0
/* Global GMAC0 Data PAD Skew Control Register */
#define GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20
/* Global GMAC1 Data PAD Skew Control Register */
#define GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24
#define GMAC_TXD_SKEW_SHIFT(x) (((x) * 4) + 16)
#define GMAC_RXD_SKEW_SHIFT(x) ((x) * 4)
/* CPU has two AHB busses. */
/* Global Arbitration0 Control Register */
#define GLOBAL_ARBITRATION0_CTRL 0x28
#define BOOT_CONTROLLER_HIGH_PRIO (1 << 3)
#define DMA_BUS1_HIGH_PRIO (1 << 2)
#define CPU0_HIGH_PRIO (1 << 0)
/* Global Arbitration1 Control Register */
#define GLOBAL_ARBITRATION1_CTRL 0x2C
#define TVE_HIGH_PRIO (1 << 9)
#define PCI_HIGH_PRIO (1 << 8)
#define USB1_HIGH_PRIO (1 << 7)
#define USB0_HIGH_PRIO (1 << 6)
#define GMAC1_HIGH_PRIO (1 << 5)
#define GMAC0_HIGH_PRIO (1 << 4)
#define SECURITY_HIGH_PRIO (1 << 3)
#define RAID_HIGH_PRIO (1 << 2)
#define IDE_HIGH_PRIO (1 << 1)
#define DMA_BUS2_HIGH_PRIO (1 << 0)
/* Common bits for both arbitration registers */
#define BURST_LENGTH_SHIFT 16
#define BURST_LENGTH_MASK (0x3F << 16)
/* Miscellaneous Control Register */
#define GLOBAL_MISC_CTRL 0x30
#define MEMORY_SPACE_SWAP (1 << 31)
#define USB1_PLUG_MINIB (1 << 30) /* else plug is mini-A */
#define USB0_PLUG_MINIB (1 << 29)
#define GMAC_GMII (1 << 28)
#define GMAC_1_ENABLE (1 << 27)
/* TODO: define ATA/SATA bits */
#define USB1_VBUS_ON (1 << 23)
#define USB0_VBUS_ON (1 << 22)
#define APB_CLKOUT_ENABLE (1 << 21)
#define TVC_CLKOUT_ENABLE (1 << 20)
#define EXT_CLKIN_ENABLE (1 << 19)
#define PCI_66MHZ (1 << 18) /* else 33 MHz */
#define PCI_CLKOUT_ENABLE (1 << 17)
#define LPC_CLKOUT_ENABLE (1 << 16)
#define USB1_WAKEUP_ON (1 << 15)
#define USB0_WAKEUP_ON (1 << 14)
/* TODO: define PCI idle detect bits */
#define TVC_PADS_ENABLE (1 << 9)
#define SSP_PADS_ENABLE (1 << 8)
#define LCD_PADS_ENABLE (1 << 7)
#define LPC_PADS_ENABLE (1 << 6)
#define PCI_PADS_ENABLE (1 << 5)
#define IDE_PADS_ENABLE (1 << 4)
#define DRAM_PADS_POWER_DOWN (1 << 3)
#define NAND_PADS_DISABLE (1 << 2)
#define PFLASH_PADS_DISABLE (1 << 1)
#define SFLASH_PADS_DISABLE (1 << 0)
/* Global Clock Control Register */
#define GLOBAL_CLOCK_CTRL 0x34
#define POWER_STATE_G0 (1 << 31)
#define POWER_STATE_S1 (1 << 30) /* else it is S3/S4 state */
#define SECURITY_APB_AHB (1 << 29)
/* else Security APB clk will be 0.75xAHB */
/* TODO: TVC clock divider */
#define PCI_CLKRUN_ENABLE (1 << 16)
#define BOOT_CLK_DISABLE (1 << 13)
#define TVC_CLK_DISABLE (1 << 12)
#define FLASH_CLK_DISABLE (1 << 11)
#define DDR_CLK_DISABLE (1 << 10)
#define PCI_CLK_DISABLE (1 << 9)
#define IDE_CLK_DISABLE (1 << 8)
#define USB1_CLK_DISABLE (1 << 7)
#define USB0_CLK_DISABLE (1 << 6)
#define SATA1_CLK_DISABLE (1 << 5)
#define SATA0_CLK_DISABLE (1 << 4)
#define GMAC1_CLK_DISABLE (1 << 3)
#define GMAC0_CLK_DISABLE (1 << 2)
#define SECURITY_CLK_DISABLE (1 << 1)
/* TODO: other registers definitions if needed */
#endif /* __MACH_GLOBAL_REG_H */
arch/arm/mach-gemini/include/mach/gpio.h
+25
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@@ -0,0 +1,25 @@
/*
* Gemini gpiolib specific defines
*
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __MACH_GPIO_H__
#define __MACH_GPIO_H__
#include <mach/irqs.h>
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(x) ((x) + GPIO_IRQ_BASE)
#define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE)
#endif /* __MACH_GPIO_H__ */

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