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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
This commit is contained in:
John W. Linville
@@ -54,7 +54,7 @@ int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len)
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int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
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{
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__le32 buf[2] = {
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const __le32 buf[2] = {
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cpu_to_le32(reg),
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cpu_to_le32(val),
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};
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@@ -104,6 +104,11 @@ enum ath_cipher {
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ATH_CIPHER_MIC = 127
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};
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enum ath_drv_info {
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AR7010_DEVICE = BIT(0),
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AR9287_DEVICE = BIT(1),
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};
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/**
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* struct ath_ops - Register read/write operations
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*
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@@ -147,6 +152,7 @@ struct ath_common {
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u8 rx_chainmask;
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u32 rx_bufsize;
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u32 driver_info;
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u32 keymax;
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DECLARE_BITMAP(keymap, ATH_KEYMAX);
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@@ -4,6 +4,7 @@ config ATH5K
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select MAC80211_LEDS
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select LEDS_CLASS
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select NEW_LEDS
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select AVERAGE
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---help---
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This module adds support for wireless adapters based on
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Atheros 5xxx chipset.
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@@ -63,15 +63,15 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
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* so i stick with the HAL version for now...
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*/
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#if 0
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const s8 hi[] = { -18, -18, -16, -14, -12 };
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const s8 lo[] = { -52, -56, -60, -64, -70 };
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const s8 sz[] = { -34, -41, -48, -55, -62 };
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const s8 fr[] = { -70, -72, -75, -78, -80 };
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static const s8 hi[] = { -18, -18, -16, -14, -12 };
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static const s8 lo[] = { -52, -56, -60, -64, -70 };
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static const s8 sz[] = { -34, -41, -48, -55, -62 };
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static const s8 fr[] = { -70, -72, -75, -78, -80 };
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#else
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const s8 sz[] = { -55, -62 };
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const s8 lo[] = { -64, -70 };
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const s8 hi[] = { -14, -12 };
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const s8 fr[] = { -78, -80 };
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static const s8 sz[] = { -55, -62 };
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static const s8 lo[] = { -64, -70 };
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static const s8 hi[] = { -14, -12 };
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static const s8 fr[] = { -78, -80 };
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#endif
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if (level < 0 || level >= ARRAY_SIZE(sz)) {
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ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range",
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@@ -102,7 +102,7 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
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void
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ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
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{
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const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
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static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
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if (level < 0 || level >= ARRAY_SIZE(val) ||
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level > ah->ah_sc->ani_state.max_spur_level) {
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@@ -127,7 +127,7 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
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void
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ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
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{
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const int val[] = { 0, 4, 8 };
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static const int val[] = { 0, 4, 8 };
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if (level < 0 || level >= ARRAY_SIZE(val)) {
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ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level);
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@@ -151,12 +151,12 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
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void
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ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
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{
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const int m1l[] = { 127, 50 };
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const int m2l[] = { 127, 40 };
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const int m1[] = { 127, 0x4d };
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const int m2[] = { 127, 0x40 };
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const int m2cnt[] = { 31, 16 };
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const int m2lcnt[] = { 63, 48 };
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static const int m1l[] = { 127, 50 };
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static const int m2l[] = { 127, 40 };
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static const int m1[] = { 127, 0x4d };
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static const int m2[] = { 127, 0x40 };
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static const int m2cnt[] = { 31, 16 };
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static const int m2lcnt[] = { 63, 48 };
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
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AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]);
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@@ -192,7 +192,7 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
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void
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ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
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{
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const int val[] = { 8, 6 };
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static const int val[] = { 8, 6 };
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
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AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
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ah->ah_sc->ani_state.cck_weak_sig = on;
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@@ -216,7 +216,7 @@ static void
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ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
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bool ofdm_trigger)
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{
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int rssi = ah->ah_beacon_rssi_avg.avg;
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int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
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ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)",
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ofdm_trigger ? "ODFM" : "CCK");
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@@ -301,7 +301,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
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static void
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ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
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{
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int rssi = ah->ah_beacon_rssi_avg.avg;
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int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
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ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity");
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@@ -25,6 +25,7 @@
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/average.h>
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#include <net/mac80211.h>
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/* RX/TX descriptor hw structs
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@@ -1102,7 +1103,7 @@ struct ath5k_hw {
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struct ath5k_nfcal_hist ah_nfcal_hist;
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/* average beacon RSSI in our BSS (used by ANI) */
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struct ath5k_avg_val ah_beacon_rssi_avg;
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struct ewma ah_beacon_rssi_avg;
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/* noise floor from last periodic calibration */
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s32 ah_noise_floor;
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@@ -1315,27 +1316,4 @@ static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
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return retval;
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}
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#define AVG_SAMPLES 8
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#define AVG_FACTOR 1000
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/**
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* ath5k_moving_average - Exponentially weighted moving average
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* @avg: average structure
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* @val: current value
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*
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* This implementation make use of a struct ath5k_avg_val to prevent rounding
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* errors.
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*/
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static inline struct ath5k_avg_val
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ath5k_moving_average(const struct ath5k_avg_val avg, const int val)
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{
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struct ath5k_avg_val new;
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new.avg_weight = avg.avg_weight ?
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(((avg.avg_weight * ((AVG_SAMPLES) - 1)) +
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(val * (AVG_FACTOR))) / (AVG_SAMPLES)) :
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(val * (AVG_FACTOR));
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new.avg = new.avg_weight / (AVG_FACTOR);
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return new;
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}
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#endif
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@@ -549,7 +549,7 @@ static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
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/* Calculate combined mode - when APs are active, operate in AP mode.
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* Otherwise use the mode of the new interface. This can currently
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* only deal with combinations of APs and STAs. Only one ad-hoc
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* interfaces is allowed above.
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* interfaces is allowed.
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*/
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if (avf->opmode == NL80211_IFTYPE_AP)
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iter_data->opmode = NL80211_IFTYPE_AP;
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@@ -558,14 +558,6 @@ static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
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iter_data->opmode = avf->opmode;
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}
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static void ath_do_set_opmode(struct ath5k_softc *sc)
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{
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struct ath5k_hw *ah = sc->ah;
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ath5k_hw_set_opmode(ah, sc->opmode);
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ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
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sc->opmode, ath_opmode_to_string(sc->opmode));
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}
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static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
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struct ieee80211_vif *vif)
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{
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@@ -595,7 +587,9 @@ static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
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/* Nothing active, default to station mode */
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sc->opmode = NL80211_IFTYPE_STATION;
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ath_do_set_opmode(sc);
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ath5k_hw_set_opmode(sc->ah, sc->opmode);
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ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
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sc->opmode, ath_opmode_to_string(sc->opmode));
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if (iter_data.need_set_hw_addr && iter_data.found_active)
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ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
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@@ -1307,8 +1301,7 @@ ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
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memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
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return;
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ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
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rssi);
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ewma_add(&ah->ah_beacon_rssi_avg, rssi);
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/* in IBSS mode we should keep RSSI statistics per neighbour */
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/* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
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@@ -2562,6 +2555,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
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ah->ah_cal_next_full = jiffies;
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ah->ah_cal_next_ani = jiffies;
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ah->ah_cal_next_nf = jiffies;
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ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8);
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/*
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* Change channels and update the h/w rate map if we're switching;
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@@ -3413,6 +3407,36 @@ static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
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return ret;
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}
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static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
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{
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struct ath5k_softc *sc = hw->priv;
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if (tx_ant == 1 && rx_ant == 1)
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ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
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else if (tx_ant == 2 && rx_ant == 2)
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ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
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else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
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ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
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else
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return -EINVAL;
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return 0;
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}
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static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
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{
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struct ath5k_softc *sc = hw->priv;
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switch (sc->ah->ah_ant_mode) {
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case AR5K_ANTMODE_FIXED_A:
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*tx_ant = 1; *rx_ant = 1; break;
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case AR5K_ANTMODE_FIXED_B:
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*tx_ant = 2; *rx_ant = 2; break;
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case AR5K_ANTMODE_DEFAULT:
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*tx_ant = 3; *rx_ant = 3; break;
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}
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return 0;
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}
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static const struct ieee80211_ops ath5k_hw_ops = {
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.tx = ath5k_tx,
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.start = ath5k_start,
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@@ -3433,6 +3457,8 @@ static const struct ieee80211_ops ath5k_hw_ops = {
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.sw_scan_start = ath5k_sw_scan_start,
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.sw_scan_complete = ath5k_sw_scan_complete,
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.set_coverage_class = ath5k_set_coverage_class,
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.set_antenna = ath5k_set_antenna,
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.get_antenna = ath5k_get_antenna,
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};
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/********************\
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@@ -719,7 +719,7 @@ static ssize_t read_file_ani(struct file *file, char __user *user_buf,
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st->mib_intr);
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len += snprintf(buf+len, sizeof(buf)-len,
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"beacon RSSI average:\t%d\n",
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sc->ah->ah_beacon_rssi_avg.avg);
|
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(int)ewma_read(&sc->ah->ah_beacon_rssi_avg));
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#define CC_PRINT(_struct, _field) \
|
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_struct._field, \
|
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@@ -834,10 +834,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
|
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{
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int i;
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const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
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const int coarseHigh[] = { -14, -14, -14, -14, -12 };
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const int coarseLow[] = { -64, -64, -64, -64, -70 };
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const int firpwr[] = { -78, -78, -78, -78, -80 };
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static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
|
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static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
|
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static const int coarseLow[] = { -64, -64, -64, -64, -70 };
|
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static const int firpwr[] = { -78, -78, -78, -78, -80 };
|
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|
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for (i = 0; i < 5; i++) {
|
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ah->totalSizeDesired[i] = totalSizeDesired[i];
|
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|
||||
@@ -244,13 +244,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
|
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int upper, lower, cur_vit_mask;
|
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int tmp, new;
|
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int i;
|
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int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
|
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
|
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static int pilot_mask_reg[4] = {
|
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AR_PHY_TIMING7, AR_PHY_TIMING8,
|
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AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
|
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};
|
||||
int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
|
||||
AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
|
||||
static int chan_mask_reg[4] = {
|
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AR_PHY_TIMING9, AR_PHY_TIMING10,
|
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AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
|
||||
};
|
||||
int inc[4] = { 0, 100, 0, 0 };
|
||||
static int inc[4] = { 0, 100, 0, 0 };
|
||||
|
||||
int8_t mask_m[123];
|
||||
int8_t mask_p[123];
|
||||
@@ -1084,12 +1086,12 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
|
||||
const int m1ThreshLow[] = { 127, 50 };
|
||||
const int m2ThreshLow[] = { 127, 40 };
|
||||
const int m1Thresh[] = { 127, 0x4d };
|
||||
const int m2Thresh[] = { 127, 0x40 };
|
||||
const int m2CountThr[] = { 31, 16 };
|
||||
const int m2CountThrLow[] = { 63, 48 };
|
||||
static const int m1ThreshLow[] = { 127, 50 };
|
||||
static const int m2ThreshLow[] = { 127, 40 };
|
||||
static const int m1Thresh[] = { 127, 0x4d };
|
||||
static const int m2Thresh[] = { 127, 0x40 };
|
||||
static const int m2CountThr[] = { 31, 16 };
|
||||
static const int m2CountThrLow[] = { 63, 48 };
|
||||
u32 on = param ? 1 : 0;
|
||||
|
||||
REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
|
||||
@@ -1141,7 +1143,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
|
||||
const int weakSigThrCck[] = { 8, 6 };
|
||||
static const int weakSigThrCck[] = { 8, 6 };
|
||||
u32 high = param ? 1 : 0;
|
||||
|
||||
REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
|
||||
@@ -1157,7 +1159,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_FIRSTEP_LEVEL:{
|
||||
const int firstep[] = { 0, 4, 8 };
|
||||
static const int firstep[] = { 0, 4, 8 };
|
||||
u32 level = param;
|
||||
|
||||
if (level >= ARRAY_SIZE(firstep)) {
|
||||
@@ -1178,7 +1180,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
|
||||
break;
|
||||
}
|
||||
case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
|
||||
const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
|
||||
static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
|
||||
u32 level = param;
|
||||
|
||||
if (level >= ARRAY_SIZE(cycpwrThr1)) {
|
||||
@@ -1579,10 +1581,55 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
|
||||
ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
|
||||
}
|
||||
|
||||
static void ar5008_hw_set_radar_params(struct ath_hw *ah,
|
||||
struct ath_hw_radar_conf *conf)
|
||||
{
|
||||
u32 radar_0 = 0, radar_1 = 0;
|
||||
|
||||
if (!conf) {
|
||||
REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
|
||||
return;
|
||||
}
|
||||
|
||||
radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
|
||||
radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
|
||||
radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
|
||||
radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
|
||||
radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
|
||||
radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
|
||||
|
||||
radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
|
||||
radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
|
||||
radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
|
||||
radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
|
||||
radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
|
||||
REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
|
||||
if (conf->ext_channel)
|
||||
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
else
|
||||
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
}
|
||||
|
||||
static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_radar_conf *conf = &ah->radar_conf;
|
||||
|
||||
conf->fir_power = -33;
|
||||
conf->radar_rssi = 20;
|
||||
conf->pulse_height = 10;
|
||||
conf->pulse_rssi = 24;
|
||||
conf->pulse_inband = 15;
|
||||
conf->pulse_maxlen = 255;
|
||||
conf->pulse_inband_step = 12;
|
||||
conf->radar_inband = 8;
|
||||
}
|
||||
|
||||
void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
||||
const u32 ar5416_cca_regs[6] = {
|
||||
static const u32 ar5416_cca_regs[6] = {
|
||||
AR_PHY_CCA,
|
||||
AR_PHY_CH1_CCA,
|
||||
AR_PHY_CH2_CCA,
|
||||
@@ -1609,6 +1656,7 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
|
||||
priv_ops->restore_chainmask = ar5008_restore_chainmask;
|
||||
priv_ops->set_diversity = ar5008_set_diversity;
|
||||
priv_ops->do_getnf = ar5008_hw_do_getnf;
|
||||
priv_ops->set_radar_params = ar5008_hw_set_radar_params;
|
||||
|
||||
if (modparam_force_new_ani) {
|
||||
priv_ops->ani_control = ar5008_hw_ani_control_new;
|
||||
@@ -1624,5 +1672,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
|
||||
priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
|
||||
|
||||
ar5008_hw_set_nf_limits(ah);
|
||||
ar5008_hw_set_radar_conf(ah);
|
||||
memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
|
||||
}
|
||||
|
||||
@@ -175,13 +175,15 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
|
||||
int upper, lower, cur_vit_mask;
|
||||
int tmp, newVal;
|
||||
int i;
|
||||
int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
|
||||
AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
|
||||
static const int pilot_mask_reg[4] = {
|
||||
AR_PHY_TIMING7, AR_PHY_TIMING8,
|
||||
AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
|
||||
};
|
||||
int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
|
||||
AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
|
||||
static const int chan_mask_reg[4] = {
|
||||
AR_PHY_TIMING9, AR_PHY_TIMING10,
|
||||
AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
|
||||
};
|
||||
int inc[4] = { 0, 100, 0, 0 };
|
||||
static const int inc[4] = { 0, 100, 0, 0 };
|
||||
struct chan_centers centers;
|
||||
|
||||
int8_t mask_m[123];
|
||||
|
||||
@@ -196,7 +196,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
|
||||
u32 qCoffDenom, iCoffDenom;
|
||||
int32_t qCoff, iCoff;
|
||||
int iqCorrNeg, i;
|
||||
const u_int32_t offset_array[3] = {
|
||||
static const u_int32_t offset_array[3] = {
|
||||
AR_PHY_RX_IQCAL_CORR_B0,
|
||||
AR_PHY_RX_IQCAL_CORR_B1,
|
||||
AR_PHY_RX_IQCAL_CORR_B2,
|
||||
@@ -603,22 +603,22 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
|
||||
static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
|
||||
static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
|
||||
AR_PHY_TX_IQCAL_STATUS_B0,
|
||||
AR_PHY_TX_IQCAL_STATUS_B1,
|
||||
AR_PHY_TX_IQCAL_STATUS_B2,
|
||||
};
|
||||
const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
|
||||
static const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
|
||||
AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
|
||||
AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
|
||||
AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
|
||||
};
|
||||
const u32 rx_corr[AR9300_MAX_CHAINS] = {
|
||||
static const u32 rx_corr[AR9300_MAX_CHAINS] = {
|
||||
AR_PHY_RX_IQCAL_CORR_B0,
|
||||
AR_PHY_RX_IQCAL_CORR_B1,
|
||||
AR_PHY_RX_IQCAL_CORR_B2,
|
||||
};
|
||||
const u_int32_t chan_info_tab[] = {
|
||||
static const u_int32_t chan_info_tab[] = {
|
||||
AR_PHY_CHAN_INFO_TAB_0,
|
||||
AR_PHY_CHAN_INFO_TAB_1,
|
||||
AR_PHY_CHAN_INFO_TAB_2,
|
||||
@@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan)
|
||||
{
|
||||
struct ath_common *common = ath9k_hw_common(ah);
|
||||
int val;
|
||||
|
||||
/*
|
||||
* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
|
||||
* running AGC/TxIQ cals
|
||||
*/
|
||||
ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
|
||||
val = REG_READ(ah, AR_ENT_OTP);
|
||||
ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
|
||||
|
||||
if (val & AR_ENT_OTP_CHAIN2_DISABLE)
|
||||
ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
|
||||
else
|
||||
/*
|
||||
* 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
|
||||
* mode before running AGC/TxIQ cals
|
||||
*/
|
||||
ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
|
||||
|
||||
/* Do Tx IQ Calibration */
|
||||
ar9003_hw_tx_iq_cal(ah);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -79,6 +79,15 @@
|
||||
#define FIXED_CCA_THRESHOLD 15
|
||||
|
||||
#define AR9300_BASE_ADDR 0x3ff
|
||||
#define AR9300_BASE_ADDR_512 0x1ff
|
||||
|
||||
#define AR9300_OTP_BASE 0x14000
|
||||
#define AR9300_OTP_STATUS 0x15f18
|
||||
#define AR9300_OTP_STATUS_TYPE 0x7
|
||||
#define AR9300_OTP_STATUS_VALID 0x4
|
||||
#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
|
||||
#define AR9300_OTP_STATUS_SM_BUSY 0x1
|
||||
#define AR9300_OTP_READ_DATA 0x15f1c
|
||||
|
||||
enum targetPowerHTRates {
|
||||
HT_TARGET_RATE_0_8_16,
|
||||
@@ -236,7 +245,7 @@ struct ar9300_modal_eep_header {
|
||||
u8 thresh62;
|
||||
__le32 papdRateMaskHt20;
|
||||
__le32 papdRateMaskHt40;
|
||||
u8 futureModal[24];
|
||||
u8 futureModal[10];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_cal_data_per_freq_op_loop {
|
||||
@@ -274,6 +283,20 @@ struct cal_ctl_data_5g {
|
||||
struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_BaseExtension_1 {
|
||||
u8 ant_div_control;
|
||||
u8 future[13];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_BaseExtension_2 {
|
||||
int8_t tempSlopeLow;
|
||||
int8_t tempSlopeHigh;
|
||||
u8 xatten1DBLow[AR9300_MAX_CHAINS];
|
||||
u8 xatten1MarginLow[AR9300_MAX_CHAINS];
|
||||
u8 xatten1DBHigh[AR9300_MAX_CHAINS];
|
||||
u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
|
||||
} __packed;
|
||||
|
||||
struct ar9300_eeprom {
|
||||
u8 eepromVersion;
|
||||
u8 templateVersion;
|
||||
@@ -283,6 +306,7 @@ struct ar9300_eeprom {
|
||||
struct ar9300_base_eep_hdr baseEepHeader;
|
||||
|
||||
struct ar9300_modal_eep_header modalHeader2G;
|
||||
struct ar9300_BaseExtension_1 base_ext1;
|
||||
u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
|
||||
struct ar9300_cal_data_per_freq_op_loop
|
||||
calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
|
||||
@@ -302,6 +326,7 @@ struct ar9300_eeprom {
|
||||
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
|
||||
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
|
||||
struct ar9300_modal_eep_header modalHeader5G;
|
||||
struct ar9300_BaseExtension_2 base_ext2;
|
||||
u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
|
||||
struct ar9300_cal_data_per_freq_op_loop
|
||||
calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
|
||||
|
||||
@@ -410,12 +410,36 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
|
||||
static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
|
||||
u32 aggrLen)
|
||||
{
|
||||
#define FIRST_DESC_NDELIMS 60
|
||||
struct ar9003_txc *ads = (struct ar9003_txc *) ds;
|
||||
|
||||
ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
|
||||
|
||||
ads->ctl17 &= ~AR_AggrLen;
|
||||
ads->ctl17 |= SM(aggrLen, AR_AggrLen);
|
||||
if (ah->ent_mode & AR_ENT_OTP_MPSD) {
|
||||
u32 ctl17, ndelim;
|
||||
/*
|
||||
* Add delimiter when using RTS/CTS with aggregation
|
||||
* and non enterprise AR9003 card
|
||||
*/
|
||||
ctl17 = ads->ctl17;
|
||||
ndelim = MS(ctl17, AR_PadDelim);
|
||||
|
||||
if (ndelim < FIRST_DESC_NDELIMS) {
|
||||
aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
|
||||
ndelim = FIRST_DESC_NDELIMS;
|
||||
}
|
||||
|
||||
ctl17 &= ~AR_AggrLen;
|
||||
ctl17 |= SM(aggrLen, AR_AggrLen);
|
||||
|
||||
ctl17 &= ~AR_PadDelim;
|
||||
ctl17 |= SM(ndelim, AR_PadDelim);
|
||||
|
||||
ads->ctl17 = ctl17;
|
||||
} else {
|
||||
ads->ctl17 &= ~AR_AggrLen;
|
||||
ads->ctl17 |= SM(aggrLen, AR_AggrLen);
|
||||
}
|
||||
}
|
||||
|
||||
static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
|
||||
|
||||
@@ -32,12 +32,12 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
|
||||
{
|
||||
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
|
||||
struct ar9300_modal_eep_header *hdr;
|
||||
const u32 ctrl0[3] = {
|
||||
static const u32 ctrl0[3] = {
|
||||
AR_PHY_PAPRD_CTRL0_B0,
|
||||
AR_PHY_PAPRD_CTRL0_B1,
|
||||
AR_PHY_PAPRD_CTRL0_B2
|
||||
};
|
||||
const u32 ctrl1[3] = {
|
||||
static const u32 ctrl1[3] = {
|
||||
AR_PHY_PAPRD_CTRL1_B0,
|
||||
AR_PHY_PAPRD_CTRL1_B1,
|
||||
AR_PHY_PAPRD_CTRL1_B2
|
||||
|
||||
@@ -128,7 +128,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
|
||||
static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
|
||||
struct ath9k_channel *chan)
|
||||
{
|
||||
u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
|
||||
static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
|
||||
int cur_bb_spur, negative = 0, cck_spur_freq;
|
||||
int i;
|
||||
|
||||
@@ -1113,10 +1113,55 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
|
||||
aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
|
||||
}
|
||||
|
||||
static void ar9003_hw_set_radar_params(struct ath_hw *ah,
|
||||
struct ath_hw_radar_conf *conf)
|
||||
{
|
||||
u32 radar_0 = 0, radar_1 = 0;
|
||||
|
||||
if (!conf) {
|
||||
REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
|
||||
return;
|
||||
}
|
||||
|
||||
radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
|
||||
radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
|
||||
radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
|
||||
radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
|
||||
radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
|
||||
radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
|
||||
|
||||
radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
|
||||
radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
|
||||
radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
|
||||
radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
|
||||
radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
|
||||
|
||||
REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
|
||||
REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
|
||||
if (conf->ext_channel)
|
||||
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
else
|
||||
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
|
||||
}
|
||||
|
||||
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_radar_conf *conf = &ah->radar_conf;
|
||||
|
||||
conf->fir_power = -28;
|
||||
conf->radar_rssi = 0;
|
||||
conf->pulse_height = 10;
|
||||
conf->pulse_rssi = 24;
|
||||
conf->pulse_inband = 8;
|
||||
conf->pulse_maxlen = 255;
|
||||
conf->pulse_inband_step = 12;
|
||||
conf->radar_inband = 8;
|
||||
}
|
||||
|
||||
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
|
||||
{
|
||||
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
||||
const u32 ar9300_cca_regs[6] = {
|
||||
static const u32 ar9300_cca_regs[6] = {
|
||||
AR_PHY_CCA_0,
|
||||
AR_PHY_CCA_1,
|
||||
AR_PHY_CCA_2,
|
||||
@@ -1141,8 +1186,10 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
|
||||
priv_ops->ani_control = ar9003_hw_ani_control;
|
||||
priv_ops->do_getnf = ar9003_hw_do_getnf;
|
||||
priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
|
||||
priv_ops->set_radar_params = ar9003_hw_set_radar_params;
|
||||
|
||||
ar9003_hw_set_nf_limits(ah);
|
||||
ar9003_hw_set_radar_conf(ah);
|
||||
memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
|
||||
}
|
||||
|
||||
|
||||
@@ -86,33 +86,19 @@ struct ath_config {
|
||||
/**
|
||||
* enum buffer_type - Buffer type flags
|
||||
*
|
||||
* @BUF_HT: Send this buffer using HT capabilities
|
||||
* @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
|
||||
* @BUF_AGGR: Indicates whether the buffer can be aggregated
|
||||
* (used in aggregation scheduling)
|
||||
* @BUF_RETRY: Indicates whether the buffer is retried
|
||||
* @BUF_XRETRY: To denote excessive retries of the buffer
|
||||
*/
|
||||
enum buffer_type {
|
||||
BUF_HT = BIT(1),
|
||||
BUF_AMPDU = BIT(2),
|
||||
BUF_AGGR = BIT(3),
|
||||
BUF_RETRY = BIT(4),
|
||||
BUF_XRETRY = BIT(5),
|
||||
};
|
||||
|
||||
#define bf_nframes bf_state.bfs_nframes
|
||||
#define bf_al bf_state.bfs_al
|
||||
#define bf_frmlen bf_state.bfs_frmlen
|
||||
#define bf_retries bf_state.bfs_retries
|
||||
#define bf_seqno bf_state.bfs_seqno
|
||||
#define bf_tidno bf_state.bfs_tidno
|
||||
#define bf_keyix bf_state.bfs_keyix
|
||||
#define bf_keytype bf_state.bfs_keytype
|
||||
#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
|
||||
#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
|
||||
#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
|
||||
#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
|
||||
#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
|
||||
|
||||
#define ATH_TXSTATUS_RING_SIZE 64
|
||||
@@ -177,8 +163,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
|
||||
|
||||
/* returns delimiter padding required given the packet length */
|
||||
#define ATH_AGGR_GET_NDELIM(_len) \
|
||||
(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
|
||||
(ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
|
||||
(((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
|
||||
DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
|
||||
|
||||
#define BAW_WITHIN(_start, _bawsz, _seqno) \
|
||||
((((_seqno) - (_start)) & 4095) < (_bawsz))
|
||||
@@ -217,18 +203,18 @@ struct ath_atx_ac {
|
||||
struct list_head tid_q;
|
||||
};
|
||||
|
||||
struct ath_frame_info {
|
||||
int framelen;
|
||||
u32 keyix;
|
||||
enum ath9k_key_type keytype;
|
||||
u8 retries;
|
||||
u16 seqno;
|
||||
};
|
||||
|
||||
struct ath_buf_state {
|
||||
int bfs_nframes;
|
||||
u16 bfs_al;
|
||||
u16 bfs_frmlen;
|
||||
int bfs_seqno;
|
||||
int bfs_tidno;
|
||||
int bfs_retries;
|
||||
u8 bf_type;
|
||||
u8 bfs_paprd;
|
||||
unsigned long bfs_paprd_timestamp;
|
||||
u32 bfs_keyix;
|
||||
enum ath9k_key_type bfs_keytype;
|
||||
enum ath9k_internal_frame_type bfs_ftype;
|
||||
};
|
||||
|
||||
struct ath_buf {
|
||||
@@ -241,7 +227,6 @@ struct ath_buf {
|
||||
dma_addr_t bf_daddr; /* physical addr of desc */
|
||||
dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
|
||||
bool bf_stale;
|
||||
bool bf_tx_aborted;
|
||||
u16 bf_flags;
|
||||
struct ath_buf_state bf_state;
|
||||
struct ath_wiphy *aphy;
|
||||
@@ -278,6 +263,7 @@ struct ath_node {
|
||||
|
||||
struct ath_tx_control {
|
||||
struct ath_txq *txq;
|
||||
struct ath_node *an;
|
||||
int if_id;
|
||||
enum ath9k_internal_frame_type frame_type;
|
||||
u8 paprd;
|
||||
@@ -338,7 +324,6 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
|
||||
struct ath_tx_control *txctl);
|
||||
void ath_tx_tasklet(struct ath_softc *sc);
|
||||
void ath_tx_edma_tasklet(struct ath_softc *sc);
|
||||
void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
|
||||
int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
|
||||
u16 tid, u16 *ssn);
|
||||
void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
|
||||
@@ -603,6 +588,7 @@ struct ath_softc {
|
||||
struct work_struct paprd_work;
|
||||
struct work_struct hw_check_work;
|
||||
struct completion paprd_complete;
|
||||
bool paprd_pending;
|
||||
|
||||
u32 intrstatus;
|
||||
u32 sc_flags; /* SC_OP_* */
|
||||
@@ -712,7 +698,7 @@ void ath9k_ps_restore(struct ath_softc *sc);
|
||||
void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
|
||||
int ath9k_wiphy_add(struct ath_softc *sc);
|
||||
int ath9k_wiphy_del(struct ath_wiphy *aphy);
|
||||
void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
|
||||
void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
|
||||
int ath9k_wiphy_pause(struct ath_wiphy *aphy);
|
||||
int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
|
||||
int ath9k_wiphy_select(struct ath_wiphy *aphy);
|
||||
|
||||
@@ -109,6 +109,25 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
|
||||
series, 4, 0);
|
||||
}
|
||||
|
||||
static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
|
||||
{
|
||||
struct ath_wiphy *aphy = hw->priv;
|
||||
struct ath_softc *sc = aphy->sc;
|
||||
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
||||
struct ath_tx_control txctl;
|
||||
|
||||
memset(&txctl, 0, sizeof(struct ath_tx_control));
|
||||
txctl.txq = sc->beacon.cabq;
|
||||
|
||||
ath_print(common, ATH_DBG_XMIT,
|
||||
"transmitting CABQ packet, skb: %p\n", skb);
|
||||
|
||||
if (ath_tx_start(hw, skb, &txctl) != 0) {
|
||||
ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
|
||||
dev_kfree_skb_any(skb);
|
||||
}
|
||||
}
|
||||
|
||||
static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif)
|
||||
{
|
||||
|
||||
@@ -534,7 +534,9 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
|
||||
u16 twiceMinEdgePower;
|
||||
u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
|
||||
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
|
||||
u16 numCtlModes, *pCtlMode, ctlMode, freq;
|
||||
u16 numCtlModes;
|
||||
const u16 *pCtlMode;
|
||||
u16 ctlMode, freq;
|
||||
struct chan_centers centers;
|
||||
struct cal_ctl_data_4k *rep;
|
||||
struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
|
||||
@@ -550,10 +552,10 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
|
||||
struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
|
||||
0, {0, 0, 0, 0}
|
||||
};
|
||||
u16 ctlModesFor11g[] =
|
||||
{ CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
|
||||
CTL_2GHT40
|
||||
};
|
||||
static const u16 ctlModesFor11g[] = {
|
||||
CTL_11B, CTL_11G, CTL_2GHT20,
|
||||
CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
|
||||
};
|
||||
|
||||
ath9k_hw_get_channel_centers(ah, chan, ¢ers);
|
||||
|
||||
|
||||
@@ -37,10 +37,10 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
|
||||
int addr, eep_start_loc;
|
||||
eep_data = (u16 *)eep;
|
||||
|
||||
if (AR9287_HTC_DEVID(ah))
|
||||
eep_start_loc = AR9287_HTC_EEP_START_LOC;
|
||||
else
|
||||
if (!common->driver_info)
|
||||
eep_start_loc = AR9287_EEP_START_LOC;
|
||||
else
|
||||
eep_start_loc = AR9287_HTC_EEP_START_LOC;
|
||||
|
||||
if (!ath9k_hw_use_flash(ah)) {
|
||||
ath_print(common, ATH_DBG_EEPROM,
|
||||
@@ -626,13 +626,13 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
|
||||
struct cal_target_power_ht targetPowerHt20,
|
||||
targetPowerHt40 = {0, {0, 0, 0, 0} };
|
||||
u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
|
||||
u16 ctlModesFor11g[] = {CTL_11B,
|
||||
CTL_11G,
|
||||
CTL_2GHT20,
|
||||
CTL_11B_EXT,
|
||||
CTL_11G_EXT,
|
||||
CTL_2GHT40};
|
||||
u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
|
||||
static const u16 ctlModesFor11g[] = {
|
||||
CTL_11B, CTL_11G, CTL_2GHT20,
|
||||
CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
|
||||
};
|
||||
u16 numCtlModes = 0;
|
||||
const u16 *pCtlMode = NULL;
|
||||
u16 ctlMode, freq;
|
||||
struct chan_centers centers;
|
||||
int tx_chainmask;
|
||||
u16 twiceMinEdgePower;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user