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Merge tag 'rmobile-for-linus' of git://github.com/pmundt/linux-sh
SH/R-Mobile updates for 3.3 merge window. * tag 'rmobile-for-linus' of git://github.com/pmundt/linux-sh: (32 commits) arm: mach-shmobile: add a resource name for shdma ARM: mach-shmobile: r8a7779 SMP support V3 ARM: mach-shmobile: Add kota2 defconfig. ARM: mach-shmobile: Add marzen defconfig. ARM: mach-shmobile: r8a7779 power domain support V2 ARM: mach-shmobile: Fix up marzen build for recent GIC changes. ARM: mach-shmobile: r8a7779 PFC function support ARM: mach-shmobile: Flush caches in platform_cpu_die() ARM: mach-shmobile: Allow SoC specific CPU kill code ARM: mach-shmobile: Fix headsmp.S code to use CPUINIT ARM: mach-shmobile: clock-r8a7779: clkz/clkzs support ARM: mach-shmobile: clock-r8a7779: add DIV4 clock support ARM: mach-shmobile: Marzen LAN89218 support ARM: mach-shmobile: Marzen SCIF2/SCIF4 support ARM: mach-shmobile: r8a7779 PFC GPIO-only support V2 ARM: mach-shmobile: r8a7779 and Marzen base support V2 sh: pfc: Unlock register support sh: pfc: Variable bitfield width config register support sh: pfc: Add config_reg_helper() function sh: pfc: Convert index to field and value pair ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,72 @@
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
|
||||
CONFIG_ARCH_R8A7740=y
|
||||
CONFIG_MACH_BONITO=y
|
||||
# CONFIG_SH_TIMER_TMU is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
|
||||
CONFIG_KEXEC=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
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||||
CONFIG_MTD_PHYSMAP=y
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||||
CONFIG_MTD_ARM_INTEGRATOR=y
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||||
CONFIG_MTD_BLOCK2MTD=y
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||||
CONFIG_SCSI=y
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||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
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||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
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||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
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||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
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||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
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||||
CONFIG_I2C_CHARDEV=y
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||||
CONFIG_I2C_SH_MOBILE=y
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||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_MFD_SUPPORT is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_UIO=y
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||||
CONFIG_UIO_PDRV=y
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||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_TMPFS=y
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||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
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||||
# CONFIG_ARM_UNWIND is not set
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@@ -0,0 +1,122 @@
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# CONFIG_ARM_PATCH_PHYS_VIRT is not set
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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||||
CONFIG_IKCONFIG=y
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||||
CONFIG_IKCONFIG_PROC=y
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||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_CGROUPS=y
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||||
CONFIG_CPUSETS=y
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||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
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||||
CONFIG_KEYBOARD_GPIO_POLLED=y
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||||
CONFIG_ARCH_SH73A0=y
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||||
CONFIG_MACH_KOTA2=y
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||||
CONFIG_MEMORY_SIZE=0x1e0000000
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||||
# CONFIG_SH_TIMER_TMU is not set
|
||||
# CONFIG_SWP_EMULATE is not set
|
||||
CONFIG_CPU_BPREDICT_DISABLE=y
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||||
CONFIG_ARM_ERRATA_460075=y
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||||
CONFIG_ARM_ERRATA_742230=y
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||||
CONFIG_ARM_ERRATA_742231=y
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||||
CONFIG_PL310_ERRATA_588369=y
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||||
CONFIG_ARM_ERRATA_720789=y
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||||
CONFIG_PL310_ERRATA_727915=y
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||||
CONFIG_ARM_ERRATA_743622=y
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||||
CONFIG_ARM_ERRATA_751472=y
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||||
CONFIG_PL310_ERRATA_753970=y
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CONFIG_ARM_ERRATA_754322=y
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||||
CONFIG_PL310_ERRATA_769419=y
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CONFIG_NO_HZ=y
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||||
CONFIG_SMP=y
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||||
CONFIG_AEABI=y
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||||
# CONFIG_OABI_COMPAT is not set
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||||
CONFIG_HIGHMEM=y
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||||
CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
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||||
CONFIG_CMDLINE_FORCE=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
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||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=y
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||||
CONFIG_WIRELESS_EXT_SYSFS=y
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||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_NETDEVICES=y
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||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
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||||
# CONFIG_NET_VENDOR_MICREL is not set
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# CONFIG_NET_VENDOR_NATSEMI is not set
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# CONFIG_NET_VENDOR_SEEQ is not set
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CONFIG_SMSC911X=y
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# CONFIG_NET_VENDOR_STMICRO is not set
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CONFIG_B43=y
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CONFIG_B43_PHY_N=y
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CONFIG_B43_DEBUG=y
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CONFIG_INPUT_SPARSEKMAP=y
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# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
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CONFIG_INPUT_EVDEV=y
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# CONFIG_KEYBOARD_ATKBD is not set
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CONFIG_KEYBOARD_GPIO=y
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CONFIG_KEYBOARD_SH_KEYSC=y
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_SH_SCI=y
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CONFIG_SERIAL_SH_SCI_NR_UARTS=9
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CONFIG_SERIAL_SH_SCI_CONSOLE=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C_SH_MOBILE=y
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# CONFIG_HWMON is not set
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CONFIG_BCMA=y
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CONFIG_BCMA_DEBUG=y
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CONFIG_FB=y
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CONFIG_FB_SH_MOBILE_LCDC=y
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CONFIG_LCD_PLATFORM=y
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CONFIG_FRAMEBUFFER_CONSOLE=y
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||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
# CONFIG_HID_SUPPORT is not set
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||||
# CONFIG_USB_SUPPORT is not set
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||||
CONFIG_MMC=y
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CONFIG_MMC_SDHI=y
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||||
CONFIG_MMC_SH_MMCIF=y
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CONFIG_NEW_LEDS=y
|
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CONFIG_LEDS_CLASS=y
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CONFIG_LEDS_GPIO=y
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||||
CONFIG_LEDS_RENESAS_TPU=y
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CONFIG_LEDS_TRIGGERS=y
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||||
# CONFIG_DNOTIFY is not set
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||||
# CONFIG_INOTIFY_USER is not set
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||||
CONFIG_TMPFS=y
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||||
# CONFIG_MISC_FILESYSTEMS is not set
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||||
CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_INFO=y
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||||
CONFIG_DEBUG_INFO_REDUCED=y
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||||
# CONFIG_FTRACE is not set
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CONFIG_DEBUG_USER=y
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||||
@@ -0,0 +1,87 @@
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
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CONFIG_EXPERIMENTAL=y
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||||
CONFIG_KERNEL_LZMA=y
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||||
CONFIG_IKCONFIG=y
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||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLOCK is not set
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CONFIG_ARCH_SHMOBILE=y
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CONFIG_ARCH_R8A7779=y
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CONFIG_MACH_MARZEN=y
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CONFIG_MEMORY_START=0x60000000
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CONFIG_MEMORY_SIZE=0x10000000
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CONFIG_SHMOBILE_TIMER_HZ=1024
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# CONFIG_SH_TIMER_CMT is not set
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# CONFIG_SWP_EMULATE is not set
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CONFIG_ARM_ERRATA_430973=y
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CONFIG_ARM_ERRATA_458693=y
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CONFIG_ARM_ERRATA_460075=y
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CONFIG_ARM_ERRATA_743622=y
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_NO_HZ=y
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CONFIG_SMP=y
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# CONFIG_ARM_CPU_TOPOLOGY is not set
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CONFIG_AEABI=y
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# CONFIG_OABI_COMPAT is not set
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CONFIG_HIGHMEM=y
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
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CONFIG_CMDLINE_FORCE=y
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CONFIG_KEXEC=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_PM_RUNTIME=y
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CONFIG_NET=y
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CONFIG_INET=y
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# CONFIG_IPV6 is not set
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# CONFIG_WIRELESS is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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# CONFIG_STANDALONE is not set
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# CONFIG_PREVENT_FIRMWARE_BUILD is not set
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# CONFIG_FW_LOADER is not set
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CONFIG_NETDEVICES=y
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# CONFIG_NET_VENDOR_BROADCOM is not set
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# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
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||||
# CONFIG_NET_VENDOR_NATSEMI is not set
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# CONFIG_NET_VENDOR_SEEQ is not set
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CONFIG_SMC911X=y
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CONFIG_SMSC911X=y
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# CONFIG_NET_VENDOR_STMICRO is not set
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# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SSB=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_FILE_LOCKING is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_INFO_REDUCED=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_AVERAGE=y
|
||||
@@ -28,6 +28,19 @@ config ARCH_SH73A0
|
||||
select ARM_GIC
|
||||
select I2C
|
||||
|
||||
config ARCH_R8A7740
|
||||
bool "R-Mobile A1 (R8A77400)"
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
config ARCH_R8A7779
|
||||
bool "R-Car H1 (R8A77790)"
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select ARM_GIC
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
comment "SH-Mobile Board Type"
|
||||
|
||||
config MACH_G3EVM
|
||||
@@ -75,6 +88,16 @@ config MACH_KOTA2
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
depends on ARCH_SH73A0
|
||||
|
||||
config MACH_BONITO
|
||||
bool "bonito board"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
depends on ARCH_R8A7740
|
||||
|
||||
config MACH_MARZEN
|
||||
bool "MARZEN board"
|
||||
depends on ARCH_R8A7779
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
comment "SH-Mobile System Configuration"
|
||||
|
||||
menu "Memory configuration"
|
||||
@@ -83,7 +106,7 @@ config MEMORY_START
|
||||
hex "Physical memory start address"
|
||||
default "0x50000000" if MACH_G3EVM
|
||||
default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
|
||||
MACH_MACKEREL
|
||||
MACH_MACKEREL || MACH_BONITO
|
||||
default "0x41000000" if MACH_KOTA2
|
||||
default "0x00000000"
|
||||
---help---
|
||||
@@ -95,7 +118,7 @@ config MEMORY_SIZE
|
||||
hex "Physical memory size"
|
||||
default "0x08000000" if MACH_G3EVM
|
||||
default "0x08000000" if MACH_G4EVM
|
||||
default "0x20000000" if MACH_AG5EVM
|
||||
default "0x20000000" if MACH_AG5EVM || MACH_BONITO
|
||||
default "0x1e000000" if MACH_KOTA2
|
||||
default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
|
||||
default "0x04000000"
|
||||
|
||||
@@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
|
||||
obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
|
||||
|
||||
# SMP objects
|
||||
smp-y := platsmp.o headsmp.o
|
||||
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
||||
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
|
||||
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
|
||||
|
||||
# Pinmux setup
|
||||
pfc-y :=
|
||||
@@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
|
||||
pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
|
||||
pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
|
||||
pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
|
||||
pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
|
||||
pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
|
||||
|
||||
# IRQ objects
|
||||
obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
|
||||
|
||||
# PM objects
|
||||
obj-$(CONFIG_SUSPEND) += suspend.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
|
||||
|
||||
# Board objects
|
||||
obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
|
||||
@@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
|
||||
obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
|
||||
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
|
||||
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
|
||||
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
|
||||
|
||||
# Framework support
|
||||
obj-$(CONFIG_SMP) += $(smp-y)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,157 @@
|
||||
/*
|
||||
* marzen board support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
/* SMSC LAN89218 */
|
||||
static struct resource smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x18000000, /* ExCS0 */
|
||||
.end = 0x180000ff, /* A1->A7 */
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(28), /* IRQ 1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_platdata = {
|
||||
.flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
};
|
||||
|
||||
static struct platform_device eth_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_platdata,
|
||||
},
|
||||
.resource = smsc911x_resources,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *marzen_devices[] __initdata = {
|
||||
ð_device,
|
||||
};
|
||||
|
||||
static struct map_desc marzen_io_desc[] __initdata = {
|
||||
/* 2M entity map for 0xf0000000 (MPCORE) */
|
||||
{
|
||||
.virtual = 0xf0000000,
|
||||
.pfn = __phys_to_pfn(0xf0000000),
|
||||
.length = SZ_2M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
|
||||
{
|
||||
.virtual = 0xfe000000,
|
||||
.pfn = __phys_to_pfn(0xfe000000),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
};
|
||||
|
||||
static void __init marzen_map_io(void)
|
||||
{
|
||||
iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
|
||||
}
|
||||
|
||||
static void __init marzen_init_early(void)
|
||||
{
|
||||
r8a7779_add_early_devices();
|
||||
|
||||
/* Early serial console setup is not included here due to
|
||||
* memory map collisions. The SCIF serial ports in r8a7779
|
||||
* are difficult to entity map 1:1 due to collision with the
|
||||
* virtual memory range used by the coherent DMA code on ARM.
|
||||
*
|
||||
* Anyone wanting to debug early can remove UPF_IOREMAP from
|
||||
* the sh-sci serial console platform data, adjust mapbase
|
||||
* to a static M:N virt:phys mapping that needs to be added to
|
||||
* the mappings passed with iotable_init() above.
|
||||
*
|
||||
* Then add a call to shmobile_setup_console() from this function.
|
||||
*
|
||||
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
|
||||
* command line.
|
||||
*/
|
||||
}
|
||||
|
||||
static void __init marzen_init(void)
|
||||
{
|
||||
r8a7779_pinmux_init();
|
||||
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
gpio_request(GPIO_FN_TX2_C, NULL);
|
||||
gpio_request(GPIO_FN_RX2_C, NULL);
|
||||
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
gpio_request(GPIO_FN_TX4, NULL);
|
||||
gpio_request(GPIO_FN_RX4, NULL);
|
||||
|
||||
/* LAN89218 */
|
||||
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
|
||||
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
|
||||
|
||||
r8a7779_add_standard_devices();
|
||||
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
|
||||
}
|
||||
|
||||
static void __init marzen_timer_init(void)
|
||||
{
|
||||
r8a7779_clock_init();
|
||||
shmobile_timer.init();
|
||||
return;
|
||||
}
|
||||
|
||||
struct sys_timer marzen_timer = {
|
||||
.init = marzen_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(MARZEN, "marzen")
|
||||
.map_io = marzen_map_io,
|
||||
.init_early = marzen_init_early,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = r8a7779_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = marzen_init,
|
||||
.timer = &marzen_timer,
|
||||
MACHINE_END
|
||||
@@ -0,0 +1,382 @@
|
||||
/*
|
||||
* R8A7740 processor support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7740.h>
|
||||
|
||||
/*
|
||||
* | MDx | XTAL1/EXTAL1 | System | EXTALR |
|
||||
* Clock |-------+-----------------+ clock | 32.768 | RCLK
|
||||
* Mode | 2/1/0 | src MHz | source | KHz | source
|
||||
* -------+-------+-----------------+-----------+--------+----------
|
||||
* 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
|
||||
* 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
|
||||
* 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
|
||||
* 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
|
||||
* 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
|
||||
* 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
|
||||
* 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
|
||||
* 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
|
||||
*/
|
||||
|
||||
/* CPG registers */
|
||||
#define FRQCRA 0xe6150000
|
||||
#define FRQCRB 0xe6150004
|
||||
#define FRQCRC 0xe61500e0
|
||||
#define PLLC01CR 0xe6150028
|
||||
|
||||
#define SUBCKCR 0xe6150080
|
||||
|
||||
#define MSTPSR0 0xe6150030
|
||||
#define MSTPSR1 0xe6150038
|
||||
#define MSTPSR2 0xe6150040
|
||||
#define MSTPSR3 0xe6150048
|
||||
#define MSTPSR4 0xe615004c
|
||||
#define SMSTPCR0 0xe6150130
|
||||
#define SMSTPCR1 0xe6150134
|
||||
#define SMSTPCR2 0xe6150138
|
||||
#define SMSTPCR3 0xe615013c
|
||||
#define SMSTPCR4 0xe6150140
|
||||
|
||||
/* Fixed 32 KHz root clock from EXTALR pin */
|
||||
static struct clk extalr_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* 25MHz default rate for the EXTAL1 root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk extal1_clk = {
|
||||
.rate = 25000000,
|
||||
};
|
||||
|
||||
/*
|
||||
* 48MHz default rate for the EXTAL2 root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk extal2_clk = {
|
||||
.rate = 48000000,
|
||||
};
|
||||
|
||||
/*
|
||||
* 27MHz default rate for the DV_CLKI root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk dv_clk = {
|
||||
.rate = 27000000,
|
||||
};
|
||||
|
||||
static unsigned long div_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / (int)(clk->priv);
|
||||
}
|
||||
|
||||
static struct clk_ops div_clk_ops = {
|
||||
.recalc = div_recalc,
|
||||
};
|
||||
|
||||
/* extal1 / 2 */
|
||||
static struct clk extal1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 1024 */
|
||||
static struct clk extal1_div1024_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 2 / 1024 */
|
||||
static struct clk extal1_div2048_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_div2_clk,
|
||||
};
|
||||
|
||||
/* extal2 / 2 */
|
||||
static struct clk extal2_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal2_clk,
|
||||
};
|
||||
|
||||
static struct clk_ops followparent_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
};
|
||||
|
||||
/* Main clock */
|
||||
static struct clk system_clk = {
|
||||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
static struct clk system_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &system_clk,
|
||||
};
|
||||
|
||||
/* r_clk */
|
||||
static struct clk r_clk = {
|
||||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
/* PLLC0/PLLC1 */
|
||||
static unsigned long pllc01_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned long mult = 1;
|
||||
|
||||
if (__raw_readl(PLLC01CR) & (1 << 14))
|
||||
mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
|
||||
|
||||
return clk->parent->rate * mult;
|
||||
}
|
||||
|
||||
static struct clk_ops pllc01_clk_ops = {
|
||||
.recalc = pllc01_recalc,
|
||||
};
|
||||
|
||||
static struct clk pllc0_clk = {
|
||||
.ops = &pllc01_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &system_clk,
|
||||
.enable_reg = (void __iomem *)FRQCRC,
|
||||
};
|
||||
|
||||
static struct clk pllc1_clk = {
|
||||
.ops = &pllc01_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &system_div2_clk,
|
||||
.enable_reg = (void __iomem *)FRQCRA,
|
||||
};
|
||||
|
||||
/* PLLC1 / 2 */
|
||||
static struct clk pllc1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &pllc1_clk,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&extalr_clk,
|
||||
&extal1_clk,
|
||||
&extal2_clk,
|
||||
&extal1_div2_clk,
|
||||
&extal1_div1024_clk,
|
||||
&extal1_div2048_clk,
|
||||
&extal2_div2_clk,
|
||||
&dv_clk,
|
||||
&system_clk,
|
||||
&system_div2_clk,
|
||||
&r_clk,
|
||||
&pllc0_clk,
|
||||
&pllc1_clk,
|
||||
&pllc1_div2_clk,
|
||||
};
|
||||
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting */
|
||||
value = __raw_readl(FRQCRB);
|
||||
value |= (1 << 31);
|
||||
__raw_writel(value, FRQCRB);
|
||||
}
|
||||
|
||||
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
|
||||
24, 32, 36, 48, 0, 72, 96, 0 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
.kick = div4_kick,
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
|
||||
DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_NR
|
||||
};
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
|
||||
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
|
||||
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
|
||||
[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV6_SUB,
|
||||
DIV6_NR
|
||||
};
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
||||
MSTP230,
|
||||
MSTP222,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
|
||||
MSTP329, MSTP323,
|
||||
|
||||
MSTP_NR
|
||||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
|
||||
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
|
||||
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
|
||||
[MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
|
||||
[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("extalr", &extalr_clk),
|
||||
CLKDEV_CON_ID("extal1", &extal1_clk),
|
||||
CLKDEV_CON_ID("extal2", &extal2_clk),
|
||||
CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
|
||||
CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
|
||||
CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
|
||||
CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
|
||||
CLKDEV_CON_ID("dv_clk", &dv_clk),
|
||||
CLKDEV_CON_ID("system_clk", &system_clk),
|
||||
CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
|
||||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
|
||||
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
|
||||
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
|
||||
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
|
||||
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
|
||||
CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
|
||||
CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
|
||||
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
|
||||
CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
|
||||
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
|
||||
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
|
||||
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
|
||||
};
|
||||
|
||||
void __init r8a7740_clock_init(u8 md_ck)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
/* detect system clock parent */
|
||||
if (md_ck & MD_CK1)
|
||||
system_clk.parent = &extal1_div2_clk;
|
||||
else
|
||||
system_clk.parent = &extal1_clk;
|
||||
|
||||
/* detect RCLK parent */
|
||||
switch (md_ck & (MD_CK2 | MD_CK1)) {
|
||||
case MD_CK2 | MD_CK1:
|
||||
r_clk.parent = &extal1_div2048_clk;
|
||||
break;
|
||||
case MD_CK2:
|
||||
r_clk.parent = &extal1_div1024_clk;
|
||||
break;
|
||||
case MD_CK1:
|
||||
default:
|
||||
r_clk.parent = &extalr_clk;
|
||||
break;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7740 clocks\n");
|
||||
}
|
||||
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
* r8a7779 clock framework support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define FRQMR 0xffc80014
|
||||
#define MSTPCR0 0xffc80030
|
||||
#define MSTPCR1 0xffc80034
|
||||
#define MSTPCR3 0xffc8003c
|
||||
#define MSTPSR1 0xffc80044
|
||||
#define MSTPSR4 0xffc80048
|
||||
#define MSTPSR6 0xffc8004c
|
||||
#define MSTPCR4 0xffc80050
|
||||
#define MSTPCR5 0xffc80054
|
||||
#define MSTPCR6 0xffc80058
|
||||
#define MSTPCR7 0xffc80040
|
||||
|
||||
/* ioremap() through clock mapping mandatory to avoid
|
||||
* collision with ARM coherent DMA virtual memory range.
|
||||
*/
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = 0xffc80000,
|
||||
.len = 0x80,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk plla_clk = {
|
||||
.rate = 1500000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&plla_clk,
|
||||
};
|
||||
|
||||
static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
|
||||
0x0018, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
|
||||
0x0700, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
|
||||
0x0040, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
|
||||
0x0010, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
|
||||
0x0060, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
|
||||
0x0300, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
|
||||
MSTP016, MSTP015, MSTP014,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
|
||||
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
|
||||
};
|
||||
|
||||
static unsigned long mul4_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * 4;
|
||||
}
|
||||
|
||||
static struct clk_ops mul4_clk_ops = {
|
||||
.recalc = mul4_recalc,
|
||||
};
|
||||
|
||||
struct clk clkz_clk = {
|
||||
.ops = &mul4_clk_ops,
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
struct clk clkzs_clk = {
|
||||
/* clks x 4 / 4 = clks */
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
static struct clk *late_main_clks[] = {
|
||||
&clkz_clk,
|
||||
&clkzs_clk,
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("plla_clk", &plla_clk),
|
||||
CLKDEV_CON_ID("clkz_clk", &clkz_clk),
|
||||
CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
|
||||
CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
|
||||
CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
|
||||
CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
|
||||
};
|
||||
|
||||
void __init r8a7779_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
|
||||
ret = clk_register(late_main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7779 clocks\n");
|
||||
}
|
||||
@@ -14,7 +14,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
__INIT
|
||||
__CPUINIT
|
||||
|
||||
/*
|
||||
* Reset vector for secondary CPUs.
|
||||
|
||||
@@ -12,14 +12,43 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
static cpumask_t dead_cpus;
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
return 1;
|
||||
int k;
|
||||
|
||||
/* this function is running on another CPU than the offline target,
|
||||
* here we need wait for shutdown code in platform_cpu_die() to
|
||||
* finish before asking SoC-specific code to power off the CPU core.
|
||||
*/
|
||||
for (k = 0; k < 1000; k++) {
|
||||
if (cpumask_test_cpu(cpu, &dead_cpus))
|
||||
return shmobile_platform_cpu_kill(cpu);
|
||||
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
/* hardware shutdown code running on the CPU that is being offlined */
|
||||
flush_cache_all();
|
||||
dsb();
|
||||
|
||||
/* notify platform_cpu_kill() that hardware shutdown is finished */
|
||||
cpumask_set_cpu(cpu, &dead_cpus);
|
||||
|
||||
/* wait for SoC code in platform_cpu_kill() to shut off CPU core
|
||||
* power. CPU bring up starts from the reset vector.
|
||||
*/
|
||||
while (1) {
|
||||
/*
|
||||
* here's the WFI
|
||||
@@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
|
||||
|
||||
int platform_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
cpumask_clear_cpu(cpu, &dead_cpus);
|
||||
/*
|
||||
* we don't allow CPU 0 to be shutdown (it is still too special
|
||||
* e.g. clock tick interrupts)
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
extern struct sys_timer shmobile_timer;
|
||||
extern void shmobile_setup_console(void);
|
||||
extern void shmobile_secondary_vector(void);
|
||||
extern int shmobile_platform_cpu_kill(unsigned int cpu);
|
||||
struct clk;
|
||||
extern int clk_init(void);
|
||||
extern void shmobile_handle_irq_intc(struct pt_regs *);
|
||||
@@ -54,4 +55,23 @@ extern void sh73a0_secondary_init(unsigned int cpu);
|
||||
extern int sh73a0_boot_secondary(unsigned int cpu);
|
||||
extern void sh73a0_smp_prepare_cpus(void);
|
||||
|
||||
extern void r8a7740_init_irq(void);
|
||||
extern void r8a7740_add_early_devices(void);
|
||||
extern void r8a7740_add_standard_devices(void);
|
||||
extern void r8a7740_clock_init(u8 md_ck);
|
||||
extern void r8a7740_pinmux_init(void);
|
||||
|
||||
extern void r8a7779_init_irq(void);
|
||||
extern void r8a7779_add_early_devices(void);
|
||||
extern void r8a7779_add_standard_devices(void);
|
||||
extern void r8a7779_clock_init(void);
|
||||
extern void r8a7779_pinmux_init(void);
|
||||
extern void r8a7779_pm_init(void);
|
||||
|
||||
extern unsigned int r8a7779_get_core_count(void);
|
||||
extern int r8a7779_platform_cpu_kill(unsigned int cpu);
|
||||
extern void r8a7779_secondary_init(unsigned int cpu);
|
||||
extern int r8a7779_boot_secondary(unsigned int cpu);
|
||||
extern void r8a7779_smp_prepare_cpus(void);
|
||||
|
||||
#endif /* __ARCH_MACH_COMMON_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,363 @@
|
||||
#ifndef __ASM_R8A7779_H__
|
||||
#define __ASM_R8A7779_H__
|
||||
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/pm_domain.h>
|
||||
|
||||
/* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function
|
||||
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
|
||||
*/
|
||||
enum {
|
||||
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
|
||||
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
|
||||
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
|
||||
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
|
||||
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
|
||||
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
|
||||
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
|
||||
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
|
||||
|
||||
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
|
||||
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
|
||||
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
|
||||
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
|
||||
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
|
||||
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
|
||||
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
|
||||
GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
|
||||
|
||||
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
|
||||
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
|
||||
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
|
||||
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
|
||||
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
|
||||
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
|
||||
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
|
||||
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
|
||||
|
||||
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
|
||||
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
|
||||
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
|
||||
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
|
||||
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
|
||||
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
|
||||
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
|
||||
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
|
||||
|
||||
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
|
||||
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
|
||||
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
|
||||
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
|
||||
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
|
||||
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
|
||||
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
|
||||
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
|
||||
|
||||
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
|
||||
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
|
||||
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
|
||||
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
|
||||
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
|
||||
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
|
||||
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
|
||||
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
|
||||
|
||||
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
|
||||
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
|
||||
GPIO_GP_6_8,
|
||||
|
||||
GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
|
||||
GPIO_FN_A19,
|
||||
|
||||
/* IPSR0 */
|
||||
GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
|
||||
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
|
||||
GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
|
||||
GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
|
||||
GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
|
||||
GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
|
||||
GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
|
||||
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
|
||||
GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
|
||||
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
|
||||
GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
|
||||
GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
|
||||
GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
|
||||
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
|
||||
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
|
||||
GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
|
||||
|
||||
/* IPSR1 */
|
||||
GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
|
||||
GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
|
||||
GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
|
||||
GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
|
||||
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
|
||||
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
|
||||
GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
|
||||
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
|
||||
GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
|
||||
GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
|
||||
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
|
||||
GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
|
||||
GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
|
||||
GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
|
||||
GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
|
||||
GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
|
||||
GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
|
||||
|
||||
/* IPSR2 */
|
||||
GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
|
||||
GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
|
||||
GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
|
||||
GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
|
||||
GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
|
||||
GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
|
||||
GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
|
||||
GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
|
||||
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
|
||||
GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
|
||||
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
|
||||
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
|
||||
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
|
||||
GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
|
||||
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
|
||||
GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
|
||||
GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
|
||||
GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
|
||||
GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
|
||||
GPIO_FN_AUDATA2,
|
||||
|
||||
/* IPSR3 */
|
||||
GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
|
||||
GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
|
||||
GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
|
||||
GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
|
||||
GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
|
||||
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
|
||||
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
|
||||
GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
|
||||
GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
|
||||
GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
|
||||
GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
|
||||
GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
|
||||
GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
|
||||
GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
|
||||
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
|
||||
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
|
||||
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
|
||||
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
|
||||
GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
|
||||
|
||||
/* IPSR4 */
|
||||
GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
|
||||
GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
|
||||
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
|
||||
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
|
||||
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
|
||||
GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
|
||||
GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
|
||||
GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
|
||||
GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
|
||||
GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
|
||||
GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
|
||||
GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
|
||||
GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
|
||||
GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
|
||||
GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
|
||||
GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
|
||||
GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
|
||||
GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
|
||||
GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
|
||||
|
||||
/* IPSR5 */
|
||||
GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
|
||||
GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
|
||||
GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
|
||||
GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
|
||||
GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
|
||||
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
|
||||
GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
|
||||
GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
|
||||
GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
|
||||
GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
|
||||
GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
|
||||
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
|
||||
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
|
||||
GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
|
||||
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
|
||||
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
|
||||
GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
|
||||
GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
|
||||
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
|
||||
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
|
||||
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
|
||||
GPIO_FN_MOUT0,
|
||||
|
||||
/* IPSR6 */
|
||||
GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
|
||||
GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
|
||||
GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
|
||||
GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
|
||||
GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
|
||||
GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
|
||||
GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
|
||||
GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
|
||||
GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
|
||||
GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
|
||||
GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
|
||||
GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
|
||||
GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
|
||||
GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
|
||||
GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
|
||||
GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
|
||||
|
||||
/* IPSR7 */
|
||||
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
|
||||
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
|
||||
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
|
||||
GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
|
||||
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
|
||||
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
|
||||
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
|
||||
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
|
||||
GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
|
||||
GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
|
||||
GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
|
||||
GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
|
||||
GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
|
||||
GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
|
||||
GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
|
||||
GPIO_FN_CTS1_B,
|
||||
|
||||
/* IPSR8 */
|
||||
GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
|
||||
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
|
||||
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
|
||||
GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
|
||||
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
|
||||
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
|
||||
GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
|
||||
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
|
||||
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
|
||||
GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
|
||||
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
|
||||
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
|
||||
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
|
||||
GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
|
||||
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
|
||||
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
|
||||
GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
|
||||
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
|
||||
GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
|
||||
|
||||
/* IPSR9 */
|
||||
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
|
||||
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
|
||||
GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
|
||||
GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
|
||||
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
|
||||
GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
|
||||
GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
|
||||
GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
|
||||
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
|
||||
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
|
||||
GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
|
||||
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
|
||||
GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
|
||||
GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
|
||||
GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
|
||||
GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
|
||||
GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
|
||||
|
||||
/* IPSR10 */
|
||||
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
|
||||
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
|
||||
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
|
||||
GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
|
||||
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
|
||||
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
|
||||
GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
|
||||
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
|
||||
GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
|
||||
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
|
||||
GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
|
||||
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
|
||||
GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
|
||||
GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
|
||||
GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
|
||||
GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
|
||||
GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
|
||||
GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
|
||||
|
||||
/* IPSR11 */
|
||||
GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
|
||||
GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
|
||||
GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
|
||||
GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
|
||||
GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
|
||||
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
|
||||
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
|
||||
GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
|
||||
GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
|
||||
GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
|
||||
GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
|
||||
GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
|
||||
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
|
||||
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
|
||||
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
|
||||
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
|
||||
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
|
||||
GPIO_FN_HRTS0_B,
|
||||
|
||||
/* IPSR12 */
|
||||
GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
|
||||
GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
|
||||
GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
|
||||
GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
|
||||
GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
|
||||
GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
|
||||
GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
|
||||
GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
|
||||
GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
|
||||
};
|
||||
|
||||
struct platform_device;
|
||||
|
||||
struct r8a7779_pm_ch {
|
||||
unsigned long chan_offs;
|
||||
unsigned int chan_bit;
|
||||
unsigned int isr_bit;
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct r8a7779_pm_ch ch;
|
||||
};
|
||||
|
||||
static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
|
||||
{
|
||||
return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
|
||||
}
|
||||
|
||||
extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern struct r8a7779_pm_domain r8a7779_sh4a;
|
||||
extern struct r8a7779_pm_domain r8a7779_sgx;
|
||||
extern struct r8a7779_pm_domain r8a7779_vdp1;
|
||||
extern struct r8a7779_pm_domain r8a7779_impx3;
|
||||
|
||||
extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
|
||||
extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
|
||||
struct platform_device *pdev);
|
||||
#else
|
||||
#define r8a7779_init_pm_domain(pd) do { } while (0)
|
||||
#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
#endif /* __ASM_R8A7779_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* r8a7779 processor support - INTC hardware block
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define INT2SMSKCR0 0xfe7822a0
|
||||
#define INT2SMSKCR1 0xfe7822a4
|
||||
#define INT2SMSKCR2 0xfe7822a8
|
||||
#define INT2SMSKCR3 0xfe7822ac
|
||||
#define INT2SMSKCR4 0xfe7822b0
|
||||
|
||||
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = __io(0xf0001000);
|
||||
void __iomem *gic_cpu_base = __io(0xf0000100);
|
||||
|
||||
/* use GIC to handle interrupts */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
||||
|
||||
/* unmask all known interrupts in INTCS2 */
|
||||
__raw_writel(0xfffffff0, INT2SMSKCR0);
|
||||
__raw_writel(0xfff7ffff, INT2SMSKCR1);
|
||||
__raw_writel(0xfffbffdf, INT2SMSKCR2);
|
||||
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
||||
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -22,12 +22,16 @@
|
||||
#include <mach/common.h>
|
||||
|
||||
#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
|
||||
#define is_r8a7779() machine_is_marzen()
|
||||
|
||||
static unsigned int __init shmobile_smp_get_core_count(void)
|
||||
{
|
||||
if (is_sh73a0())
|
||||
return sh73a0_get_core_count();
|
||||
|
||||
if (is_r8a7779())
|
||||
return r8a7779_get_core_count();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
@@ -35,6 +39,17 @@ static void __init shmobile_smp_prepare_cpus(void)
|
||||
{
|
||||
if (is_sh73a0())
|
||||
sh73a0_smp_prepare_cpus();
|
||||
|
||||
if (is_r8a7779())
|
||||
r8a7779_smp_prepare_cpus();
|
||||
}
|
||||
|
||||
int shmobile_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
if (is_r8a7779())
|
||||
return r8a7779_platform_cpu_kill(cpu);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void __cpuinit platform_secondary_init(unsigned int cpu)
|
||||
@@ -43,6 +58,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
||||
|
||||
if (is_sh73a0())
|
||||
sh73a0_secondary_init(cpu);
|
||||
|
||||
if (is_r8a7779())
|
||||
r8a7779_secondary_init(cpu);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
@@ -50,6 +68,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
if (is_sh73a0())
|
||||
return sh73a0_boot_secondary(cpu);
|
||||
|
||||
if (is_r8a7779())
|
||||
return r8a7779_boot_secondary(cpu);
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* r8a7779 Power management support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/console.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
|
||||
static void __iomem *r8a7779_sysc_base;
|
||||
|
||||
/* SYSC */
|
||||
#define SYSCSR 0x00
|
||||
#define SYSCISR 0x04
|
||||
#define SYSCISCR 0x08
|
||||
#define SYSCIER 0x0c
|
||||
#define SYSCIMR 0x10
|
||||
#define PWRSR0 0x40
|
||||
#define PWRSR1 0x80
|
||||
#define PWRSR2 0xc0
|
||||
#define PWRSR3 0x100
|
||||
#define PWRSR4 0x140
|
||||
|
||||
#define PWRSR_OFFS 0x00
|
||||
#define PWROFFCR_OFFS 0x04
|
||||
#define PWRONCR_OFFS 0x0c
|
||||
#define PWRER_OFFS 0x14
|
||||
|
||||
#define SYSCSR_RETRIES 100
|
||||
#define SYSCSR_DELAY_US 1
|
||||
|
||||
#define SYSCISR_RETRIES 1000
|
||||
#define SYSCISR_DELAY_US 1
|
||||
|
||||
#if defined(CONFIG_PM) || defined(CONFIG_SMP)
|
||||
|
||||
static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
|
||||
|
||||
static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
|
||||
int sr_bit, int reg_offs)
|
||||
{
|
||||
int k;
|
||||
|
||||
for (k = 0; k < SYSCSR_RETRIES; k++) {
|
||||
if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
|
||||
break;
|
||||
udelay(SYSCSR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCSR_RETRIES)
|
||||
return -EAGAIN;
|
||||
|
||||
iowrite32(1 << r8a7779_ch->chan_bit,
|
||||
r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
|
||||
int (*on_off_fn)(struct r8a7779_pm_ch *))
|
||||
{
|
||||
unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
|
||||
unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
|
||||
unsigned int status;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
spin_lock_irqsave(&r8a7779_sysc_lock, flags);
|
||||
|
||||
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
|
||||
|
||||
do {
|
||||
ret = on_off_fn(r8a7779_ch);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
status = ioread32(r8a7779_sysc_base +
|
||||
r8a7779_ch->chan_offs + PWRER_OFFS);
|
||||
} while (status & chan_mask);
|
||||
|
||||
for (k = 0; k < SYSCISR_RETRIES; k++) {
|
||||
if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
|
||||
break;
|
||||
udelay(SYSCISR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCISR_RETRIES)
|
||||
ret = -EIO;
|
||||
|
||||
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
|
||||
|
||||
pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
|
||||
r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
|
||||
ioread32(r8a7779_sysc_base + PWRSR1),
|
||||
ioread32(r8a7779_sysc_base + PWRSR2),
|
||||
ioread32(r8a7779_sysc_base + PWRSR3),
|
||||
ioread32(r8a7779_sysc_base + PWRSR4), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
|
||||
}
|
||||
|
||||
int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
|
||||
}
|
||||
|
||||
static void __init r8a7779_sysc_init(void)
|
||||
{
|
||||
r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
|
||||
if (!r8a7779_sysc_base)
|
||||
panic("unable to ioremap r8a7779 SYSC hardware block\n");
|
||||
|
||||
/* enable all interrupt sources, but do not use interrupt handler */
|
||||
iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
|
||||
iowrite32(0, r8a7779_sysc_base + SYSCIMR);
|
||||
}
|
||||
|
||||
#else /* CONFIG_PM || CONFIG_SMP */
|
||||
|
||||
static inline void r8a7779_sysc_init(void) {}
|
||||
|
||||
#endif /* CONFIG_PM || CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int pd_power_down(struct generic_pm_domain *genpd)
|
||||
{
|
||||
return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
|
||||
}
|
||||
|
||||
static int pd_power_up(struct generic_pm_domain *genpd)
|
||||
{
|
||||
return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
|
||||
}
|
||||
|
||||
static bool pd_is_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
|
||||
unsigned int st;
|
||||
|
||||
st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
|
||||
if (st & (1 << r8a7779_ch->chan_bit))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool pd_active_wakeup(struct device *dev)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
|
||||
{
|
||||
struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
|
||||
|
||||
pm_genpd_init(genpd, NULL, false);
|
||||
genpd->dev_ops.stop = pm_clk_suspend;
|
||||
genpd->dev_ops.start = pm_clk_resume;
|
||||
genpd->dev_ops.active_wakeup = pd_active_wakeup;
|
||||
genpd->dev_irq_safe = true;
|
||||
genpd->power_off = pd_power_down;
|
||||
genpd->power_on = pd_power_up;
|
||||
|
||||
if (pd_is_off(&r8a7779_pd->genpd))
|
||||
pd_power_up(&r8a7779_pd->genpd);
|
||||
}
|
||||
|
||||
void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
pm_genpd_add_device(&r8a7779_pd->genpd, dev);
|
||||
if (pm_clk_no_clocks(dev))
|
||||
pm_clk_add(dev, NULL);
|
||||
}
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_sh4a = {
|
||||
.ch = {
|
||||
.chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
|
||||
.isr_bit = 16, /* SH4A */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_sgx = {
|
||||
.ch = {
|
||||
.chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
|
||||
.isr_bit = 20, /* SGX */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_vdp1 = {
|
||||
.ch = {
|
||||
.chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
|
||||
.isr_bit = 21, /* VDP */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_impx3 = {
|
||||
.ch = {
|
||||
.chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
|
||||
.isr_bit = 24, /* IMP */
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
void __init r8a7779_pm_init(void)
|
||||
{
|
||||
static int once;
|
||||
|
||||
if (!once++)
|
||||
r8a7779_sysc_init();
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user