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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Fix return value from memcpy [POWERPC] iseries: Define insw et al. so libata/ide will compile [POWERPC] Fix irq enable/disable in smp_generic_take_timebase [POWERPC] Fix problem with time not advancing on 32-bit platforms [POWERPC] Restore copyright notice in arch/powerpc/kernel/fpu.S [POWERPC] Fix up ibm_architecture_vec definition [POWERPC] Make OF irq map code detect more error cases [POWERPC] Support for "weird" MPICs and fixup mpc7448_hpc2 [POWERPC] Fix MPIC sense codes in documentation [POWERPC] Fix performance regression in IRQ radix tree locking [POWERPC] Add mpc7448hpc2 device tree source file [POWERPC] Add MPC8349E MDS device tree source file to arch/powerpc/boot/dts [POWERPC] modify mpc83xx platforms to use new IRQ layer [POWERPC] Adapt ipic driver to new host_ops interface, add set_irq_type to set IRQ sense [POWERPC] back up old school ipic.[hc] to arch/ppc [POWERPC] Use mpc8641hpcn PIC base address from dev tree. [POWERPC] Allow MPC8641 HPCN to build with CONFIG_PCI disabled too. [POWERPC] Fix powerpc 44x_mmu build [POWERPC] Remove flush_dcache_all export
This commit is contained in:
Linus Torvalds
@@ -1136,10 +1136,10 @@ Sense and level information should be encoded as follows:
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Devices connected to openPIC-compatible controllers should encode
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sense and polarity as follows:
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0 = high to low edge sensitive type enabled
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0 = low to high edge sensitive type enabled
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1 = active low level sensitive type enabled
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2 = low to high edge sensitive type enabled
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3 = active high level sensitive type enabled
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2 = active high level sensitive type enabled
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3 = high to low edge sensitive type enabled
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ISA PIC interrupt controllers should adhere to the ISA PIC
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encodings listed below:
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+14
-6
@@ -354,6 +354,7 @@ endchoice
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config PPC_PSERIES
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depends on PPC_MULTIPLATFORM && PPC64
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bool "IBM pSeries & new (POWER5-based) iSeries"
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select MPIC
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select PPC_I8259
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select PPC_RTAS
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select RTAS_ERROR_LOGGING
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@@ -363,6 +364,7 @@ config PPC_PSERIES
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config PPC_CHRP
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bool "Common Hardware Reference Platform (CHRP) based machines"
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depends on PPC_MULTIPLATFORM && PPC32
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select MPIC
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select PPC_I8259
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select PPC_INDIRECT_PCI
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select PPC_RTAS
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@@ -373,6 +375,7 @@ config PPC_CHRP
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config PPC_PMAC
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bool "Apple PowerMac based machines"
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depends on PPC_MULTIPLATFORM
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select MPIC
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select PPC_INDIRECT_PCI if PPC32
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select PPC_MPC106 if PPC32
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default y
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@@ -380,6 +383,7 @@ config PPC_PMAC
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config PPC_PMAC64
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bool
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depends on PPC_PMAC && POWER4
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select MPIC
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select U3_DART
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select MPIC_BROKEN_U3
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select GENERIC_TBSYNC
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@@ -389,6 +393,7 @@ config PPC_PMAC64
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config PPC_PREP
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bool "PowerPC Reference Platform (PReP) based machines"
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depends on PPC_MULTIPLATFORM && PPC32 && BROKEN
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select MPIC
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select PPC_I8259
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select PPC_INDIRECT_PCI
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select PPC_UDBG_16550
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@@ -397,6 +402,7 @@ config PPC_PREP
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config PPC_MAPLE
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depends on PPC_MULTIPLATFORM && PPC64
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bool "Maple 970FX Evaluation Board"
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select MPIC
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select U3_DART
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select MPIC_BROKEN_U3
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select GENERIC_TBSYNC
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@@ -439,12 +445,6 @@ config U3_DART
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depends on PPC_MULTIPLATFORM && PPC64
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default n
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config MPIC
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depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
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|| MPC7448HPC2
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bool
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default y
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config PPC_RTAS
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bool
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default n
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@@ -812,6 +812,14 @@ config GENERIC_ISA_DMA
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depends on PPC64 || POWER4 || 6xx && !CPM2
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default y
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config MPIC
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bool
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default n
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config MPIC_WEIRD
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bool
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default n
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config PPC_I8259
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bool
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default n
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@@ -0,0 +1,190 @@
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/*
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* MPC7448HPC2 (Taiga) board Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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* 2006 Roy Zang <Roy Zang at freescale.com>.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "mpc7448hpc2";
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compatible = "mpc74xx";
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#address-cells = <1>;
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#size-cells = <1>;
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linux,phandle = <100>;
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells =<0>;
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linux,phandle = <200>;
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PowerPC,7448@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K bytes
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i-cache-size = <8000>; // L1, 32K bytes
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timebase-frequency = <0>; // 33 MHz, from uboot
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clock-frequency = <0>; // From U-Boot
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bus-frequency = <0>; // From U-Boot
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32-bit;
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linux,phandle = <201>;
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linux,boot-cpu;
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};
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};
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memory {
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device_type = "memory";
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linux,phandle = <300>;
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reg = <00000000 20000000 // DDR2 512M at 0
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>;
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};
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tsi108@c0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "tsi-bridge";
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ranges = <00000000 c0000000 00010000>;
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reg = <c0000000 00010000>;
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bus-frequency = <0>;
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i2c@7000 {
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interrupt-parent = <7400>;
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interrupts = <E 0>;
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reg = <7000 400>;
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device_type = "i2c";
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compatible = "tsi-i2c";
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};
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mdio@6000 {
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device_type = "mdio";
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compatible = "tsi-ethernet";
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ethernet-phy@6000 {
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linux,phandle = <6000>;
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interrupt-parent = <7400>;
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interrupts = <2 1>;
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reg = <6000 50>;
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phy-id = <8>;
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device_type = "ethernet-phy";
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};
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ethernet-phy@6400 {
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linux,phandle = <6400>;
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interrupt-parent = <7400>;
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interrupts = <2 1>;
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reg = <6000 50>;
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phy-id = <9>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@6200 {
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#size-cells = <0>;
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device_type = "network";
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model = "TSI-ETH";
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compatible = "tsi-ethernet";
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reg = <6000 200>;
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address = [ 00 06 D2 00 00 01 ];
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interrupts = <10 2>;
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interrupt-parent = <7400>;
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phy-handle = <6000>;
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};
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ethernet@6600 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSI-ETH";
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compatible = "tsi-ethernet";
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reg = <6400 200>;
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address = [ 00 06 D2 00 00 02 ];
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interrupts = <11 2>;
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interrupt-parent = <7400>;
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phy-handle = <6400>;
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};
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serial@7808 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <7808 200>;
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clock-frequency = <3f6b5a00>;
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interrupts = <c 0>;
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interrupt-parent = <7400>;
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};
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serial@7c08 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <7c08 200>;
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clock-frequency = <3f6b5a00>;
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interrupts = <d 0>;
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interrupt-parent = <7400>;
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};
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pic@7400 {
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linux,phandle = <7400>;
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <7400 400>;
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built-in;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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pci@1000 {
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compatible = "tsi10x";
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device_type = "pci";
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linux,phandle = <1000>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <1000 1000>;
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bus-range = <0 0>;
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ranges = <02000000 0 e0000000 e0000000 0 1A000000
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01000000 0 00000000 fa000000 0 00010000>;
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clock-frequency = <7f28154>;
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interrupt-parent = <7400>;
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interrupts = <17 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0800 0 0 1 7400 24 0
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0800 0 0 2 7400 25 0
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0800 0 0 3 7400 26 0
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0800 0 0 4 7400 27 0
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/* IDSEL 0x12 */
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1000 0 0 1 7400 25 0
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1000 0 0 2 7400 26 0
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1000 0 0 3 7400 27 0
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1000 0 0 4 7400 24 0
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/* IDSEL 0x13 */
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1800 0 0 1 7400 26 0
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1800 0 0 2 7400 27 0
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1800 0 0 3 7400 24 0
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1800 0 0 4 7400 25 0
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/* IDSEL 0x14 */
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2000 0 0 1 7400 27 0
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2000 0 0 2 7400 24 0
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2000 0 0 3 7400 25 0
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2000 0 0 4 7400 26 0
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>;
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};
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};
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};
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@@ -0,0 +1,328 @@
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/*
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* MPC8349E MDS Device Tree Source
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*
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* Copyright 2005, 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8349EMDS";
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compatible = "MPC834xMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8349@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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32-bit;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 10000000>; // 256MB at 0
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};
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soc8349@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = <700>;
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dfsrr;
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};
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i2c@3100 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3100 100>;
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interrupts = <f 8>;
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interrupt-parent = <700>;
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dfsrr;
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};
|
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spi@7000 {
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device_type = "spi";
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compatible = "mpc83xx_spi";
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reg = <7000 1000>;
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interrupts = <10 8>;
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interrupt-parent = <700>;
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mode = <0>;
|
||||
};
|
||||
|
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/* phy type (ULPI or SERIAL) are only types supportted for MPH */
|
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/* port = 0 or 1 */
|
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usb@22000 {
|
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device_type = "usb";
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compatible = "fsl-usb2-mph";
|
||||
reg = <22000 1000>;
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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interrupt-parent = <700>;
|
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interrupts = <27 2>;
|
||||
phy_type = "ulpi";
|
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port1;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
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usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <700>;
|
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interrupts = <26 2>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linux,phandle = <24520>;
|
||||
ethernet-phy@0 {
|
||||
linux,phandle = <2452000>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <11 2>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
ethernet-phy@1 {
|
||||
linux,phandle = <2452001>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <12 2>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <20 8 21 8 22 8>;
|
||||
interrupt-parent = <700>;
|
||||
phy-handle = <2452000>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 8 24 8 25 8>;
|
||||
interrupt-parent = <700>;
|
||||
phy-handle = <2452001>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = <700>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = <700>;
|
||||
};
|
||||
|
||||
pci@8500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
8800 0 0 1 700 14 8
|
||||
8800 0 0 2 700 15 8
|
||||
8800 0 0 3 700 16 8
|
||||
8800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
9000 0 0 1 700 16 8
|
||||
9000 0 0 2 700 17 8
|
||||
9000 0 0 3 700 14 8
|
||||
9000 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
9800 0 0 1 700 17 8
|
||||
9800 0 0 2 700 14 8
|
||||
9800 0 0 3 700 15 8
|
||||
9800 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
a800 0 0 1 700 14 8
|
||||
a800 0 0 2 700 15 8
|
||||
a800 0 0 3 700 16 8
|
||||
a800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
b000 0 0 1 700 17 8
|
||||
b000 0 0 2 700 14 8
|
||||
b000 0 0 3 700 15 8
|
||||
b000 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
b800 0 0 1 700 16 8
|
||||
b800 0 0 2 700 17 8
|
||||
b800 0 0 3 700 14 8
|
||||
b800 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
b000 0 0 1 700 15 8
|
||||
b000 0 0 2 700 16 8
|
||||
b000 0 0 3 700 17 8
|
||||
b000 0 0 4 700 14 8>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8500 100>;
|
||||
compatible = "83xx";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@8600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
8800 0 0 1 700 14 8
|
||||
8800 0 0 2 700 15 8
|
||||
8800 0 0 3 700 16 8
|
||||
8800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
9000 0 0 1 700 16 8
|
||||
9000 0 0 2 700 17 8
|
||||
9000 0 0 3 700 14 8
|
||||
9000 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
9800 0 0 1 700 17 8
|
||||
9800 0 0 2 700 14 8
|
||||
9800 0 0 3 700 15 8
|
||||
9800 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
a800 0 0 1 700 14 8
|
||||
a800 0 0 2 700 15 8
|
||||
a800 0 0 3 700 16 8
|
||||
a800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
b000 0 0 1 700 17 8
|
||||
b000 0 0 2 700 14 8
|
||||
b000 0 0 3 700 15 8
|
||||
b000 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
b800 0 0 1 700 16 8
|
||||
b800 0 0 2 700 17 8
|
||||
b800 0 0 3 700 14 8
|
||||
b800 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
b000 0 0 1 700 15 8
|
||||
b000 0 0 2 700 16 8
|
||||
b000 0 0 3 700 17 8
|
||||
b000 0 0 4 700 14 8>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 b0000000 b0000000 0 10000000
|
||||
42000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 e2100000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8600 100>;
|
||||
compatible = "83xx";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = <700>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
pic@700 {
|
||||
linux,phandle = <700>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
built-in;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -2,6 +2,11 @@
|
||||
* FPU support code, moved here from head.S so that it can be used
|
||||
* by chips which use other head-whatever.S files.
|
||||
*
|
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
||||
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
|
||||
* Copyright (C) 1996 Paul Mackerras.
|
||||
* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
|
||||
+66
-18
@@ -322,7 +322,8 @@ EXPORT_SYMBOL(do_softirq);
|
||||
|
||||
static LIST_HEAD(irq_hosts);
|
||||
static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED;
|
||||
|
||||
static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
|
||||
static unsigned int irq_radix_writer;
|
||||
struct irq_map_entry irq_map[NR_IRQS];
|
||||
static unsigned int irq_virq_count = NR_IRQS;
|
||||
static struct irq_host *irq_default_host;
|
||||
@@ -455,6 +456,58 @@ void irq_set_virq_count(unsigned int count)
|
||||
irq_virq_count = count;
|
||||
}
|
||||
|
||||
/* radix tree not lockless safe ! we use a brlock-type mecanism
|
||||
* for now, until we can use a lockless radix tree
|
||||
*/
|
||||
static void irq_radix_wrlock(unsigned long *flags)
|
||||
{
|
||||
unsigned int cpu, ok;
|
||||
|
||||
spin_lock_irqsave(&irq_big_lock, *flags);
|
||||
irq_radix_writer = 1;
|
||||
smp_mb();
|
||||
do {
|
||||
barrier();
|
||||
ok = 1;
|
||||
for_each_possible_cpu(cpu) {
|
||||
if (per_cpu(irq_radix_reader, cpu)) {
|
||||
ok = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!ok)
|
||||
cpu_relax();
|
||||
} while(!ok);
|
||||
}
|
||||
|
||||
static void irq_radix_wrunlock(unsigned long flags)
|
||||
{
|
||||
smp_wmb();
|
||||
irq_radix_writer = 0;
|
||||
spin_unlock_irqrestore(&irq_big_lock, flags);
|
||||
}
|
||||
|
||||
static void irq_radix_rdlock(unsigned long *flags)
|
||||
{
|
||||
local_irq_save(*flags);
|
||||
__get_cpu_var(irq_radix_reader) = 1;
|
||||
smp_mb();
|
||||
if (likely(irq_radix_writer == 0))
|
||||
return;
|
||||
__get_cpu_var(irq_radix_reader) = 0;
|
||||
smp_wmb();
|
||||
spin_lock(&irq_big_lock);
|
||||
__get_cpu_var(irq_radix_reader) = 1;
|
||||
spin_unlock(&irq_big_lock);
|
||||
}
|
||||
|
||||
static void irq_radix_rdunlock(unsigned long flags)
|
||||
{
|
||||
__get_cpu_var(irq_radix_reader) = 0;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
||||
unsigned int irq_create_mapping(struct irq_host *host,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
@@ -604,13 +657,9 @@ void irq_dispose_mapping(unsigned int virq)
|
||||
/* Check if radix tree allocated yet */
|
||||
if (host->revmap_data.tree.gfp_mask == 0)
|
||||
break;
|
||||
/* XXX radix tree not safe ! remove lock whem it becomes safe
|
||||
* and use some RCU sync to make sure everything is ok before we
|
||||
* can re-use that map entry
|
||||
*/
|
||||
spin_lock_irqsave(&irq_big_lock, flags);
|
||||
irq_radix_wrlock(&flags);
|
||||
radix_tree_delete(&host->revmap_data.tree, hwirq);
|
||||
spin_unlock_irqrestore(&irq_big_lock, flags);
|
||||
irq_radix_wrunlock(flags);
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -677,25 +726,24 @@ unsigned int irq_radix_revmap(struct irq_host *host,
|
||||
if (tree->gfp_mask == 0)
|
||||
return irq_find_mapping(host, hwirq);
|
||||
|
||||
/* XXX Current radix trees are NOT SMP safe !!! Remove that lock
|
||||
* when that is fixed (when Nick's patch gets in
|
||||
*/
|
||||
spin_lock_irqsave(&irq_big_lock, flags);
|
||||
|
||||
/* Now try to resolve */
|
||||
irq_radix_rdlock(&flags);
|
||||
ptr = radix_tree_lookup(tree, hwirq);
|
||||
irq_radix_rdunlock(flags);
|
||||
|
||||
/* Found it, return */
|
||||
if (ptr) {
|
||||
virq = ptr - irq_map;
|
||||
goto bail;
|
||||
return virq;
|
||||
}
|
||||
|
||||
/* If not there, try to insert it */
|
||||
virq = irq_find_mapping(host, hwirq);
|
||||
if (virq != NO_IRQ)
|
||||
if (virq != NO_IRQ) {
|
||||
irq_radix_wrlock(&flags);
|
||||
radix_tree_insert(tree, hwirq, &irq_map[virq]);
|
||||
bail:
|
||||
spin_unlock_irqrestore(&irq_big_lock, flags);
|
||||
irq_radix_wrunlock(flags);
|
||||
}
|
||||
return virq;
|
||||
}
|
||||
|
||||
@@ -806,12 +854,12 @@ static int irq_late_init(void)
|
||||
struct irq_host *h;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&irq_big_lock, flags);
|
||||
irq_radix_wrlock(&flags);
|
||||
list_for_each_entry(h, &irq_hosts, link) {
|
||||
if (h->revmap_type == IRQ_HOST_MAP_TREE)
|
||||
INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC);
|
||||
}
|
||||
spin_unlock_irqrestore(&irq_big_lock, flags);
|
||||
irq_radix_wrunlock(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1289,6 +1289,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
|
||||
|
||||
DBG("Try to map irq for %s...\n", pci_name(pci_dev));
|
||||
|
||||
#ifdef DEBUG
|
||||
memset(&oirq, 0xff, sizeof(oirq));
|
||||
#endif
|
||||
/* Try to get a mapping from the device-tree */
|
||||
if (of_irq_map_pci(pci_dev, &oirq)) {
|
||||
u8 line, pin;
|
||||
@@ -1314,8 +1317,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
|
||||
if (virq != NO_IRQ)
|
||||
set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
|
||||
} else {
|
||||
DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
|
||||
oirq.size, oirq.specifier[0], oirq.controller->full_name);
|
||||
DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
|
||||
oirq.size, oirq.specifier[0], oirq.specifier[1],
|
||||
oirq.controller->full_name);
|
||||
|
||||
virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
|
||||
oirq.size);
|
||||
@@ -1324,6 +1328,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
|
||||
DBG(" -> failed to map !\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
DBG(" -> mapped to linux irq %d\n", virq);
|
||||
|
||||
pci_dev->irq = virq;
|
||||
pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
|
||||
|
||||
|
||||
@@ -126,10 +126,6 @@ EXPORT_SYMBOL(pci_bus_mem_base_phys);
|
||||
EXPORT_SYMBOL(pci_bus_to_hose);
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
EXPORT_SYMBOL(flush_dcache_all);
|
||||
#endif
|
||||
|
||||
EXPORT_SYMBOL(start_thread);
|
||||
EXPORT_SYMBOL(kernel_thread);
|
||||
|
||||
|
||||
@@ -646,13 +646,13 @@ static unsigned char ibm_architecture_vec[] = {
|
||||
5 - 1, /* 5 option vectors */
|
||||
|
||||
/* option vector 1: processor architectures supported */
|
||||
3 - 1, /* length */
|
||||
3 - 2, /* length */
|
||||
0, /* don't ignore, don't halt */
|
||||
OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
|
||||
OV1_PPC_2_04 | OV1_PPC_2_05,
|
||||
|
||||
/* option vector 2: Open Firmware options supported */
|
||||
34 - 1, /* length */
|
||||
34 - 2, /* length */
|
||||
OV2_REAL_MODE,
|
||||
0, 0,
|
||||
W(0xffffffff), /* real_base */
|
||||
@@ -666,16 +666,16 @@ static unsigned char ibm_architecture_vec[] = {
|
||||
48, /* max log_2(hash table size) */
|
||||
|
||||
/* option vector 3: processor options supported */
|
||||
3 - 1, /* length */
|
||||
3 - 2, /* length */
|
||||
0, /* don't ignore, don't halt */
|
||||
OV3_FP | OV3_VMX,
|
||||
|
||||
/* option vector 4: IBM PAPR implementation */
|
||||
2 - 1, /* length */
|
||||
2 - 2, /* length */
|
||||
0, /* don't halt */
|
||||
|
||||
/* option vector 5: PAPR/OF options */
|
||||
3 - 1, /* length */
|
||||
3 - 2, /* length */
|
||||
0, /* don't ignore, don't halt */
|
||||
OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES,
|
||||
};
|
||||
|
||||
@@ -639,14 +639,17 @@ void of_irq_map_init(unsigned int flags)
|
||||
|
||||
}
|
||||
|
||||
int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
|
||||
struct of_irq *out_irq)
|
||||
int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 ointsize,
|
||||
u32 *addr, struct of_irq *out_irq)
|
||||
{
|
||||
struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
|
||||
u32 *tmp, *imap, *imask;
|
||||
u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
|
||||
int imaplen, match, i;
|
||||
|
||||
DBG("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
|
||||
parent->full_name, intspec[0], intspec[1], ointsize);
|
||||
|
||||
ipar = of_node_get(parent);
|
||||
|
||||
/* First get the #interrupt-cells property of the current cursor
|
||||
@@ -670,6 +673,9 @@ int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
|
||||
|
||||
DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
|
||||
|
||||
if (ointsize != intsize)
|
||||
return -EINVAL;
|
||||
|
||||
/* Look for this #address-cells. We have to implement the old linux
|
||||
* trick of looking for the parent here as some device-trees rely on it
|
||||
*/
|
||||
@@ -875,12 +881,15 @@ int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq
|
||||
}
|
||||
intsize = *tmp;
|
||||
|
||||
DBG(" intsize=%d intlen=%d\n", intsize, intlen);
|
||||
|
||||
/* Check index */
|
||||
if ((index + 1) * intsize > intlen)
|
||||
return -EINVAL;
|
||||
|
||||
/* Get new specifier and map it */
|
||||
res = of_irq_map_raw(p, intspec + index * intsize, addr, out_irq);
|
||||
res = of_irq_map_raw(p, intspec + index * intsize, intsize,
|
||||
addr, out_irq);
|
||||
of_node_put(p);
|
||||
return res;
|
||||
}
|
||||
@@ -965,7 +974,7 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
|
||||
laddr[0] = (pdev->bus->number << 16)
|
||||
| (pdev->devfn << 8);
|
||||
laddr[1] = laddr[2] = 0;
|
||||
return of_irq_map_raw(ppnode, &lspec, laddr, out_irq);
|
||||
return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_irq_map_pci);
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
@@ -45,8 +45,9 @@ void __devinit smp_generic_take_timebase(void)
|
||||
{
|
||||
int cmd;
|
||||
u64 tb;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_disable();
|
||||
local_irq_save(flags);
|
||||
while (!running)
|
||||
barrier();
|
||||
rmb();
|
||||
@@ -70,7 +71,7 @@ void __devinit smp_generic_take_timebase(void)
|
||||
set_tb(tb >> 32, tb & 0xfffffffful);
|
||||
enter_contest(tbsync->mark, -1);
|
||||
}
|
||||
local_irq_enable();
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static int __devinit start_contest(int cmd, long offset, int num)
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
.align 7
|
||||
_GLOBAL(memcpy)
|
||||
std r3,48(r1) /* save destination pointer for return value */
|
||||
mtcrf 0x01,r5
|
||||
cmpldi cr1,r5,16
|
||||
neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
|
||||
@@ -38,7 +39,7 @@ _GLOBAL(memcpy)
|
||||
stdu r9,16(r3)
|
||||
bdnz 1b
|
||||
3: std r8,8(r3)
|
||||
beqlr
|
||||
beq 3f
|
||||
addi r3,r3,16
|
||||
ld r9,8(r4)
|
||||
.Ldo_tail:
|
||||
@@ -53,7 +54,8 @@ _GLOBAL(memcpy)
|
||||
2: bf cr7*4+3,3f
|
||||
rotldi r9,r9,8
|
||||
stb r9,0(r3)
|
||||
3: blr
|
||||
3: ld r3,48(r1) /* return dest pointer */
|
||||
blr
|
||||
|
||||
.Lsrc_unaligned:
|
||||
srdi r6,r5,3
|
||||
@@ -115,7 +117,7 @@ _GLOBAL(memcpy)
|
||||
5: srd r12,r9,r11
|
||||
or r12,r8,r12
|
||||
std r12,24(r3)
|
||||
beqlr
|
||||
beq 4f
|
||||
cmpwi cr1,r5,8
|
||||
addi r3,r3,32
|
||||
sld r9,r9,r10
|
||||
@@ -167,4 +169,5 @@ _GLOBAL(memcpy)
|
||||
3: bf cr7*4+3,4f
|
||||
lbz r0,0(r4)
|
||||
stb r0,0(r3)
|
||||
4: blr
|
||||
4: ld r3,48(r1) /* return dest pointer */
|
||||
blr
|
||||
|
||||
@@ -103,7 +103,7 @@ unsigned long __init mmu_mapin_ram(void)
|
||||
|
||||
/* Determine number of entries necessary to cover lowmem */
|
||||
pinned_tlbs = (unsigned int)
|
||||
(_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT);
|
||||
(_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
|
||||
|
||||
/* Write upper watermark to save location */
|
||||
tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
|
||||
@@ -111,7 +111,7 @@ unsigned long __init mmu_mapin_ram(void)
|
||||
/* If necessary, set additional pinned TLBs */
|
||||
if (pinned_tlbs > 1)
|
||||
for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
|
||||
unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE;
|
||||
unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
|
||||
ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
|
||||
}
|
||||
|
||||
|
||||
@@ -46,26 +46,6 @@ unsigned long isa_io_base = 0;
|
||||
unsigned long isa_mem_base = 0;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int
|
||||
mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
|
||||
{
|
||||
static char pci_irq_table[][4] =
|
||||
/*
|
||||
* PCI IDSEL/INTPIN->INTLINE
|
||||
* A B C D
|
||||
*/
|
||||
{
|
||||
{PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x0e */
|
||||
{PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x0f */
|
||||
{PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x10 */
|
||||
};
|
||||
|
||||
const long min_idsel = 0x0e, max_idsel = 0x10, irqs_per_slot = 4;
|
||||
return PCI_IRQ_TABLE_LOOKUP;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* ************************************************************************
|
||||
*
|
||||
* Setup the architecture
|
||||
@@ -92,8 +72,6 @@ static void __init mpc834x_itx_setup_arch(void)
|
||||
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
|
||||
add_bridge(np);
|
||||
|
||||
ppc_md.pci_swizzle = common_swizzle;
|
||||
ppc_md.pci_map_irq = mpc83xx_map_irq;
|
||||
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
|
||||
#endif
|
||||
|
||||
@@ -106,25 +84,13 @@ static void __init mpc834x_itx_setup_arch(void)
|
||||
|
||||
void __init mpc834x_itx_init_IRQ(void)
|
||||
{
|
||||
u8 senses[8] = {
|
||||
0, /* EXT 0 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 1 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 2 */
|
||||
0, /* EXT 3 */
|
||||
#ifdef CONFIG_PCI
|
||||
IRQ_SENSE_LEVEL, /* EXT 4 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 5 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 6 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 7 */
|
||||
#else
|
||||
0, /* EXT 4 */
|
||||
0, /* EXT 5 */
|
||||
0, /* EXT 6 */
|
||||
0, /* EXT 7 */
|
||||
#endif
|
||||
};
|
||||
struct device_node *np;
|
||||
|
||||
ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
|
||||
np = of_find_node_by_type(NULL, "ipic");
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
ipic_init(np, 0);
|
||||
|
||||
/* Initialize the default interrupt mapping priorities,
|
||||
* in case the boot rom changed something on us.
|
||||
@@ -153,4 +119,7 @@ define_machine(mpc834x_itx) {
|
||||
.time_init = mpc83xx_time_init,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup = mpc83xx_pcibios_fixup,
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -43,33 +43,6 @@ unsigned long isa_io_base = 0;
|
||||
unsigned long isa_mem_base = 0;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static int
|
||||
mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
|
||||
{
|
||||
static char pci_irq_table[][4] =
|
||||
/*
|
||||
* PCI IDSEL/INTPIN->INTLINE
|
||||
* A B C D
|
||||
*/
|
||||
{
|
||||
{PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
|
||||
{PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
|
||||
{PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
|
||||
{0, 0, 0, 0},
|
||||
{PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
|
||||
{PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
|
||||
{PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
|
||||
{PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
|
||||
{0, 0, 0, 0}, /* idsel 0x19 */
|
||||
{0, 0, 0, 0}, /* idsel 0x20 */
|
||||
};
|
||||
|
||||
const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
|
||||
return PCI_IRQ_TABLE_LOOKUP;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* ************************************************************************
|
||||
*
|
||||
* Setup the architecture
|
||||
@@ -96,8 +69,6 @@ static void __init mpc834x_sys_setup_arch(void)
|
||||
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
|
||||
add_bridge(np);
|
||||
|
||||
ppc_md.pci_swizzle = common_swizzle;
|
||||
ppc_md.pci_map_irq = mpc83xx_map_irq;
|
||||
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
|
||||
#endif
|
||||
|
||||
@@ -110,25 +81,13 @@ static void __init mpc834x_sys_setup_arch(void)
|
||||
|
||||
void __init mpc834x_sys_init_IRQ(void)
|
||||
{
|
||||
u8 senses[8] = {
|
||||
0, /* EXT 0 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 1 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 2 */
|
||||
0, /* EXT 3 */
|
||||
#ifdef CONFIG_PCI
|
||||
IRQ_SENSE_LEVEL, /* EXT 4 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 5 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 6 */
|
||||
IRQ_SENSE_LEVEL, /* EXT 7 */
|
||||
#else
|
||||
0, /* EXT 4 */
|
||||
0, /* EXT 5 */
|
||||
0, /* EXT 6 */
|
||||
0, /* EXT 7 */
|
||||
#endif
|
||||
};
|
||||
struct device_node *np;
|
||||
|
||||
ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
|
||||
np = of_find_node_by_type(NULL, "ipic");
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
ipic_init(np, 0);
|
||||
|
||||
/* Initialize the default interrupt mapping priorities,
|
||||
* in case the boot rom changed something on us.
|
||||
@@ -178,4 +137,7 @@ define_machine(mpc834x_sys) {
|
||||
.time_init = mpc83xx_time_init,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup = mpc83xx_pcibios_fixup,
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
extern int add_bridge(struct device_node *dev);
|
||||
extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
|
||||
extern void mpc83xx_pcibios_fixup(void);
|
||||
extern void mpc83xx_restart(char *cmd);
|
||||
extern long mpc83xx_time_init(void);
|
||||
|
||||
|
||||
@@ -45,6 +45,15 @@ int mpc83xx_exclude_device(u_char bus, u_char devfn)
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void __init mpc83xx_pcibios_fixup(void)
|
||||
{
|
||||
struct pci_dev *dev = NULL;
|
||||
|
||||
/* map all the PCI irqs */
|
||||
for_each_pci_dev(dev)
|
||||
pci_read_irq_line(dev);
|
||||
}
|
||||
|
||||
int __init add_bridge(struct device_node *dev)
|
||||
{
|
||||
int len;
|
||||
|
||||
@@ -52,6 +52,7 @@ unsigned long pci_dram_offset = 0;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
@@ -60,40 +61,43 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
|
||||
generic_handle_irq(cascade_irq, regs);
|
||||
desc->chip->eoi(irq);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
void __init
|
||||
mpc86xx_hpcn_init_irq(void)
|
||||
{
|
||||
struct mpic *mpic1;
|
||||
struct device_node *np, *cascade_node = NULL;
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
#ifdef CONFIG_PCI
|
||||
struct device_node *cascade_node = NULL;
|
||||
int cascade_irq;
|
||||
phys_addr_t openpic_paddr;
|
||||
#endif
|
||||
|
||||
/* Determine PIC address. */
|
||||
np = of_find_node_by_type(NULL, "open-pic");
|
||||
if (np == NULL)
|
||||
return;
|
||||
|
||||
/* Determine the Physical Address of the OpenPIC regs */
|
||||
openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
|
||||
of_address_to_resource(np, 0, &res);
|
||||
|
||||
/* Alloc mpic structure and per isu has 16 INT entries. */
|
||||
mpic1 = mpic_alloc(np, openpic_paddr,
|
||||
mpic1 = mpic_alloc(np, res.start,
|
||||
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
|
||||
16, NR_IRQS - 4,
|
||||
" MPIC ");
|
||||
BUG_ON(mpic1 == NULL);
|
||||
|
||||
mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10000);
|
||||
mpic_assign_isu(mpic1, 0, res.start + 0x10000);
|
||||
|
||||
/* 48 Internal Interrupts */
|
||||
mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10200);
|
||||
mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10400);
|
||||
mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10600);
|
||||
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
|
||||
mpic_assign_isu(mpic1, 2, res.start + 0x10400);
|
||||
mpic_assign_isu(mpic1, 3, res.start + 0x10600);
|
||||
|
||||
/* 16 External interrupts
|
||||
* Moving them from [0 - 15] to [64 - 79]
|
||||
*/
|
||||
mpic_assign_isu(mpic1, 4, openpic_paddr + 0x10000);
|
||||
mpic_assign_isu(mpic1, 4, res.start + 0x10000);
|
||||
|
||||
mpic_init(mpic1);
|
||||
|
||||
|
||||
@@ -188,7 +188,8 @@ int __init add_bridge(struct device_node *dev)
|
||||
|
||||
printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
|
||||
"Firmware bus number: %d->%d\n",
|
||||
rsrc.start, hose->first_busno, hose->last_busno);
|
||||
(unsigned long) rsrc.start,
|
||||
hose->first_busno, hose->last_busno);
|
||||
|
||||
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
|
||||
hose, hose->cfg_addr, hose->cfg_data);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user